diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt | 373 |
1 files changed, 189 insertions, 184 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 3373b2092..896e43907 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.559967 # Number of seconds simulated -sim_ticks 559966999500 # Number of ticks simulated -final_tick 559966999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.559962 # Number of seconds simulated +sim_ticks 559961514500 # Number of ticks simulated +final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 393705 # Simulator instruction rate (inst/s) -host_op_rate 393705 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237364888 # Simulator tick rate (ticks/s) -host_mem_usage 245892 # Number of bytes of host memory used -host_seconds 2359.10 # Real time elapsed on the host +host_inst_rate 343254 # Simulator instruction rate (inst/s) +host_op_rate 343254 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 206945650 # Simulator tick rate (ticks/s) +host_mem_usage 305268 # Number of bytes of host memory used +host_seconds 2705.84 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -23,33 +23,33 @@ system.physmem.num_reads::cpu.inst 291519 # Nu system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 33318421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33318421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7621363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7621363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7621363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 33318421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40939784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 33318747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17280 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 270 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 17935 # Per bank write bursts system.physmem.perBankRdBursts::1 18289 # Per bank write bursts system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18248 # Per bank write bursts -system.physmem.perBankRdBursts::4 18163 # Per bank write bursts -system.physmem.perBankRdBursts::5 18239 # Per bank write bursts +system.physmem.perBankRdBursts::3 18250 # Per bank write bursts +system.physmem.perBankRdBursts::4 18167 # Per bank write bursts +system.physmem.perBankRdBursts::5 18240 # Per bank write bursts system.physmem.perBankRdBursts::6 18320 # Per bank write bursts system.physmem.perBankRdBursts::7 18299 # Per bank write bursts system.physmem.perBankRdBursts::8 18230 # Per bank write bursts @@ -59,7 +59,7 @@ system.physmem.perBankRdBursts::11 18391 # Pe system.physmem.perBankRdBursts::12 18259 # Per bank write bursts system.physmem.perBankRdBursts::13 18042 # Per bank write bursts system.physmem.perBankRdBursts::14 17977 # Per bank write bursts -system.physmem.perBankRdBursts::15 18106 # Per bank write bursts +system.physmem.perBankRdBursts::15 18101 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -78,7 +78,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 559966923500 # Total gap between requests +system.physmem.totGap 559961438500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -93,8 +93,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.912664 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.833166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 269.609760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39535 37.79% 37.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43904 41.96% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8672 8.29% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 695 0.66% 88.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 728 0.70% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 763 0.73% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1332 1.27% 91.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 808 0.77% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8193 7.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.196437 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.192949 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.958027 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes @@ -221,12 +221,12 @@ system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Wr system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2990654250 # Total ticks spent queuing -system.physmem.totMemAccLat 8451573000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456245000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10268.38 # Average queueing delay per DRAM burst +system.physmem.totQLat 2985206750 # Total ticks spent queuing +system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29018.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s @@ -237,35 +237,40 @@ system.physmem.busUtilRead 0.26 # Da system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 202814 # Number of row buffer hits during reads -system.physmem.writeRowHits 50461 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 1563271.35 # Average gap between requests -system.physmem.pageHitRate 70.76 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 275670988500 # Time in different power states -system.physmem.memoryStateTime::REF 18698420000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 265594606500 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 393989400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 396952920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 214974375 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 216591375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 1136974800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 1134400800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 216438480 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 215550720 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 36574109520 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 36574109520 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 108415975050 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 108760602465 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 240876668250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 240574363500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 387829129875 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 387872571300 # Total energy per rank (pJ) -system.physmem.averagePower::0 692.596540 # Core power per rank (mW) -system.physmem.averagePower::1 692.674119 # Core power per rank (mW) +system.physmem.readRowHits 202789 # Number of row buffer hits during reads +system.physmem.writeRowHits 50437 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes +system.physmem.avgGap 1563256.04 # Average gap between requests +system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.597962 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states +system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.677886 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 125749069 # Number of BP lookups system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect @@ -309,24 +314,24 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1119933999 # number of cpu cycles simulated +system.cpu.numCycles 1119923029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.205800 # CPI: cycles per instruction -system.cpu.ipc 0.829325 # IPC: instructions per cycle -system.cpu.tickCycles 1060170405 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59763594 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.205788 # CPI: cycles per instruction +system.cpu.ipc 0.829333 # IPC: instructions per cycle +system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.890193 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890193 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 4092.890165 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -354,14 +359,14 @@ system.cpu.dcache.demand_misses::cpu.inst 849082 # n system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 849082 # number of overall misses system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23415653250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23415653250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9042894000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9042894000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 32458547250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32458547250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 32458547250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32458547250 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 32445902750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 98301200 # number of WriteReq accesses(hits+misses) @@ -378,14 +383,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.002618 system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32890.433245 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32890.433245 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65932.892463 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65932.892463 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38227.812214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38227.812214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38227.812214 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 32892.515616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 65829.890706 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 38212.920248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,14 +417,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21914188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21914188000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4452805750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4452805750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26366993750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26366993750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26366993750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26366993750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 26361393250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for WriteReq accesses @@ -428,22 +433,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.002407 system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30794.919177 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30794.919177 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64523.130371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64523.130371 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33776.643613 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33776.643613 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 33769.469261 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10606 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.447542 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447542 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id @@ -467,12 +472,12 @@ system.cpu.icache.demand_misses::cpu.inst 12350 # n system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses system.cpu.icache.overall_misses::total 12350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333735500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333735500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333735500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333735500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 333735500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 333735500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 333924000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 333924000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 333924000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses @@ -485,12 +490,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27023.117409 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27023.117409 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27023.117409 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27023.117409 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27023.117409 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27038.380567 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27038.380567 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27038.380567 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27038.380567 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,41 +510,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12350 system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 307779500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 307779500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307779500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 307779500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307968000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 307968000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307968000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 307968000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307968000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 307968000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24921.417004 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24921.417004 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24921.417004 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24921.417004 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24936.680162 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24936.680162 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 258740 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32601.453126 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32601.451844 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 523849 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2865.906217 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.546909 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2865.934205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 29735.517639 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.907456 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2657 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses @@ -562,14 +567,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 291520 # system.cpu.l2cache.demand_misses::total 291520 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 291520 # number of overall misses system.cpu.l2cache.overall_misses::total 291520 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16507068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16507068000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4360106750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4360106750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20867174750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20867174750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20867174750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20867174750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16508718500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4353044250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20861762750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20861762750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20861762750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) @@ -588,14 +593,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.367627 system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.367627 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73405.527515 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73405.527515 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65422.863681 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65422.863681 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71580.593956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71580.593956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71580.593956 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -614,14 +619,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 291520 system.cpu.l2cache.demand_mshr_misses::total 291520 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 291520 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13668599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13668599500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3526847250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3526847250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17195446750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17195446750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17195446750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17195446750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17190059750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.310615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.965716 # mshr miss rate for ReadExReq accesses @@ -630,14 +635,14 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.367627 system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.367627 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60783.099500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60783.099500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52919.907720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52919.907720 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58985.478698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58985.478698 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution @@ -666,7 +671,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # La system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222199250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution @@ -688,9 +693,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 975509000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2745284750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |