diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 1614 |
1 files changed, 804 insertions, 810 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 72a187780..f6b6cbb05 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.276414 # Number of seconds simulated -sim_ticks 276414065500 # Number of ticks simulated -final_tick 276414065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.174766 # Number of seconds simulated +sim_ticks 174766258500 # Number of ticks simulated +final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168860 # Simulator instruction rate (inst/s) -host_op_rate 168860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55408638 # Simulator tick rate (ticks/s) -host_mem_usage 309496 # Number of bytes of host memory used -host_seconds 4988.65 # Real time elapsed on the host +host_inst_rate 293073 # Simulator instruction rate (inst/s) +host_op_rate 293073 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60802944 # Simulator tick rate (ticks/s) +host_mem_usage 263360 # Number of bytes of host memory used +host_seconds 2874.31 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 172736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18523584 # Number of bytes read from this memory -system.physmem.bytes_read::total 18696320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 172736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 172736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289431 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292130 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 624918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 67013898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67638816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 624918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 624918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15439562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15439562 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15439562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 624918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 67013898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 83078377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292130 # Number of read requests accepted -system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292130 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18675136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21184 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18696320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory +system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 174016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 174016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory +system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2719 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289447 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292166 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 995707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 105996479 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 106992186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 995707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 995707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 24419176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24419176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24419176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 995707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 105996479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 131411362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292166 # Number of read requests accepted +system.physmem.writeReqs 66682 # Number of write requests accepted +system.physmem.readBursts 292166 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 18677824 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265792 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18698624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18006 # Per bank write bursts -system.physmem.perBankRdBursts::1 18321 # Per bank write bursts -system.physmem.perBankRdBursts::2 18379 # Per bank write bursts -system.physmem.perBankRdBursts::3 18333 # Per bank write bursts -system.physmem.perBankRdBursts::4 18240 # Per bank write bursts -system.physmem.perBankRdBursts::5 18219 # Per bank write bursts -system.physmem.perBankRdBursts::6 18314 # Per bank write bursts -system.physmem.perBankRdBursts::7 18303 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18223 # Per bank write bursts -system.physmem.perBankRdBursts::10 18219 # Per bank write bursts -system.physmem.perBankRdBursts::11 18380 # Per bank write bursts -system.physmem.perBankRdBursts::12 18258 # Per bank write bursts -system.physmem.perBankRdBursts::13 18122 # Per bank write bursts -system.physmem.perBankRdBursts::14 18052 # Per bank write bursts -system.physmem.perBankRdBursts::15 18198 # Per bank write bursts +system.physmem.perBankRdBursts::1 18334 # Per bank write bursts +system.physmem.perBankRdBursts::2 18382 # Per bank write bursts +system.physmem.perBankRdBursts::3 18340 # Per bank write bursts +system.physmem.perBankRdBursts::4 18235 # Per bank write bursts +system.physmem.perBankRdBursts::5 18233 # Per bank write bursts +system.physmem.perBankRdBursts::6 18311 # Per bank write bursts +system.physmem.perBankRdBursts::7 18302 # Per bank write bursts +system.physmem.perBankRdBursts::8 18233 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18220 # Per bank write bursts +system.physmem.perBankRdBursts::11 18388 # Per bank write bursts +system.physmem.perBankRdBursts::12 18256 # Per bank write bursts +system.physmem.perBankRdBursts::13 18125 # Per bank write bursts +system.physmem.perBankRdBursts::14 18057 # Per bank write bursts +system.physmem.perBankRdBursts::15 18192 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts system.physmem.perBankWrBursts::3 4160 # Per bank write bursts system.physmem.perBankWrBursts::4 4142 # Per bank write bursts system.physmem.perBankWrBursts::5 4099 # Per bank write bursts -system.physmem.perBankWrBursts::6 4262 # Per bank write bursts +system.physmem.perBankWrBursts::6 4261 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4187 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts +system.physmem.perBankWrBursts::9 4180 # Per bank write bursts +system.physmem.perBankWrBursts::10 4148 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,28 +82,28 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 276413976000 # Total gap between requests +system.physmem.totGap 174766169000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292130 # Read request sizes (log2) +system.physmem.readPktSize::6 292166 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 170 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66682 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 215310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,120 +193,124 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 99419 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 230.737062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.797862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.058381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 34339 34.54% 34.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42571 42.82% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9880 9.94% 87.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 767 0.77% 88.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1066 1.07% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 606 0.61% 89.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 182 0.18% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1419 1.43% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8589 8.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 99419 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.841638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.476950 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 763.295063 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 96628 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.414911 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 153.615169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 282.362382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 31544 32.64% 32.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41851 43.31% 75.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11279 11.67% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 407 0.42% 88.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 349 0.36% 88.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 422 0.44% 88.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 656 0.68% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1511 1.56% 91.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8609 8.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 96628 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.731557 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.520071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 729.773377 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 3 0.07% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.443759 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.423618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.831866 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3155 77.82% 77.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 77.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 896 22.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads -system.physmem.totQLat 3656274250 # Total ticks spent queuing -system.physmem.totMemAccLat 9127505500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1458995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12530.11 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.445349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.425120 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.833815 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3151 77.74% 77.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.07% 77.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 896 22.11% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads +system.physmem.totQLat 3659606000 # Total ticks spent queuing +system.physmem.totMemAccLat 9131624750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459205000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12539.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31280.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 67.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.43 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 15.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31289.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 106.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 24.41 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 106.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 24.42 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.65 # Data bus utilization in percentage -system.physmem.busUtilRead 0.53 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 207034 # Number of row buffer hits during reads -system.physmem.writeRowHits 52000 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes -system.physmem.avgGap 770356.64 # Average gap between requests -system.physmem.pageHitRate 72.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 374197320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204175125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139463000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18053880000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80208829935 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 95488658250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 195685642110 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.948810 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 158328598000 # Time in different power states -system.physmem_0.memoryStateTime::REF 9230000000 # Time in different power states +system.physmem.busUtil 1.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.19 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing +system.physmem.readRowHits 209802 # Number of row buffer hits during reads +system.physmem.writeRowHits 52054 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes +system.physmem.avgGap 487020.04 # Average gap between requests +system.physmem.pageHitRate 73.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 364626360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 198952875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1139346000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63677219400 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 49000374750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 126011580585 # Total energy per rank (pJ) +system.physmem_0.averagePower 721.044153 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81102514500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5835700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108853550750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87824440500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 377342280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 205891125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136187000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18053880000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80561309670 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 95179465500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 195729613335 # Total energy per rank (pJ) -system.physmem_1.averagePower 708.107889 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 157816922000 # Time in different power states -system.physmem_1.memoryStateTime::REF 9230000000 # Time in different power states +system.physmem_1.actEnergy 365752800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 199567500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136265000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215479440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63630052470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49041749250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 126003495660 # Total energy per rank (pJ) +system.physmem_1.averagePower 720.997890 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81165303250 # Time in different power states +system.physmem_1.memoryStateTime::REF 5835700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109365226750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192576024 # Number of BP lookups -system.cpu.branchPred.condPredicted 126054494 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11561226 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 137875105 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126274367 # Number of BTB hits +system.cpu.branchPred.lookups 129267026 # Number of BP lookups +system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93510959 # Number of BTB lookups +system.cpu.branchPred.BTBHits 70602364 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.586053 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28678385 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 133 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 75.501700 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19428078 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1137 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 14846480 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 14819636 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 26844 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 242441427 # DTB read hits -system.cpu.dtb.read_misses 312020 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 242753447 # DTB read accesses -system.cpu.dtb.write_hits 135445847 # DTB write hits -system.cpu.dtb.write_misses 31631 # DTB write misses +system.cpu.dtb.read_hits 243602185 # DTB read hits +system.cpu.dtb.read_misses 267667 # DTB read misses +system.cpu.dtb.read_acv 2 # DTB read access violations +system.cpu.dtb.read_accesses 243869852 # DTB read accesses +system.cpu.dtb.write_hits 101634527 # DTB write hits +system.cpu.dtb.write_misses 39608 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135477478 # DTB write accesses -system.cpu.dtb.data_hits 377887274 # DTB hits -system.cpu.dtb.data_misses 343651 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 378230925 # DTB accesses -system.cpu.itb.fetch_hits 194827904 # ITB hits -system.cpu.itb.fetch_misses 239 # ITB misses +system.cpu.dtb.write_accesses 101674135 # DTB write accesses +system.cpu.dtb.data_hits 345236712 # DTB hits +system.cpu.dtb.data_misses 307275 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 345543987 # DTB accesses +system.cpu.itb.fetch_hits 116217608 # ITB hits +system.cpu.itb.fetch_misses 1594 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 194828143 # ITB accesses +system.cpu.itb.fetch_accesses 116219202 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -320,236 +324,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 552828132 # number of cpu cycles simulated +system.cpu.numCycles 349532518 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 198849781 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1637321417 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192576024 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 154952752 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341932468 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 23591048 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6961 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 194827904 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7885927 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 552584882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963022 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176483 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 116536228 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 973715519 # Number of instructions fetch has processed +system.cpu.fetch.Branches 129267026 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 104850078 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 232359516 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 756618 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13025 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 116217608 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 170932 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 349287938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.787716 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.090069 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236070631 42.72% 42.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29638226 5.36% 48.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21699661 3.93% 52.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 35773155 6.47% 58.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67709217 12.25% 70.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21596173 3.91% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19328814 3.50% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3978253 0.72% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 116790752 21.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 152570668 43.68% 43.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 21852908 6.26% 49.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15618674 4.47% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 24569577 7.03% 61.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 38589117 11.05% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 15690770 4.49% 76.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 12536709 3.59% 80.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3990160 1.14% 81.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 63869355 18.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 552584882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.348347 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.961719 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 166809048 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 90546856 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 271205722 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12234440 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11788816 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15468258 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 6932 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1567837184 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 24953 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11788816 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 173694356 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 60697364 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276538556 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29852032 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1529249378 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 8057 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2407484 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 20532473 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7206116 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1021410389 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1760087391 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1720201095 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39886295 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 349287938 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369828 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.785765 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 85729217 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 85771889 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158922951 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18492364 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 371517 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11932000 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 7014 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 968678626 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25475 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 371517 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 93246352 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12124008 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14162 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 169252951 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 74278948 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 966798475 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 812 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 25198716 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 40147884 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7202949 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 666569389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1151537527 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114498375 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 37039151 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 382443231 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1367 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9068503 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 369184759 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 173801249 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40216404 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11112363 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1296784829 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 74 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1011355981 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8787623 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 454402873 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 422535596 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 552584882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.830227 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.913668 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27602231 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 87958062 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 245057270 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 102624029 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 35348443 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4751860 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 877942600 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 76 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 871652294 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 10599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 35560646 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 10943510 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 349287938 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.495512 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.135180 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 197292642 35.70% 35.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 90775823 16.43% 52.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 90545836 16.39% 68.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 58767814 10.64% 79.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 57065281 10.33% 89.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29635375 5.36% 94.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 16880319 3.05% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7509205 1.36% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4112587 0.74% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 75519507 21.62% 21.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 61352705 17.57% 39.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 57497159 16.46% 55.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 51075272 14.62% 70.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 45041028 12.90% 83.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20641156 5.91% 89.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 18147367 5.20% 94.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10284591 2.94% 97.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9729153 2.79% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 552584882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 349287938 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2519786 10.56% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15987276 67.00% 77.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5353537 22.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3589516 19.40% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11788826 63.72% 83.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3123532 16.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 577738940 57.13% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7929 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13232476 1.31% 58.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826543 0.38% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339799 0.33% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 274563490 27.15% 86.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138645524 13.71% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 505111201 57.95% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7850 0.00% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13300877 1.53% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826560 0.44% 59.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339807 0.38% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 244259904 28.02% 88.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 101804815 11.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1011355981 # Type of FU issued -system.cpu.iq.rate 1.829422 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23860599 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023593 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2536933524 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1709848613 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 936642568 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 71011542 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41384153 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34526963 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 998751721 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36463583 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 49725864 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 871652294 # Type of FU issued +system.cpu.iq.rate 2.493766 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18501874 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2041816444 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 876761594 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 835992532 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 69288555 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36778587 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34169821 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 855051836 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 35101056 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 65597329 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 131674162 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1208593 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45366 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 75500049 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7546673 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 37094 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4322829 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2715 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4217 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2714 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4439 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11788816 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 59730385 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 188341 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1470365584 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17995 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 369184759 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 173801249 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 74 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15707 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 184002 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45366 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11555966 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 14467 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11570433 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 973002254 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 242753622 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 38353727 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 371517 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4003286 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 617757 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 966013425 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 16652 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 245057270 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 102624029 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 76 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 538427 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 92920 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 37094 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 128203 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 15937 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 144140 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 871030251 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 243869972 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 622043 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 173580681 # number of nop insts executed -system.cpu.iew.exec_refs 378231388 # number of memory reference insts executed -system.cpu.iew.exec_branches 128483769 # Number of branches executed -system.cpu.iew.exec_stores 135477766 # Number of stores executed -system.cpu.iew.exec_rate 1.760045 # Inst execution rate -system.cpu.iew.wb_sent 971735602 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 971169531 # cumulative count of insts written-back -system.cpu.iew.wb_producers 554965093 # num instructions producing a value -system.cpu.iew.wb_consumers 830941176 # num instructions consuming a value -system.cpu.iew.wb_rate 1.756730 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.667875 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 534547076 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 88070749 # number of nop insts executed +system.cpu.iew.exec_refs 345544428 # number of memory reference insts executed +system.cpu.iew.exec_branches 127159642 # Number of branches executed +system.cpu.iew.exec_stores 101674456 # Number of stores executed +system.cpu.iew.exec_rate 2.491986 # Inst execution rate +system.cpu.iew.wb_sent 870623887 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 870162353 # cumulative count of insts written-back +system.cpu.iew.wb_producers 525000957 # num instructions producing a value +system.cpu.iew.wb_consumers 821946847 # num instructions consuming a value +system.cpu.iew.wb_rate 2.489503 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.638729 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 31811556 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11554519 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 481220935 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.929649 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.612057 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 138434 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 345159794 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.690312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.060061 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 204061483 42.40% 42.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 101508829 21.09% 63.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 52351815 10.88% 74.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25424424 5.28% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 20903892 4.34% 84.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8988981 1.87% 85.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10032197 2.08% 87.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6246270 1.30% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 51703044 10.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 109423104 31.70% 31.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 81928646 23.74% 55.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 29947333 8.68% 64.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19779535 5.73% 69.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 17819278 5.16% 75.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7961935 2.31% 77.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3040960 0.88% 78.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3978860 1.15% 79.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 71280143 20.65% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 481220935 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 345159794 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -595,351 +599,341 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 51703044 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1890031457 # The number of ROB reads -system.cpu.rob.rob_writes 2997634424 # The number of ROB writes -system.cpu.timesIdled 3187 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 243250 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 71280143 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1231657697 # The number of ROB reads +system.cpu.rob.rob_writes 1924928764 # The number of ROB writes +system.cpu.timesIdled 3152 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 244580 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.656268 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.656268 # CPI: Total CPI of All Threads -system.cpu.ipc 1.523768 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.523768 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1234256884 # number of integer regfile reads -system.cpu.int_regfile_writes 703449505 # number of integer regfile writes -system.cpu.fp_regfile_reads 36844868 # number of floating regfile reads -system.cpu.fp_regfile_writes 24462479 # number of floating regfile writes +system.cpu.cpi 0.414933 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.414933 # CPI: Total CPI of All Threads +system.cpu.ipc 2.410025 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.410025 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1104176449 # number of integer regfile reads +system.cpu.int_regfile_writes 635594518 # number of integer regfile writes +system.cpu.fp_regfile_reads 36406853 # number of floating regfile reads +system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777152 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.896824 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288563683 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 369.362460 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 369982500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.896824 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 776668 # number of replacements +system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780764 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 350.748599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 371412500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4091.068449 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998796 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2491 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 582801420 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 582801420 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 191154367 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 191154367 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97409302 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97409302 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 288563669 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 288563669 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 288563669 # number of overall hits -system.cpu.dcache.overall_hits::total 288563669 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1554504 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1554504 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 891898 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 891898 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2446402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2446402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2446402 # number of overall misses -system.cpu.dcache.overall_misses::total 2446402 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83607056000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83607056000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61973215333 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61973215333 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 82500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 82500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145580271333 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145580271333 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145580271333 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145580271333 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 192708871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 192708871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97408623 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 273851866 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 273851866 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 273851866 # number of overall hits +system.cpu.dcache.overall_hits::total 273851866 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1554707 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1554707 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 892577 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 892577 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2447284 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2447284 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2447284 # number of overall misses +system.cpu.dcache.overall_misses::total 2447284 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83708553000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83708553000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61914869831 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61914869831 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145623422831 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145623422831 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145623422831 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145623422831 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177997950 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177997950 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 291010071 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 291010071 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 291010071 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 291010071 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008067 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009073 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009073 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.066667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.066667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008407 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008407 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008407 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008407 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53783.750959 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53783.750959 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69484.644357 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69484.644357 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 82500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 82500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59507.910529 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59507.910529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59507.910529 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59507.910529 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 23437 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 62248 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 339 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.135693 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 120.402321 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 276299150 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 276299150 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 276299150 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 276299150 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008734 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008734 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009080 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009080 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59504.096309 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59504.096309 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22333 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 68716 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.360231 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 132.400771 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88616 # number of writebacks -system.cpu.dcache.writebacks::total 88616 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842060 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 842060 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823094 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 823094 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1665154 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1665154 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1665154 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1665154 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712444 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712444 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68804 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68804 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781248 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781248 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781248 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781248 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24228621500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24228621500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5666649497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5666649497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29895270997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29895270997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29895270997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29895270997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003697 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003697 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002685 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002685 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002685 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002685 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34007.755697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34007.755697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82359.303195 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82359.303195 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38266.044837 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38266.044837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38266.044837 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38266.044837 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 88604 # number of writebacks +system.cpu.dcache.writebacks::total 88604 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842561 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842561 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823959 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 823959 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1666520 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1666520 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1666520 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1666520 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712146 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712146 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68618 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68618 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780764 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780764 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780764 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780764 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24226479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24226479500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5661245497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5661245497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29887724997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29887724997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29887724997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000698 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # 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Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801414 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801414 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1702 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1647.904441 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.804641 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1535 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.831055 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 389662112 # Number of tag accesses -system.cpu.icache.tags.data_accesses 389662112 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 194819661 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 194819661 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 194819661 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 194819661 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 194819661 # number of overall hits -system.cpu.icache.overall_hits::total 194819661 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8243 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8243 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8243 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8243 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8243 # number of overall misses -system.cpu.icache.overall_misses::total 8243 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 351192999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 351192999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 351192999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 351192999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 351192999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 351192999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 194827904 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 194827904 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 194827904 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 194827904 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 194827904 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 194827904 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42604.998059 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42604.998059 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42604.998059 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42604.998059 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42604.998059 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42604.998059 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 510 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses +system.cpu.icache.tags.data_accesses 232441538 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 116209358 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 116209358 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 116209358 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 116209358 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 116209358 # number of overall hits +system.cpu.icache.overall_hits::total 116209358 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8250 # number of overall misses +system.cpu.icache.overall_misses::total 8250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354158499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354158499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354158499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354158499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354158499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354158499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 116217608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 116217608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 116217608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 116217608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 116217608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 116217608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42928.302909 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42928.302909 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42928.302909 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42928.302909 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 738 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.363636 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 4602 # number of writebacks -system.cpu.icache.writebacks::total 4602 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1938 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1938 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1938 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1938 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1938 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1938 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6305 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6305 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6305 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6305 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6305 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6305 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 261344999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 261344999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 261344999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 261344999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261344999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 261344999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41450.436003 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41450.436003 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41450.436003 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41450.436003 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41450.436003 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41450.436003 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 4617 # number of writebacks +system.cpu.icache.writebacks::total 4617 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1927 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1927 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1927 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1927 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1927 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1927 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6323 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6323 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6323 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6323 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6323 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6323 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 263974500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 263974500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 263974500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 263974500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 263974500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 263974500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41748.299858 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41748.299858 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32631.179257 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207901 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292487 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.129760 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259794 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292532 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.126188 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2522.721637 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 62.286398 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30046.171221 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076987 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001901 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.916936 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2634.083249 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.428877 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29874.113923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.080386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.911686 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994160 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32738 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20656900500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20846271500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.968345 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.968345 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.428232 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312733 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312733 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370473 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370935 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.428232 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370473 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370935 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73155.277219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73155.277219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69241.481481 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69241.481481 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70844.251700 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70844.251700 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69241.481481 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71376.241660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71356.511291 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69241.481481 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71376.241660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71356.511291 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970955 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430176 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312888 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.371200 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.371200 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73108.330206 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73108.330206 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69621.691176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69621.691176 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70846.047518 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70846.047518 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1569307 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781754 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 1568372 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 781285 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1989 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1989 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2003 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 718748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68804 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68804 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6305 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712444 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17211 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2356859 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 697984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55671296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56369280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259749 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1047302 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001899 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043538 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 881176 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712146 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17262 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338196 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2355458 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56339648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259794 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1046881 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001913 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.043699 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1045313 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1989 0.19% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1044878 99.81% 99.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2003 0.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1047302 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877871500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9456000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1046881 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 877407000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 9483000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171872499 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225504 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191079 # Transaction distribution -system.membus.trans_dist::ReadExReq 66626 # Transaction distribution -system.membus.trans_dist::ReadExResp 66626 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225504 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842022 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22964032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22964032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadResp 225541 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution +system.membus.trans_dist::CleanEvict 191110 # Transaction distribution +system.membus.trans_dist::ReadExReq 66625 # Transaction distribution +system.membus.trans_dist::ReadExResp 66625 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225541 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842124 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842124 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22966272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 549892 # Request fanout histogram +system.membus.snoop_fanout::samples 549958 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549892 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 549958 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549892 # Request fanout histogram -system.membus.reqLayer0.occupancy 880924000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551641250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_fanout::total 549958 # Request fanout histogram +system.membus.reqLayer0.occupancy 877671500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1551270000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- |