diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha')
16 files changed, 0 insertions, 7577 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 1dc6d91c8..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index 8954fa36f..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,8 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index c97afb693..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28059 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 -592000: 2038558826 -591000: 3948772976 -590000: 439262378 -589000: 329537197 -588000: 3678661972 -587000: 4240182727 -586000: 2283602206 -585000: 1129811410 -584000: 2831949168 -583000: 1224559023 -582000: 3161562107 -581000: 2695467835 -580000: 1234192577 -579000: 1974816198 -578000: 449576701 -577000: 1424873035 -576000: 2370444290 -575000: 1743089134 -574000: 2624046998 -573000: 2071148441 -572000: 2449219691 -571000: 3774476172 -570000: 1111630327 -569000: 121721805 -568000: 2981212266 -567000: 3811833647 -566000: 3676851843 -565000: 1766252334 -564000: 1622887950 -563000: 1684409857 -562000: 1686489387 -561000: 610219569 -560000: 2705092362 -559000: 108031723 -558000: 1316736987 -557000: 2434129258 -556000: 1411819652 -555000: 1173886179 -554000: 3044539233 -553000: 151590417 -552000: 3759426289 -551000: 3451520306 -550000: 294242855 -549000: 890241051 -548000: 876385779 -547000: 119864600 -546000: 3065674956 -545000: 1670853168 -544000: 997261561 -543000: 660227344 -542000: 3132294889 -541000: 521956271 -540000: 1133928405 -539000: 3838154786 -538000: 58624572 -537000: 3544030439 -536000: 432804999 -535000: 1021857051 -534000: 2644812356 -533000: 773094580 -532000: 901027171 -531000: 3976696839 -530000: 4167278216 -529000: 504481120 -528000: 320399857 -527000: 638048690 -526000: 3348998474 -525000: 2660662065 -524000: 2641437803 -523000: 626927006 -522000: 4063917554 -521000: 3212249308 -520000: 2561025301 -519000: 1078140141 -518000: 653939181 -517000: 2154098204 -516000: 3773089676 -515000: 2568381435 -514000: 3838886937 -513000: 941125346 -512000: 1318900410 -511000: 297013287 -510000: 241723934 -509000: 1835499795 -508000: 2309451230 -507000: 1174814430 -506000: 3615943386 -505000: 51034971 -504000: 3950453295 -503000: 4186097241 -502000: 327518343 -501000: 3052462710 -500000: 1586937404 -499000: 2169094819 -498000: 3613195151 -497000: 817359591 -496000: 1470916579 -495000: 2091261583 -494000: 2080080890 -493000: 1772858697 -492000: 2085609872 -491000: 3280632925 -490000: 1689322569 -489000: 2947406469 -488000: 765163324 -487000: 3122594732 -486000: 3385418480 -485000: 1712345567 -484000: 3675825158 -483000: 1558929764 -482000: 2672493410 -481000: 3822528440 -480000: 3741769935 -479000: 2794026235 -478000: 2541364185 -477000: 3964482316 -476000: 1202478165 -475000: 4027617791 -474000: 1905026738 -473000: 2573787636 -472000: 1170529797 -471000: 2272525618 -470000: 820833429 -469000: 3219769529 -468000: 2121197441 -467000: 269331764 -466000: 3038487237 -465000: 2462675338 -464000: 2703163101 -463000: 547052037 -462000: 3454526671 -461000: 2124641794 -460000: 1043737466 -459000: 1785834964 -458000: 3312335313 -457000: 1213835042 -456000: 3099430685 -455000: 3003350806 -454000: 3646781335 -453000: 1474165966 -452000: 705795987 -451000: 2723908407 -450000: 1323056304 -449000: 1157256530 -448000: 4077983523 -447000: 3189085703 -446000: 2241002747 -445000: 3229050072 -444000: 3500150226 -443000: 1290722604 -442000: 1866107725 -441000: 4238277470 -440000: 847346408 -439000: 2474557496 -438000: 2243092317 -437000: 706909230 -436000: 1303503693 -435000: 1456129560 -434000: 1073061079 -433000: 692226634 -432000: 186498656 -431000: 2203415525 -430000: 2183000701 -429000: 1007776545 -428000: 941117387 -427000: 3805851413 -426000: 1474193180 -425000: 4231673903 -424000: 2622576664 -423000: 388097625 -422000: 1165097488 -421000: 3226044518 -420000: 2531461570 -419000: 1509806310 -418000: 2667519114 -417000: 1751592438 -416000: 1286773513 -415000: 1098182293 -414000: 2111912709 -413000: 1230737431 -412000: 4090873946 -411000: 3998652133 -410000: 2486660396 -409000: 2120483596 -408000: 587404533 -407000: 188697995 -406000: 3265346093 -405000: 4234961905 -404000: 1211873901 -403000: 4265173305 -402000: 2208355316 -401000: 3315952806 -400000: 3917328941 -399000: 2523594649 -398000: 3805986783 -397000: 2624925960 -396000: 3716020189 -395000: 2016201122 -394000: 912930261 -393000: 596904160 -392000: 3571173642 -391000: 2290782861 -390000: 1162492227 -389000: 1738718380 -388000: 2599667355 -387000: 2382332909 -386000: 1471269037 -385000: 2238392684 -384000: 4034826126 -383000: 1378654892 -382000: 3702601850 -381000: 397206179 -380000: 2437704230 -379000: 4187604139 -378000: 779452169 -377000: 2010372403 -376000: 531902409 -375000: 1371470602 -374000: 4137796987 -373000: 567426549 -372000: 3082742955 -371000: 2271575596 -370000: 759731212 -369000: 4063369437 -368000: 299356452 -367000: 536656228 -366000: 3014961694 -365000: 3016542135 -364000: 2841873124 -363000: 524434057 -362000: 2887828889 -361000: 3865529589 -360000: 671363647 -359000: 3104594256 -358000: 1502485940 -357000: 1776624159 -356000: 4222478488 -355000: 4127624139 -354000: 2439477793 -353000: 1593794891 -352000: 591275342 -351000: 2177291538 -350000: 1923444781 -349000: 758084193 -348000: 775471359 -347000: 191356974 -346000: 494488375 -345000: 1990489399 -344000: 124118372 -343000: 2046377904 -342000: 1395427716 -341000: 1342299790 -340000: 38145994 -339000: 2291884417 -338000: 351940574 -337000: 3984301480 -336000: 2468666235 -335000: 371500747 -334000: 969922131 -333000: 240854580 -332000: 1644465214 -331000: 1539846168 -330000: 940087216 -329000: 1491329232 -328000: 2281687201 -327000: 3030170550 -326000: 3648503863 -325000: 2037898355 -324000: 174369956 -323000: 2433605668 -322000: 2334905107 -321000: 1597704047 -320000: 302297707 -319000: 3209203690 -318000: 3894539879 -317000: 2868907580 -316000: 2808087076 -315000: 4034586233 -314000: 3694191694 -313000: 2001671958 -312000: 559582279 -311000: 3043016195 -310000: 2785098502 -309000: 4104602138 -308000: 966154914 -307000: 2446376687 -306000: 789956605 -305000: 1708137092 -304000: 1733063901 -303000: 2924555399 -302000: 971356234 -301000: 481382543 -300000: 2647080988 -299000: 4065744916 -298000: 921140 -297000: 654346784 -296000: 485492098 -295000: 217516816 -294000: 4050820137 -293000: 534726686 -292000: 1686691079 -291000: 1316587195 -290000: 3746020838 -289000: 1641967381 -288000: 3492475215 -287000: 3154885393 -286000: 3686450617 -285000: 3589739293 -284000: 3558041700 -283000: 4130142319 -282000: 3132446063 -281000: 982677436 -280000: 799322395 -279000: 151715214 -278000: 3765942871 -277000: 1712470933 -276000: 3807622752 -275000: 4163730108 -274000: 1633425299 -273000: 1654241631 -272000: 1131025394 -271000: 1375475855 -270000: 553294237 -269000: 4091487177 -268000: 2841855980 -267000: 2997369904 -266000: 454385594 -265000: 3757482634 -264000: 3856197465 -263000: 1084605457 -262000: 2552759023 -261000: 3786548799 -260000: 272762545 -259000: 2670277860 -258000: 76233700 -257000: 476168167 -256000: 8969192 -255000: 1998841030 -254000: 1240074303 -253000: 1771564446 -252000: 710374418 -251000: 821383716 -250000: 3157726088 -249000: 3083379502 -248000: 2563632690 -247000: 33723341 -246000: 3303336748 -245000: 4110677892 -244000: 3811702913 -243000: 53856215 -242000: 243571468 -241000: 52177779 -240000: 46805590 -239000: 1622010618 -238000: 1321640849 -237000: 3106837291 -236000: 4102944642 -235000: 137904396 -234000: 339510135 -233000: 88415957 -232000: 3157666382 -231000: 2571005912 -230000: 3586247649 -229000: 4172761781 -228000: 2463305780 -227000: 956927307 -226000: 2169861547 -225000: 1751989251 -224000: 673059158 -223000: 2782464516 -222000: 3741392140 -221000: 2856154963 -220000: 3778376854 -219000: 1538476717 -218000: 2879698522 -217000: 3734645735 -216000: 1899042577 -215000: 371356008 -214000: 2416663698 -213000: 1595919347 -212000: 2816045438 -211000: 132438808 -210000: 1098603890 -209000: 834913667 -208000: 2707567283 -207000: 3154122448 -206000: 3696516104 -205000: 1427952551 -204000: 280496321 -203000: 1185678745 -202000: 3461951699 -201000: 1369208434 -200000: 3900136261 -199000: 870818876 -198000: 327248310 -197000: 3116959470 -196000: 1544241188 -195000: 1568248814 -194000: 2978831302 -193000: 205660429 -192000: 1704239501 -191000: 3570135474 -190000: 3878512103 -189000: 1212729210 -188000: 1873588815 -187000: 324853813 -186000: 432676298 -185000: 1641364437 -184000: 1568401301 -183000: 525792402 -182000: 861154382 -181000: 2357325066 -180000: 3626762590 -179000: 4172125462 -178000: 2108738993 -177000: 2084782857 -176000: 3956924509 -175000: 17183073 -174000: 3676839474 -173000: 458250029 -172000: 2635215219 -171000: 1801029767 -170000: 3602628987 -169000: 370704281 -168000: 177963345 -167000: 924067814 -166000: 3577678376 -165000: 3717789117 -164000: 3285809386 -163000: 3738962897 -162000: 3172510171 -161000: 417992786 -160000: 2591600214 -159000: 3315096579 -158000: 3590763949 -157000: 198872871 -156000: 2960653534 -155000: 2246563682 -154000: 2304045306 -153000: 2647353543 -152000: 2043381015 -151000: 3952056867 -150000: 2644058641 -149000: 3477151018 -148000: 1740210241 -147000: 3314851112 -146000: 1604832482 -145000: 2572410736 -144000: 1965059167 -143000: 889666293 -142000: 1024747903 -141000: 226685285 -140000: 3149168519 -139000: 403638872 -138000: 1725889104 -137000: 1417402331 -136000: 422304488 -135000: 2595894054 -134000: 4266597695 -133000: 1116326556 -132000: 3537080833 -131000: 2181246909 -130000: 1241997223 -129000: 628191304 -128000: 3074132403 -127000: 2112958836 -126000: 1371260930 -125000: 2272975771 -124000: 1379085607 -123000: 1998991877 -122000: 2760271255 -121000: 3784187756 -120000: 311188417 -119000: 1123593459 -118000: 1249155194 -117000: 908703020 -116000: 3765244393 -115000: 3040869794 -114000: 437536659 -113000: 3343598822 -112000: 2419089776 -111000: 1263143640 -110000: 1384687523 -109000: 1727931349 -108000: 2861733388 -107000: 963829093 -106000: 431354627 -105000: 3568623360 -104000: 2957399361 -103000: 1071045618 -102000: 3968457714 -101000: 3448338394 -100000: 2586060251 -99000: 3401651822 -98000: 1579089478 -97000: 3722618916 -96000: 759319595 -95000: 1269278712 -94000: 150489448 -93000: 390013662 -92000: 3663029784 -91000: 555197170 -90000: 166476858 -89000: 1658807720 -88000: 3430520531 -87000: 2946861093 -86000: 3000600326 -85000: 300034452 -84000: 2813719249 -83000: 3009927425 -82000: 1127728469 -81000: 2667791855 -80000: 2632316050 -79000: 2180301200 -78000: 418999983 -77000: 4254858933 -76000: 2728734498 -75000: 1863202698 -74000: 4226419921 -73000: 1917572494 -72000: 3117082625 -71000: 1032601538 -70000: 2992135524 -69000: 670119660 -68000: 638731522 -67000: 1460114012 -66000: 1232274665 -65000: 3667669961 -64000: 191277965 -63000: 3868442802 -62000: 700664540 -61000: 2271087482 -60000: 3274078227 -59000: 159900296 -58000: 2778747772 -57000: 2788477153 -56000: 3965957780 -55000: 2276993918 -54000: 1986966104 -53000: 3416414682 -52000: 2162594060 -51000: 2947744069 -50000: 4024793290 -49000: 631161701 -48000: 728285173 -47000: 1487641693 -46000: 4049519424 -45000: 613160608 -44000: 1566126172 -43000: 3731725133 -42000: 2746368727 -41000: 4168967735 -40000: 1319649932 -39000: 2964978784 -38000: 967937134 -37000: 3116555742 -36000: 2279790642 -35000: 2852914953 -34000: 1040410911 -33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 521167228000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 42592acc9..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,829 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.521167 # Number of seconds simulated -sim_ticks 521167228000 # Number of ticks simulated -final_tick 521167228000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 492017 # Simulator instruction rate (inst/s) -host_op_rate 492017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 276083455 # Simulator tick rate (ticks/s) -host_mem_usage 263220 # Number of bytes of host memory used -host_seconds 1887.72 # Real time elapsed on the host -sim_insts 928789150 # Number of instructions simulated -sim_ops 928789150 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 356861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35537338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35894199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 356861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 356861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8188757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8188757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8188757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 356861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35537338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44082956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292295 # Number of read requests accepted -system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292295 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18686976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18028 # Per bank write bursts -system.physmem.perBankRdBursts::1 18369 # Per bank write bursts -system.physmem.perBankRdBursts::2 18396 # Per bank write bursts -system.physmem.perBankRdBursts::3 18341 # Per bank write bursts -system.physmem.perBankRdBursts::4 18255 # Per bank write bursts -system.physmem.perBankRdBursts::5 18258 # Per bank write bursts -system.physmem.perBankRdBursts::6 18325 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18235 # Per bank write bursts -system.physmem.perBankRdBursts::10 18232 # Per bank write bursts -system.physmem.perBankRdBursts::11 18375 # Per bank write bursts -system.physmem.perBankRdBursts::12 18268 # Per bank write bursts -system.physmem.perBankRdBursts::13 18134 # Per bank write bursts -system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18187 # Per bank write bursts -system.physmem.perBankWrBursts::0 4123 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4221 # Per bank write bursts -system.physmem.perBankWrBursts::3 4157 # Per bank write bursts -system.physmem.perBankWrBursts::4 4141 # Per bank write bursts -system.physmem.perBankWrBursts::5 4097 # Per bank write bursts -system.physmem.perBankWrBursts::6 4260 # Per bank write bursts -system.physmem.perBankWrBursts::7 4224 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4192 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 521167139500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292295 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.106731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.105135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 271.560992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28950 30.16% 30.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41784 43.53% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11694 12.18% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2599 2.71% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 913 0.95% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 756 0.79% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 331 0.34% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 447 0.47% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8515 8.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95989 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.753823 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.637200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 730.740597 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.441539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.421503 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.829633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3159 77.92% 77.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 895 22.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads -system.physmem.totQLat 15194551500 # Total ticks spent queuing -system.physmem.totMemAccLat 20669251500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 52038.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70788.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 35.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 35.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.19 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.34 # Data bus utilization in percentage -system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 210474 # Number of row buffer hits during reads -system.physmem.writeRowHits 52167 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes -system.physmem.avgGap 1451808.02 # Average gap between requests -system.physmem.pageHitRate 73.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341770380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 181632495 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1044360660 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174280140 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 28691395200.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8105258640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1605839040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 57337999170 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 51043667520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 64046185080 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 212592411075 # Total energy per rank (pJ) -system.physmem_0.averagePower 407.915916 # Core power per rank (mW) -system.physmem_0.totalIdleTime 499165974500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3167480750 # Time in different power states -system.physmem_0.memoryStateTime::REF 12206580000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 240498579500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 132926079750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6626927000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 125741581000 # Time in different power states -system.physmem_1.actEnergy 343648200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 182645760 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1040405100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 173653740 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 28803874320.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8196268830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616284320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 57528037740 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 51141308640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 63870409695 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 212914803135 # Total energy per rank (pJ) -system.physmem_1.averagePower 408.534516 # Core power per rank (mW) -system.physmem_1.totalIdleTime 498942805750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3183963500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12254448000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 239604631750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 133180372750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6785962500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 126157849500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851675 # Number of BP lookups -system.cpu.branchPred.condPredicted 79872959 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 686742 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066154 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190152 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.809759 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697401 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 11223 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14052181 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14048615 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3566 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11656 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237539296 # DTB read hits -system.cpu.dtb.read_misses 195211 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305023 # DTB write hits -system.cpu.dtb.write_misses 7170 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312193 # DTB write accesses -system.cpu.dtb.data_hits 335844319 # DTB hits -system.cpu.dtb.data_misses 202381 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046700 # DTB accesses -system.cpu.itb.fetch_hits 286584578 # ITB hits -system.cpu.itb.fetch_misses 119 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584697 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1042334456 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928789150 # Number of instructions committed -system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319598 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.122251 # CPI: cycles per instruction -system.cpu.ipc 0.891066 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction -system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::MemRead 228135214 24.56% 88.39% # Class of committed instruction -system.cpu.op_class_0::MemWrite 94471145 10.17% 98.56% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 9570033 1.03% 99.59% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 3836926 0.41% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962817000 # Number of cycles that the object actually ticked -system.cpu.idleCycles 79517456 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.209717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318705 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320442 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 968708500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.209717 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999075 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999075 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 957 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115675 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115675 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164048 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164048 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318705 # number of overall hits -system.cpu.dcache.overall_hits::total 320318705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137152 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137152 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 848805 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 848805 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 848805 # number of overall misses -system.cpu.dcache.overall_misses::total 848805 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36922839000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36922839000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10957317000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10957317000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 47880156000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 47880156000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 47880156000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 47880156000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167510 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167510 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167510 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167510 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51883.205720 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51883.205720 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79891.777007 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79891.777007 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56408.899571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56408.899571 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks -system.cpu.dcache.writebacks::total 88440 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68141 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68141 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68150 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68150 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68150 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68150 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711644 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711644 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780655 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36210490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36210490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5501688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5501688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41712178500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41712178500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41712178500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41712178500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50882.871913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50882.871913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79721.899407 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79721.899407 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10581 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.101724 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572250 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12327 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23247.525756 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1690.101724 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825245 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825245 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181483 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181483 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572250 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572250 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572250 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286572250 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286572250 # number of overall hits -system.cpu.icache.overall_hits::total 286572250 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12328 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12328 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12328 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12328 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12328 # number of overall misses -system.cpu.icache.overall_misses::total 12328 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 376885500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 376885500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 376885500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 376885500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 376885500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 376885500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286584578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286584578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286584578 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286584578 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286584578 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286584578 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30571.503894 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30571.503894 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30571.503894 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30571.503894 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10581 # number of writebacks -system.cpu.icache.writebacks::total 10581 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12328 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12328 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12328 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 364558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 364558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 364558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 364558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 364558500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 364558500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29571.585010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29571.585010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259984 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32658.667775 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1287369 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292752 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.397473 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 3857784000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51.730334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.865838 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32527.071603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001579 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002437 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.992647 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996663 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2875 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12933736 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12933736 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88440 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88440 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10581 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10581 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488900 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488900 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9421 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491266 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 500687 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9421 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491266 # number of overall hits -system.cpu.l2cache.overall_hits::total 500687 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2907 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2907 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222744 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222744 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289389 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292296 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2907 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289389 # number of overall misses -system.cpu.l2cache.overall_misses::total 292296 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5373301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5373301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 247147500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 247147500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30009565500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30009565500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 247147500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35382867000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35630014500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 247147500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35382867000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35630014500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88440 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88440 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10581 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10581 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12328 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12328 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12328 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780655 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792983 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12328 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792983 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312999 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312999 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.368603 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.368603 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80625.725861 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80625.725861 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85018.059856 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85018.059856 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134726.706443 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134726.706443 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 121897.030750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 121897.030750 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292296 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4706851500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4706851500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 218087500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 218087500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27782125500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27782125500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218087500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32488977000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32707064500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218087500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32488977000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32707064500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368603 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368603 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70625.725861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70625.725861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75021.499828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75021.499828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124726.706443 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124726.706443 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580123 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787140 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1466112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57088192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259984 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052967 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001991 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044571 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050871 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2096 0.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052967 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889082500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18490500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170982500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 550183 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257888 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225650 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191205 # Transaction distribution -system.membus.trans_dist::ReadExReq 66645 # Transaction distribution -system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225650 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842478 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22974592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292295 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292295 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292295 # Request fanout histogram -system.membus.reqLayer0.occupancy 925387500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1555624500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index 49d14f26b..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index 8954fa36f..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,8 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 2bef733aa..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28086 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 -592000: 2038558826 -591000: 3948772976 -590000: 439262378 -589000: 329537197 -588000: 3678661972 -587000: 4240182727 -586000: 2283602206 -585000: 1129811410 -584000: 2831949168 -583000: 1224559023 -582000: 3161562107 -581000: 2695467835 -580000: 1234192577 -579000: 1974816198 -578000: 449576701 -577000: 1424873035 -576000: 2370444290 -575000: 1743089134 -574000: 2624046998 -573000: 2071148441 -572000: 2449219691 -571000: 3774476172 -570000: 1111630327 -569000: 121721805 -568000: 2981212266 -567000: 3811833647 -566000: 3676851843 -565000: 1766252334 -564000: 1622887950 -563000: 1684409857 -562000: 1686489387 -561000: 610219569 -560000: 2705092362 -559000: 108031723 -558000: 1316736987 -557000: 2434129258 -556000: 1411819652 -555000: 1173886179 -554000: 3044539233 -553000: 151590417 -552000: 3759426289 -551000: 3451520306 -550000: 294242855 -549000: 890241051 -548000: 876385779 -547000: 119864600 -546000: 3065674956 -545000: 1670853168 -544000: 997261561 -543000: 660227344 -542000: 3132294889 -541000: 521956271 -540000: 1133928405 -539000: 3838154786 -538000: 58624572 -537000: 3544030439 -536000: 432804999 -535000: 1021857051 -534000: 2644812356 -533000: 773094580 -532000: 901027171 -531000: 3976696839 -530000: 4167278216 -529000: 504481120 -528000: 320399857 -527000: 638048690 -526000: 3348998474 -525000: 2660662065 -524000: 2641437803 -523000: 626927006 -522000: 4063917554 -521000: 3212249308 -520000: 2561025301 -519000: 1078140141 -518000: 653939181 -517000: 2154098204 -516000: 3773089676 -515000: 2568381435 -514000: 3838886937 -513000: 941125346 -512000: 1318900410 -511000: 297013287 -510000: 241723934 -509000: 1835499795 -508000: 2309451230 -507000: 1174814430 -506000: 3615943386 -505000: 51034971 -504000: 3950453295 -503000: 4186097241 -502000: 327518343 -501000: 3052462710 -500000: 1586937404 -499000: 2169094819 -498000: 3613195151 -497000: 817359591 -496000: 1470916579 -495000: 2091261583 -494000: 2080080890 -493000: 1772858697 -492000: 2085609872 -491000: 3280632925 -490000: 1689322569 -489000: 2947406469 -488000: 765163324 -487000: 3122594732 -486000: 3385418480 -485000: 1712345567 -484000: 3675825158 -483000: 1558929764 -482000: 2672493410 -481000: 3822528440 -480000: 3741769935 -479000: 2794026235 -478000: 2541364185 -477000: 3964482316 -476000: 1202478165 -475000: 4027617791 -474000: 1905026738 -473000: 2573787636 -472000: 1170529797 -471000: 2272525618 -470000: 820833429 -469000: 3219769529 -468000: 2121197441 -467000: 269331764 -466000: 3038487237 -465000: 2462675338 -464000: 2703163101 -463000: 547052037 -462000: 3454526671 -461000: 2124641794 -460000: 1043737466 -459000: 1785834964 -458000: 3312335313 -457000: 1213835042 -456000: 3099430685 -455000: 3003350806 -454000: 3646781335 -453000: 1474165966 -452000: 705795987 -451000: 2723908407 -450000: 1323056304 -449000: 1157256530 -448000: 4077983523 -447000: 3189085703 -446000: 2241002747 -445000: 3229050072 -444000: 3500150226 -443000: 1290722604 -442000: 1866107725 -441000: 4238277470 -440000: 847346408 -439000: 2474557496 -438000: 2243092317 -437000: 706909230 -436000: 1303503693 -435000: 1456129560 -434000: 1073061079 -433000: 692226634 -432000: 186498656 -431000: 2203415525 -430000: 2183000701 -429000: 1007776545 -428000: 941117387 -427000: 3805851413 -426000: 1474193180 -425000: 4231673903 -424000: 2622576664 -423000: 388097625 -422000: 1165097488 -421000: 3226044518 -420000: 2531461570 -419000: 1509806310 -418000: 2667519114 -417000: 1751592438 -416000: 1286773513 -415000: 1098182293 -414000: 2111912709 -413000: 1230737431 -412000: 4090873946 -411000: 3998652133 -410000: 2486660396 -409000: 2120483596 -408000: 587404533 -407000: 188697995 -406000: 3265346093 -405000: 4234961905 -404000: 1211873901 -403000: 4265173305 -402000: 2208355316 -401000: 3315952806 -400000: 3917328941 -399000: 2523594649 -398000: 3805986783 -397000: 2624925960 -396000: 3716020189 -395000: 2016201122 -394000: 912930261 -393000: 596904160 -392000: 3571173642 -391000: 2290782861 -390000: 1162492227 -389000: 1738718380 -388000: 2599667355 -387000: 2382332909 -386000: 1471269037 -385000: 2238392684 -384000: 4034826126 -383000: 1378654892 -382000: 3702601850 -381000: 397206179 -380000: 2437704230 -379000: 4187604139 -378000: 779452169 -377000: 2010372403 -376000: 531902409 -375000: 1371470602 -374000: 4137796987 -373000: 567426549 -372000: 3082742955 -371000: 2271575596 -370000: 759731212 -369000: 4063369437 -368000: 299356452 -367000: 536656228 -366000: 3014961694 -365000: 3016542135 -364000: 2841873124 -363000: 524434057 -362000: 2887828889 -361000: 3865529589 -360000: 671363647 -359000: 3104594256 -358000: 1502485940 -357000: 1776624159 -356000: 4222478488 -355000: 4127624139 -354000: 2439477793 -353000: 1593794891 -352000: 591275342 -351000: 2177291538 -350000: 1923444781 -349000: 758084193 -348000: 775471359 -347000: 191356974 -346000: 494488375 -345000: 1990489399 -344000: 124118372 -343000: 2046377904 -342000: 1395427716 -341000: 1342299790 -340000: 38145994 -339000: 2291884417 -338000: 351940574 -337000: 3984301480 -336000: 2468666235 -335000: 371500747 -334000: 969922131 -333000: 240854580 -332000: 1644465214 -331000: 1539846168 -330000: 940087216 -329000: 1491329232 -328000: 2281687201 -327000: 3030170550 -326000: 3648503863 -325000: 2037898355 -324000: 174369956 -323000: 2433605668 -322000: 2334905107 -321000: 1597704047 -320000: 302297707 -319000: 3209203690 -318000: 3894539879 -317000: 2868907580 -316000: 2808087076 -315000: 4034586233 -314000: 3694191694 -313000: 2001671958 -312000: 559582279 -311000: 3043016195 -310000: 2785098502 -309000: 4104602138 -308000: 966154914 -307000: 2446376687 -306000: 789956605 -305000: 1708137092 -304000: 1733063901 -303000: 2924555399 -302000: 971356234 -301000: 481382543 -300000: 2647080988 -299000: 4065744916 -298000: 921140 -297000: 654346784 -296000: 485492098 -295000: 217516816 -294000: 4050820137 -293000: 534726686 -292000: 1686691079 -291000: 1316587195 -290000: 3746020838 -289000: 1641967381 -288000: 3492475215 -287000: 3154885393 -286000: 3686450617 -285000: 3589739293 -284000: 3558041700 -283000: 4130142319 -282000: 3132446063 -281000: 982677436 -280000: 799322395 -279000: 151715214 -278000: 3765942871 -277000: 1712470933 -276000: 3807622752 -275000: 4163730108 -274000: 1633425299 -273000: 1654241631 -272000: 1131025394 -271000: 1375475855 -270000: 553294237 -269000: 4091487177 -268000: 2841855980 -267000: 2997369904 -266000: 454385594 -265000: 3757482634 -264000: 3856197465 -263000: 1084605457 -262000: 2552759023 -261000: 3786548799 -260000: 272762545 -259000: 2670277860 -258000: 76233700 -257000: 476168167 -256000: 8969192 -255000: 1998841030 -254000: 1240074303 -253000: 1771564446 -252000: 710374418 -251000: 821383716 -250000: 3157726088 -249000: 3083379502 -248000: 2563632690 -247000: 33723341 -246000: 3303336748 -245000: 4110677892 -244000: 3811702913 -243000: 53856215 -242000: 243571468 -241000: 52177779 -240000: 46805590 -239000: 1622010618 -238000: 1321640849 -237000: 3106837291 -236000: 4102944642 -235000: 137904396 -234000: 339510135 -233000: 88415957 -232000: 3157666382 -231000: 2571005912 -230000: 3586247649 -229000: 4172761781 -228000: 2463305780 -227000: 956927307 -226000: 2169861547 -225000: 1751989251 -224000: 673059158 -223000: 2782464516 -222000: 3741392140 -221000: 2856154963 -220000: 3778376854 -219000: 1538476717 -218000: 2879698522 -217000: 3734645735 -216000: 1899042577 -215000: 371356008 -214000: 2416663698 -213000: 1595919347 -212000: 2816045438 -211000: 132438808 -210000: 1098603890 -209000: 834913667 -208000: 2707567283 -207000: 3154122448 -206000: 3696516104 -205000: 1427952551 -204000: 280496321 -203000: 1185678745 -202000: 3461951699 -201000: 1369208434 -200000: 3900136261 -199000: 870818876 -198000: 327248310 -197000: 3116959470 -196000: 1544241188 -195000: 1568248814 -194000: 2978831302 -193000: 205660429 -192000: 1704239501 -191000: 3570135474 -190000: 3878512103 -189000: 1212729210 -188000: 1873588815 -187000: 324853813 -186000: 432676298 -185000: 1641364437 -184000: 1568401301 -183000: 525792402 -182000: 861154382 -181000: 2357325066 -180000: 3626762590 -179000: 4172125462 -178000: 2108738993 -177000: 2084782857 -176000: 3956924509 -175000: 17183073 -174000: 3676839474 -173000: 458250029 -172000: 2635215219 -171000: 1801029767 -170000: 3602628987 -169000: 370704281 -168000: 177963345 -167000: 924067814 -166000: 3577678376 -165000: 3717789117 -164000: 3285809386 -163000: 3738962897 -162000: 3172510171 -161000: 417992786 -160000: 2591600214 -159000: 3315096579 -158000: 3590763949 -157000: 198872871 -156000: 2960653534 -155000: 2246563682 -154000: 2304045306 -153000: 2647353543 -152000: 2043381015 -151000: 3952056867 -150000: 2644058641 -149000: 3477151018 -148000: 1740210241 -147000: 3314851112 -146000: 1604832482 -145000: 2572410736 -144000: 1965059167 -143000: 889666293 -142000: 1024747903 -141000: 226685285 -140000: 3149168519 -139000: 403638872 -138000: 1725889104 -137000: 1417402331 -136000: 422304488 -135000: 2595894054 -134000: 4266597695 -133000: 1116326556 -132000: 3537080833 -131000: 2181246909 -130000: 1241997223 -129000: 628191304 -128000: 3074132403 -127000: 2112958836 -126000: 1371260930 -125000: 2272975771 -124000: 1379085607 -123000: 1998991877 -122000: 2760271255 -121000: 3784187756 -120000: 311188417 -119000: 1123593459 -118000: 1249155194 -117000: 908703020 -116000: 3765244393 -115000: 3040869794 -114000: 437536659 -113000: 3343598822 -112000: 2419089776 -111000: 1263143640 -110000: 1384687523 -109000: 1727931349 -108000: 2861733388 -107000: 963829093 -106000: 431354627 -105000: 3568623360 -104000: 2957399361 -103000: 1071045618 -102000: 3968457714 -101000: 3448338394 -100000: 2586060251 -99000: 3401651822 -98000: 1579089478 -97000: 3722618916 -96000: 759319595 -95000: 1269278712 -94000: 150489448 -93000: 390013662 -92000: 3663029784 -91000: 555197170 -90000: 166476858 -89000: 1658807720 -88000: 3430520531 -87000: 2946861093 -86000: 3000600326 -85000: 300034452 -84000: 2813719249 -83000: 3009927425 -82000: 1127728469 -81000: 2667791855 -80000: 2632316050 -79000: 2180301200 -78000: 418999983 -77000: 4254858933 -76000: 2728734498 -75000: 1863202698 -74000: 4226419921 -73000: 1917572494 -72000: 3117082625 -71000: 1032601538 -70000: 2992135524 -69000: 670119660 -68000: 638731522 -67000: 1460114012 -66000: 1232274665 -65000: 3667669961 -64000: 191277965 -63000: 3868442802 -62000: 700664540 -61000: 2271087482 -60000: 3274078227 -59000: 159900296 -58000: 2778747772 -57000: 2788477153 -56000: 3965957780 -55000: 2276993918 -54000: 1986966104 -53000: 3416414682 -52000: 2162594060 -51000: 2947744069 -50000: 4024793290 -49000: 631161701 -48000: 728285173 -47000: 1487641693 -46000: 4049519424 -45000: 613160608 -44000: 1566126172 -43000: 3731725133 -42000: 2746368727 -41000: 4168967735 -40000: 1319649932 -39000: 2964978784 -38000: 967937134 -37000: 3116555742 -36000: 2279790642 -35000: 2852914953 -34000: 1040410911 -33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 180964610500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index b479c4175..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1097 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.180965 # Number of seconds simulated -sim_ticks 180964610500 # Number of ticks simulated -final_tick 180964610500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 431391 # Simulator instruction rate (inst/s) -host_op_rate 431391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92673550 # Simulator tick rate (ticks/s) -host_mem_usage 265016 # Number of bytes of host memory used -host_seconds 1952.71 # Real time elapsed on the host -sim_insts 842382029 # Number of instructions simulated -sim_ops 842382029 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18525056 # Number of bytes read from this memory -system.physmem.bytes_read::total 18699008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292172 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 961249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102368391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103329640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 961249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 961249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 23582777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 23582777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 23582777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 961249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102368391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 126912416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292172 # Number of read requests accepted -system.physmem.writeReqs 66682 # Number of write requests accepted -system.physmem.readBursts 292172 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18678912 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18699008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18010 # Per bank write bursts -system.physmem.perBankRdBursts::1 18337 # Per bank write bursts -system.physmem.perBankRdBursts::2 18388 # Per bank write bursts -system.physmem.perBankRdBursts::3 18350 # Per bank write bursts -system.physmem.perBankRdBursts::4 18232 # Per bank write bursts -system.physmem.perBankRdBursts::5 18236 # Per bank write bursts -system.physmem.perBankRdBursts::6 18319 # Per bank write bursts -system.physmem.perBankRdBursts::7 18311 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18232 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18381 # Per bank write bursts -system.physmem.perBankRdBursts::12 18250 # Per bank write bursts -system.physmem.perBankRdBursts::13 18122 # Per bank write bursts -system.physmem.perBankRdBursts::14 18054 # Per bank write bursts -system.physmem.perBankRdBursts::15 18189 # Per bank write bursts -system.physmem.perBankWrBursts::0 4125 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4223 # Per bank write bursts -system.physmem.perBankWrBursts::3 4160 # Per bank write bursts -system.physmem.perBankWrBursts::4 4142 # Per bank write bursts -system.physmem.perBankWrBursts::5 4099 # Per bank write bursts -system.physmem.perBankWrBursts::6 4261 # Per bank write bursts -system.physmem.perBankWrBursts::7 4226 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4182 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 180964514000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292172 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 214643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.251837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.294089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.548448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30650 32.23% 32.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40922 43.03% 75.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11798 12.41% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 210 0.22% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 215 0.23% 88.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 192 0.20% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 361 0.38% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1740 1.83% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9017 9.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95105 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.502343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.667312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 739.938886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4047 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4055 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4055 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.438224 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.418308 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.827243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3164 78.03% 78.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.17% 78.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 882 21.75% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4055 # Writes before turning the bus around for reads -system.physmem.totQLat 10146386000 # Total ticks spent queuing -system.physmem.totMemAccLat 15618723500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34764.80 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53514.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 23.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.33 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 23.58 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.99 # Data bus utilization in percentage -system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.18 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing -system.physmem.readRowHits 211326 # Number of row buffer hits during reads -system.physmem.writeRowHits 52079 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.10 # Row buffer hit rate for writes -system.physmem.avgGap 504284.51 # Average gap between requests -system.physmem.pageHitRate 73.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 339192840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 180273885 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1043746620 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174348000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 16047635760.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5505974850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 757646880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 38977794150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 26263488480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 5833398105 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 95148801450 # Total energy per rank (pJ) -system.physmem_0.averagePower 525.786736 # Core power per rank (mW) -system.physmem_0.totalIdleTime 166860797500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1403220500 # Time in different power states -system.physmem_0.memoryStateTime::REF 6819966000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 12988477500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 68394436250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5880505500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 85478004750 # Time in different power states -system.physmem_1.actEnergy 339892560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 180649590 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1040119500 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 173601540 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 16056240720.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5469389970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 750054720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 39161701800 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 26293456800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 5720767110 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 95209751490 # Total energy per rank (pJ) -system.physmem_1.averagePower 526.123579 # Core power per rank (mW) -system.physmem_1.totalIdleTime 166963691000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1377166250 # Time in different power states -system.physmem_1.memoryStateTime::REF 6823618000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 12610325250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 68472559500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5800086000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 85880855500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 129261099 # Number of BP lookups -system.cpu.branchPred.condPredicted 83045520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 145257 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93509067 # Number of BTB lookups -system.cpu.branchPred.BTBHits 70599314 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 75.499966 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19428116 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1153 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14846448 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14825593 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 20855 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 243608266 # DTB read hits -system.cpu.dtb.read_misses 267709 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 243875975 # DTB read accesses -system.cpu.dtb.write_hits 101634051 # DTB write hits -system.cpu.dtb.write_misses 39619 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 101673670 # DTB write accesses -system.cpu.dtb.data_hits 345242317 # DTB hits -system.cpu.dtb.data_misses 307328 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 345549645 # DTB accesses -system.cpu.itb.fetch_hits 116218000 # ITB hits -system.cpu.itb.fetch_misses 1612 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 116219612 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 361929222 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 116540326 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973682349 # Number of instructions fetch has processed -system.cpu.fetch.Branches 129261099 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 104853023 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 244730119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 756754 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 840 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 15490 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 116218000 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 168019 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 361665180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.692220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.078693 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 164951201 45.61% 45.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 21852654 6.04% 51.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15621060 4.32% 55.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24569981 6.79% 62.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 38586382 10.67% 73.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15690881 4.34% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 12539815 3.47% 81.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3986839 1.10% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63866367 17.66% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 361665180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.357145 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.690256 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85732697 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98146269 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158921683 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18492948 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371583 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11928940 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7011 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 968666226 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25451 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371583 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93249960 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12380390 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 169252258 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86395583 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 966785843 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1367 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25166874 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 51736906 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7729074 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 666569704 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1151545318 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114509565 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 37035752 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27602546 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 87961020 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 245059340 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 102632582 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35344831 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4698812 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 877945756 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 74 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 871651299 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 10628 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35563800 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10965429 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 361665180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.410106 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.146787 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 87893149 24.30% 24.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 61352794 16.96% 41.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 57499290 15.90% 57.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51081168 14.12% 71.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45042350 12.45% 83.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20636672 5.71% 89.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18146014 5.02% 94.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10282367 2.84% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9731376 2.69% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 361665180 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3586644 18.56% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11632892 60.20% 78.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3008624 15.57% 94.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 913480 4.73% 99.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 182872 0.95% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 505104722 57.95% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7855 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13297886 1.53% 59.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826557 0.44% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 234518362 26.91% 87.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 97834915 11.22% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 9747446 1.12% 99.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 3972470 0.46% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 871651299 # Type of FU issued -system.cpu.iq.rate 2.408347 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19324512 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2054837876 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 876768256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 835988686 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69465042 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36778231 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34166819 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855694014 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35280521 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65597237 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7548743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37089 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4331382 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2716 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4307 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371583 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4257057 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 608088 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 966007295 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16673 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 245059340 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 102632582 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 74 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 538259 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83477 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37089 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128251 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 15992 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 144243 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 871026557 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 243876094 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 624742 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88061465 # number of nop insts executed -system.cpu.iew.exec_refs 345550079 # number of memory reference insts executed -system.cpu.iew.exec_branches 127153600 # Number of branches executed -system.cpu.iew.exec_stores 101673985 # Number of stores executed -system.cpu.iew.exec_rate 2.406621 # Inst execution rate -system.cpu.iew.wb_sent 870617196 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 870155505 # cumulative count of insts written-back -system.cpu.iew.wb_producers 525001925 # num instructions producing a value -system.cpu.iew.wb_consumers 821956019 # num instructions consuming a value -system.cpu.iew.wb_rate 2.404215 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.638723 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 31805123 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 138464 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 357537289 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.597177 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.046569 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121797842 34.07% 34.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 81929888 22.92% 56.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 29949089 8.38% 65.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19779772 5.53% 70.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17819434 4.98% 75.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7962754 2.23% 78.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3039675 0.85% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3979990 1.11% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71278845 19.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 357537289 # Number of insts commited each cycle -system.cpu.commit.committedInsts 928587628 # Number of instructions committed -system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 335811797 # Number of memory references committed -system.cpu.commit.loads 237510597 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 123111018 # Number of branches committed -system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions. -system.cpu.commit.int_insts 821934723 # Number of committed integer instructions. -system.cpu.commit.function_calls 18524163 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 227943648 24.55% 88.38% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 94464282 10.17% 98.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 9566949 1.03% 99.59% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 3836918 0.41% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 71278845 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1244030057 # The number of ROB reads -system.cpu.rob.rob_writes 1924915650 # The number of ROB writes -system.cpu.timesIdled 3145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 264042 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 842382029 # Number of Instructions Simulated -system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.429650 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.429650 # CPI: Total CPI of All Threads -system.cpu.ipc 2.327477 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.327477 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1104175341 # number of integer regfile reads -system.cpu.int_regfile_writes 635597274 # number of integer regfile writes -system.cpu.fp_regfile_reads 36400867 # number of floating regfile reads -system.cpu.fp_regfile_writes 24677538 # number of floating regfile writes -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776666 # number of replacements -system.cpu.dcache.tags.tagsinuse 4090.964650 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 273860034 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780762 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 350.759942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 396630500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4090.964650 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998771 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2527 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 553391630 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 553391630 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 176451824 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 176451824 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408197 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408197 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 273860021 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 273860021 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 273860021 # number of overall hits -system.cpu.dcache.overall_hits::total 273860021 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1552397 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1552397 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 893003 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 893003 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2445400 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2445400 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2445400 # number of overall misses -system.cpu.dcache.overall_misses::total 2445400 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 96567477000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 96567477000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 65926918364 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 65926918364 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 162494395364 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 162494395364 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 162494395364 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 162494395364 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 178004221 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 178004221 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 276305421 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 276305421 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 276305421 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 276305421 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008721 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008721 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009084 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008850 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008850 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008850 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008850 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62205.400423 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62205.400423 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73826.088338 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73826.088338 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66449.004402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66449.004402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66449.004402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66449.004402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25561 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 192860 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 308 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.990260 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 371.599229 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88570 # number of writebacks -system.cpu.dcache.writebacks::total 88570 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840254 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 840254 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824384 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 824384 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1664638 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1664638 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1664638 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1664638 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712143 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712143 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68619 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68619 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780762 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780762 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780762 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780762 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30603980500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30603980500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6049145998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6049145998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36653126498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36653126498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36653126498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36653126498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42974.487568 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42974.487568 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88155.554555 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88155.554555 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46945.325846 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46945.325846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46945.325846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46945.325846 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.809929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 116209747 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6323 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18378.894038 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.809929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1545 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 232442323 # Number of tag accesses -system.cpu.icache.tags.data_accesses 232442323 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 116209747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 116209747 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 116209747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 116209747 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 116209747 # number of overall hits -system.cpu.icache.overall_hits::total 116209747 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8253 # number of overall misses -system.cpu.icache.overall_misses::total 8253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 382535999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 382535999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 382535999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 382535999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 382535999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 382535999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 116218000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 116218000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 116218000 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 116218000 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 116218000 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 116218000 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46351.144917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46351.144917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46351.144917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46351.144917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46351.144917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46351.144917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 811 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.384615 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4618 # number of writebacks -system.cpu.icache.writebacks::total 4618 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1929 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1929 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1929 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1929 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1929 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1929 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6324 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6324 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6324 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6324 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6324 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6324 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 282422000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 282422000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 282422000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 282422000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 282422000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 282422000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44658.760278 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44658.760278 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44658.760278 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44658.760278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44658.760278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44658.760278 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259808 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32653.135367 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1275792 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292576 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.360549 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 1306360000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 44.057169 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.938267 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32540.139931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001345 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002104 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.993046 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996495 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 834 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8358 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 23070 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12839536 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12839536 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88570 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88570 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3605 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3605 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489315 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 489315 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3605 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 494913 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3605 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491308 # number of overall hits -system.cpu.l2cache.overall_hits::total 494913 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66626 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66626 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2719 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2719 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222828 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222828 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2719 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289454 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292173 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2719 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289454 # number of overall misses -system.cpu.l2cache.overall_misses::total 292173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5925054000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5925054000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234987000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 234987000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 24391913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 24391913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 234987000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30316967000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30551954000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 234987000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30316967000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30551954000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88570 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88570 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68619 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68619 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6324 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6324 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712143 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712143 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6324 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780762 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 787086 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6324 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780762 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 787086 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.970956 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.970956 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.429949 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.429949 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312898 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312898 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.429949 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370733 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.371208 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.429949 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370733 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.371208 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88930.057335 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88930.057335 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86424.052961 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86424.052961 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109465.206347 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109465.206347 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86424.052961 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104738.462761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 104568.026477 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86424.052961 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104738.462761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 104568.026477 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66682 # number of writebacks -system.cpu.l2cache.writebacks::total 66682 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66626 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66626 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2719 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2719 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222828 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222828 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2719 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289454 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2719 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289454 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5258794000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5258794000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207807000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207807000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 22163633000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 22163633000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207807000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27422427000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27630234000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207807000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27422427000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27630234000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970956 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970956 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.429949 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312898 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312898 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370733 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.371208 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370733 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.371208 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78930.057335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78930.057335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76427.730783 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76427.730783 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99465.206347 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99465.206347 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76427.730783 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94738.462761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94568.060704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76427.730783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94738.462761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94568.060704 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1568370 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781284 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2012 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 718466 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6324 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712143 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2355455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55637248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56337472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259808 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1046894 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001922 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043797 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1044882 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2012 0.19% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1046894 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877373000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9484500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171143000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 549969 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257797 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution -system.membus.trans_dist::CleanEvict 191115 # Transaction distribution -system.membus.trans_dist::ReadExReq 66626 # Transaction distribution -system.membus.trans_dist::ReadExResp 66626 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225546 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842141 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842141 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22966656 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292172 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292172 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292172 # Request fanout histogram -system.membus.reqLayer0.occupancy 877590500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551176250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index 0452b264c..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 54e31201a..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index 3f843823b..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4304 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 -592000: 2038558826 -591000: 3948772976 -590000: 439262378 -589000: 329537197 -588000: 3678661972 -587000: 4240182727 -586000: 2283602206 -585000: 1129811410 -584000: 2831949168 -583000: 1224559023 -582000: 3161562107 -581000: 2695467835 -580000: 1234192577 -579000: 1974816198 -578000: 449576701 -577000: 1424873035 -576000: 2370444290 -575000: 1743089134 -574000: 2624046998 -573000: 2071148441 -572000: 2449219691 -571000: 3774476172 -570000: 1111630327 -569000: 121721805 -568000: 2981212266 -567000: 3811833647 -566000: 3676851843 -565000: 1766252334 -564000: 1622887950 -563000: 1684409857 -562000: 1686489387 -561000: 610219569 -560000: 2705092362 -559000: 108031723 -558000: 1316736987 -557000: 2434129258 -556000: 1411819652 -555000: 1173886179 -554000: 3044539233 -553000: 151590417 -552000: 3759426289 -551000: 3451520306 -550000: 294242855 -549000: 890241051 -548000: 876385779 -547000: 119864600 -546000: 3065674956 -545000: 1670853168 -544000: 997261561 -543000: 660227344 -542000: 3132294889 -541000: 521956271 -540000: 1133928405 -539000: 3838154786 -538000: 58624572 -537000: 3544030439 -536000: 432804999 -535000: 1021857051 -534000: 2644812356 -533000: 773094580 -532000: 901027171 -531000: 3976696839 -530000: 4167278216 -529000: 504481120 -528000: 320399857 -527000: 638048690 -526000: 3348998474 -525000: 2660662065 -524000: 2641437803 -523000: 626927006 -522000: 4063917554 -521000: 3212249308 -520000: 2561025301 -519000: 1078140141 -518000: 653939181 -517000: 2154098204 -516000: 3773089676 -515000: 2568381435 -514000: 3838886937 -513000: 941125346 -512000: 1318900410 -511000: 297013287 -510000: 241723934 -509000: 1835499795 -508000: 2309451230 -507000: 1174814430 -506000: 3615943386 -505000: 51034971 -504000: 3950453295 -503000: 4186097241 -502000: 327518343 -501000: 3052462710 -500000: 1586937404 -499000: 2169094819 -498000: 3613195151 -497000: 817359591 -496000: 1470916579 -495000: 2091261583 -494000: 2080080890 -493000: 1772858697 -492000: 2085609872 -491000: 3280632925 -490000: 1689322569 -489000: 2947406469 -488000: 765163324 -487000: 3122594732 -486000: 3385418480 -485000: 1712345567 -484000: 3675825158 -483000: 1558929764 -482000: 2672493410 -481000: 3822528440 -480000: 3741769935 -479000: 2794026235 -478000: 2541364185 -477000: 3964482316 -476000: 1202478165 -475000: 4027617791 -474000: 1905026738 -473000: 2573787636 -472000: 1170529797 -471000: 2272525618 -470000: 820833429 -469000: 3219769529 -468000: 2121197441 -467000: 269331764 -466000: 3038487237 -465000: 2462675338 -464000: 2703163101 -463000: 547052037 -462000: 3454526671 -461000: 2124641794 -460000: 1043737466 -459000: 1785834964 -458000: 3312335313 -457000: 1213835042 -456000: 3099430685 -455000: 3003350806 -454000: 3646781335 -453000: 1474165966 -452000: 705795987 -451000: 2723908407 -450000: 1323056304 -449000: 1157256530 -448000: 4077983523 -447000: 3189085703 -446000: 2241002747 -445000: 3229050072 -444000: 3500150226 -443000: 1290722604 -442000: 1866107725 -441000: 4238277470 -440000: 847346408 -439000: 2474557496 -438000: 2243092317 -437000: 706909230 -436000: 1303503693 -435000: 1456129560 -434000: 1073061079 -433000: 692226634 -432000: 186498656 -431000: 2203415525 -430000: 2183000701 -429000: 1007776545 -428000: 941117387 -427000: 3805851413 -426000: 1474193180 -425000: 4231673903 -424000: 2622576664 -423000: 388097625 -422000: 1165097488 -421000: 3226044518 -420000: 2531461570 -419000: 1509806310 -418000: 2667519114 -417000: 1751592438 -416000: 1286773513 -415000: 1098182293 -414000: 2111912709 -413000: 1230737431 -412000: 4090873946 -411000: 3998652133 -410000: 2486660396 -409000: 2120483596 -408000: 587404533 -407000: 188697995 -406000: 3265346093 -405000: 4234961905 -404000: 1211873901 -403000: 4265173305 -402000: 2208355316 -401000: 3315952806 -400000: 3917328941 -399000: 2523594649 -398000: 3805986783 -397000: 2624925960 -396000: 3716020189 -395000: 2016201122 -394000: 912930261 -393000: 596904160 -392000: 3571173642 -391000: 2290782861 -390000: 1162492227 -389000: 1738718380 -388000: 2599667355 -387000: 2382332909 -386000: 1471269037 -385000: 2238392684 -384000: 4034826126 -383000: 1378654892 -382000: 3702601850 -381000: 397206179 -380000: 2437704230 -379000: 4187604139 -378000: 779452169 -377000: 2010372403 -376000: 531902409 -375000: 1371470602 -374000: 4137796987 -373000: 567426549 -372000: 3082742955 -371000: 2271575596 -370000: 759731212 -369000: 4063369437 -368000: 299356452 -367000: 536656228 -366000: 3014961694 -365000: 3016542135 -364000: 2841873124 -363000: 524434057 -362000: 2887828889 -361000: 3865529589 -360000: 671363647 -359000: 3104594256 -358000: 1502485940 -357000: 1776624159 -356000: 4222478488 -355000: 4127624139 -354000: 2439477793 -353000: 1593794891 -352000: 591275342 -351000: 2177291538 -350000: 1923444781 -349000: 758084193 -348000: 775471359 -347000: 191356974 -346000: 494488375 -345000: 1990489399 -344000: 124118372 -343000: 2046377904 -342000: 1395427716 -341000: 1342299790 -340000: 38145994 -339000: 2291884417 -338000: 351940574 -337000: 3984301480 -336000: 2468666235 -335000: 371500747 -334000: 969922131 -333000: 240854580 -332000: 1644465214 -331000: 1539846168 -330000: 940087216 -329000: 1491329232 -328000: 2281687201 -327000: 3030170550 -326000: 3648503863 -325000: 2037898355 -324000: 174369956 -323000: 2433605668 -322000: 2334905107 -321000: 1597704047 -320000: 302297707 -319000: 3209203690 -318000: 3894539879 -317000: 2868907580 -316000: 2808087076 -315000: 4034586233 -314000: 3694191694 -313000: 2001671958 -312000: 559582279 -311000: 3043016195 -310000: 2785098502 -309000: 4104602138 -308000: 966154914 -307000: 2446376687 -306000: 789956605 -305000: 1708137092 -304000: 1733063901 -303000: 2924555399 -302000: 971356234 -301000: 481382543 -300000: 2647080988 -299000: 4065744916 -298000: 921140 -297000: 654346784 -296000: 485492098 -295000: 217516816 -294000: 4050820137 -293000: 534726686 -292000: 1686691079 -291000: 1316587195 -290000: 3746020838 -289000: 1641967381 -288000: 3492475215 -287000: 3154885393 -286000: 3686450617 -285000: 3589739293 -284000: 3558041700 -283000: 4130142319 -282000: 3132446063 -281000: 982677436 -280000: 799322395 -279000: 151715214 -278000: 3765942871 -277000: 1712470933 -276000: 3807622752 -275000: 4163730108 -274000: 1633425299 -273000: 1654241631 -272000: 1131025394 -271000: 1375475855 -270000: 553294237 -269000: 4091487177 -268000: 2841855980 -267000: 2997369904 -266000: 454385594 -265000: 3757482634 -264000: 3856197465 -263000: 1084605457 -262000: 2552759023 -261000: 3786548799 -260000: 272762545 -259000: 2670277860 -258000: 76233700 -257000: 476168167 -256000: 8969192 -255000: 1998841030 -254000: 1240074303 -253000: 1771564446 -252000: 710374418 -251000: 821383716 -250000: 3157726088 -249000: 3083379502 -248000: 2563632690 -247000: 33723341 -246000: 3303336748 -245000: 4110677892 -244000: 3811702913 -243000: 53856215 -242000: 243571468 -241000: 52177779 -240000: 46805590 -239000: 1622010618 -238000: 1321640849 -237000: 3106837291 -236000: 4102944642 -235000: 137904396 -234000: 339510135 -233000: 88415957 -232000: 3157666382 -231000: 2571005912 -230000: 3586247649 -229000: 4172761781 -228000: 2463305780 -227000: 956927307 -226000: 2169861547 -225000: 1751989251 -224000: 673059158 -223000: 2782464516 -222000: 3741392140 -221000: 2856154963 -220000: 3778376854 -219000: 1538476717 -218000: 2879698522 -217000: 3734645735 -216000: 1899042577 -215000: 371356008 -214000: 2416663698 -213000: 1595919347 -212000: 2816045438 -211000: 132438808 -210000: 1098603890 -209000: 834913667 -208000: 2707567283 -207000: 3154122448 -206000: 3696516104 -205000: 1427952551 -204000: 280496321 -203000: 1185678745 -202000: 3461951699 -201000: 1369208434 -200000: 3900136261 -199000: 870818876 -198000: 327248310 -197000: 3116959470 -196000: 1544241188 -195000: 1568248814 -194000: 2978831302 -193000: 205660429 -192000: 1704239501 -191000: 3570135474 -190000: 3878512103 -189000: 1212729210 -188000: 1873588815 -187000: 324853813 -186000: 432676298 -185000: 1641364437 -184000: 1568401301 -183000: 525792402 -182000: 861154382 -181000: 2357325066 -180000: 3626762590 -179000: 4172125462 -178000: 2108738993 -177000: 2084782857 -176000: 3956924509 -175000: 17183073 -174000: 3676839474 -173000: 458250029 -172000: 2635215219 -171000: 1801029767 -170000: 3602628987 -169000: 370704281 -168000: 177963345 -167000: 924067814 -166000: 3577678376 -165000: 3717789117 -164000: 3285809386 -163000: 3738962897 -162000: 3172510171 -161000: 417992786 -160000: 2591600214 -159000: 3315096579 -158000: 3590763949 -157000: 198872871 -156000: 2960653534 -155000: 2246563682 -154000: 2304045306 -153000: 2647353543 -152000: 2043381015 -151000: 3952056867 -150000: 2644058641 -149000: 3477151018 -148000: 1740210241 -147000: 3314851112 -146000: 1604832482 -145000: 2572410736 -144000: 1965059167 -143000: 889666293 -142000: 1024747903 -141000: 226685285 -140000: 3149168519 -139000: 403638872 -138000: 1725889104 -137000: 1417402331 -136000: 422304488 -135000: 2595894054 -134000: 4266597695 -133000: 1116326556 -132000: 3537080833 -131000: 2181246909 -130000: 1241997223 -129000: 628191304 -128000: 3074132403 -127000: 2112958836 -126000: 1371260930 -125000: 2272975771 -124000: 1379085607 -123000: 1998991877 -122000: 2760271255 -121000: 3784187756 -120000: 311188417 -119000: 1123593459 -118000: 1249155194 -117000: 908703020 -116000: 3765244393 -115000: 3040869794 -114000: 437536659 -113000: 3343598822 -112000: 2419089776 -111000: 1263143640 -110000: 1384687523 -109000: 1727931349 -108000: 2861733388 -107000: 963829093 -106000: 431354627 -105000: 3568623360 -104000: 2957399361 -103000: 1071045618 -102000: 3968457714 -101000: 3448338394 -100000: 2586060251 -99000: 3401651822 -98000: 1579089478 -97000: 3722618916 -96000: 759319595 -95000: 1269278712 -94000: 150489448 -93000: 390013662 -92000: 3663029784 -91000: 555197170 -90000: 166476858 -89000: 1658807720 -88000: 3430520531 -87000: 2946861093 -86000: 3000600326 -85000: 300034452 -84000: 2813719249 -83000: 3009927425 -82000: 1127728469 -81000: 2667791855 -80000: 2632316050 -79000: 2180301200 -78000: 418999983 -77000: 4254858933 -76000: 2728734498 -75000: 1863202698 -74000: 4226419921 -73000: 1917572494 -72000: 3117082625 -71000: 1032601538 -70000: 2992135524 -69000: 670119660 -68000: 638731522 -67000: 1460114012 -66000: 1232274665 -65000: 3667669961 -64000: 191277965 -63000: 3868442802 -62000: 700664540 -61000: 2271087482 -60000: 3274078227 -59000: 159900296 -58000: 2778747772 -57000: 2788477153 -56000: 3965957780 -55000: 2276993918 -54000: 1986966104 -53000: 3416414682 -52000: 2162594060 -51000: 2947744069 -50000: 4024793290 -49000: 631161701 -48000: 728285173 -47000: 1487641693 -46000: 4049519424 -45000: 613160608 -44000: 1566126172 -43000: 3731725133 -42000: 2746368727 -41000: 4168967735 -40000: 1319649932 -39000: 2964978784 -38000: 967937134 -37000: 3116555742 -36000: 2279790642 -35000: 2852914953 -34000: 1040410911 -33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 464394627000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index fdd12f539..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.464395 # Number of seconds simulated -sim_ticks 464394627000 # Number of ticks simulated -final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2996785 # Simulator instruction rate (inst/s) -host_op_rate 2996785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1498717563 # Simulator tick rate (ticks/s) -host_mem_usage 251436 # Number of bytes of host memory used -host_seconds 309.86 # Real time elapsed on the host -sim_insts 928587629 # Number of instructions simulated -sim_ops 928587629 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory -system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory -system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237510597 # DTB read hits -system.cpu.dtb.read_misses 194650 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237705247 # DTB read accesses -system.cpu.dtb.write_hits 98301200 # DTB write hits -system.cpu.dtb.write_misses 6871 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98308071 # DTB write accesses -system.cpu.dtb.data_hits 335811797 # DTB hits -system.cpu.dtb.data_misses 201521 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336013318 # DTB accesses -system.cpu.itb.fetch_hits 928789150 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 928789255 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 464394627000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 928789255 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928587629 # Number of instructions committed -system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses -system.cpu.num_func_calls 37048314 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls -system.cpu.num_int_insts 822136244 # number of integer instructions -system.cpu.num_fp_insts 33439365 # number of float instructions -system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read -system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read -system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written -system.cpu.num_mem_refs 336013318 # number of memory refs -system.cpu.num_load_insts 237705247 # Number of load instructions -system.cpu.num_store_insts 98308071 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 928789255 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 123111018 # Number of branches fetched -system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction -system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction -system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction -system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction -system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 928789150 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution -system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution -system.membus.trans_dist::WriteReq 98301200 # Transaction distribution -system.membus.trans_dist::WriteResp 98301200 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1264600947 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1264600947 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index b6ac9fa01..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 54e31201a..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index 6564d4aeb..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4305 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 -592000: 2038558826 -591000: 3948772976 -590000: 439262378 -589000: 329537197 -588000: 3678661972 -587000: 4240182727 -586000: 2283602206 -585000: 1129811410 -584000: 2831949168 -583000: 1224559023 -582000: 3161562107 -581000: 2695467835 -580000: 1234192577 -579000: 1974816198 -578000: 449576701 -577000: 1424873035 -576000: 2370444290 -575000: 1743089134 -574000: 2624046998 -573000: 2071148441 -572000: 2449219691 -571000: 3774476172 -570000: 1111630327 -569000: 121721805 -568000: 2981212266 -567000: 3811833647 -566000: 3676851843 -565000: 1766252334 -564000: 1622887950 -563000: 1684409857 -562000: 1686489387 -561000: 610219569 -560000: 2705092362 -559000: 108031723 -558000: 1316736987 -557000: 2434129258 -556000: 1411819652 -555000: 1173886179 -554000: 3044539233 -553000: 151590417 -552000: 3759426289 -551000: 3451520306 -550000: 294242855 -549000: 890241051 -548000: 876385779 -547000: 119864600 -546000: 3065674956 -545000: 1670853168 -544000: 997261561 -543000: 660227344 -542000: 3132294889 -541000: 521956271 -540000: 1133928405 -539000: 3838154786 -538000: 58624572 -537000: 3544030439 -536000: 432804999 -535000: 1021857051 -534000: 2644812356 -533000: 773094580 -532000: 901027171 -531000: 3976696839 -530000: 4167278216 -529000: 504481120 -528000: 320399857 -527000: 638048690 -526000: 3348998474 -525000: 2660662065 -524000: 2641437803 -523000: 626927006 -522000: 4063917554 -521000: 3212249308 -520000: 2561025301 -519000: 1078140141 -518000: 653939181 -517000: 2154098204 -516000: 3773089676 -515000: 2568381435 -514000: 3838886937 -513000: 941125346 -512000: 1318900410 -511000: 297013287 -510000: 241723934 -509000: 1835499795 -508000: 2309451230 -507000: 1174814430 -506000: 3615943386 -505000: 51034971 -504000: 3950453295 -503000: 4186097241 -502000: 327518343 -501000: 3052462710 -500000: 1586937404 -499000: 2169094819 -498000: 3613195151 -497000: 817359591 -496000: 1470916579 -495000: 2091261583 -494000: 2080080890 -493000: 1772858697 -492000: 2085609872 -491000: 3280632925 -490000: 1689322569 -489000: 2947406469 -488000: 765163324 -487000: 3122594732 -486000: 3385418480 -485000: 1712345567 -484000: 3675825158 -483000: 1558929764 -482000: 2672493410 -481000: 3822528440 -480000: 3741769935 -479000: 2794026235 -478000: 2541364185 -477000: 3964482316 -476000: 1202478165 -475000: 4027617791 -474000: 1905026738 -473000: 2573787636 -472000: 1170529797 -471000: 2272525618 -470000: 820833429 -469000: 3219769529 -468000: 2121197441 -467000: 269331764 -466000: 3038487237 -465000: 2462675338 -464000: 2703163101 -463000: 547052037 -462000: 3454526671 -461000: 2124641794 -460000: 1043737466 -459000: 1785834964 -458000: 3312335313 -457000: 1213835042 -456000: 3099430685 -455000: 3003350806 -454000: 3646781335 -453000: 1474165966 -452000: 705795987 -451000: 2723908407 -450000: 1323056304 -449000: 1157256530 -448000: 4077983523 -447000: 3189085703 -446000: 2241002747 -445000: 3229050072 -444000: 3500150226 -443000: 1290722604 -442000: 1866107725 -441000: 4238277470 -440000: 847346408 -439000: 2474557496 -438000: 2243092317 -437000: 706909230 -436000: 1303503693 -435000: 1456129560 -434000: 1073061079 -433000: 692226634 -432000: 186498656 -431000: 2203415525 -430000: 2183000701 -429000: 1007776545 -428000: 941117387 -427000: 3805851413 -426000: 1474193180 -425000: 4231673903 -424000: 2622576664 -423000: 388097625 -422000: 1165097488 -421000: 3226044518 -420000: 2531461570 -419000: 1509806310 -418000: 2667519114 -417000: 1751592438 -416000: 1286773513 -415000: 1098182293 -414000: 2111912709 -413000: 1230737431 -412000: 4090873946 -411000: 3998652133 -410000: 2486660396 -409000: 2120483596 -408000: 587404533 -407000: 188697995 -406000: 3265346093 -405000: 4234961905 -404000: 1211873901 -403000: 4265173305 -402000: 2208355316 -401000: 3315952806 -400000: 3917328941 -399000: 2523594649 -398000: 3805986783 -397000: 2624925960 -396000: 3716020189 -395000: 2016201122 -394000: 912930261 -393000: 596904160 -392000: 3571173642 -391000: 2290782861 -390000: 1162492227 -389000: 1738718380 -388000: 2599667355 -387000: 2382332909 -386000: 1471269037 -385000: 2238392684 -384000: 4034826126 -383000: 1378654892 -382000: 3702601850 -381000: 397206179 -380000: 2437704230 -379000: 4187604139 -378000: 779452169 -377000: 2010372403 -376000: 531902409 -375000: 1371470602 -374000: 4137796987 -373000: 567426549 -372000: 3082742955 -371000: 2271575596 -370000: 759731212 -369000: 4063369437 -368000: 299356452 -367000: 536656228 -366000: 3014961694 -365000: 3016542135 -364000: 2841873124 -363000: 524434057 -362000: 2887828889 -361000: 3865529589 -360000: 671363647 -359000: 3104594256 -358000: 1502485940 -357000: 1776624159 -356000: 4222478488 -355000: 4127624139 -354000: 2439477793 -353000: 1593794891 -352000: 591275342 -351000: 2177291538 -350000: 1923444781 -349000: 758084193 -348000: 775471359 -347000: 191356974 -346000: 494488375 -345000: 1990489399 -344000: 124118372 -343000: 2046377904 -342000: 1395427716 -341000: 1342299790 -340000: 38145994 -339000: 2291884417 -338000: 351940574 -337000: 3984301480 -336000: 2468666235 -335000: 371500747 -334000: 969922131 -333000: 240854580 -332000: 1644465214 -331000: 1539846168 -330000: 940087216 -329000: 1491329232 -328000: 2281687201 -327000: 3030170550 -326000: 3648503863 -325000: 2037898355 -324000: 174369956 -323000: 2433605668 -322000: 2334905107 -321000: 1597704047 -320000: 302297707 -319000: 3209203690 -318000: 3894539879 -317000: 2868907580 -316000: 2808087076 -315000: 4034586233 -314000: 3694191694 -313000: 2001671958 -312000: 559582279 -311000: 3043016195 -310000: 2785098502 -309000: 4104602138 -308000: 966154914 -307000: 2446376687 -306000: 789956605 -305000: 1708137092 -304000: 1733063901 -303000: 2924555399 -302000: 971356234 -301000: 481382543 -300000: 2647080988 -299000: 4065744916 -298000: 921140 -297000: 654346784 -296000: 485492098 -295000: 217516816 -294000: 4050820137 -293000: 534726686 -292000: 1686691079 -291000: 1316587195 -290000: 3746020838 -289000: 1641967381 -288000: 3492475215 -287000: 3154885393 -286000: 3686450617 -285000: 3589739293 -284000: 3558041700 -283000: 4130142319 -282000: 3132446063 -281000: 982677436 -280000: 799322395 -279000: 151715214 -278000: 3765942871 -277000: 1712470933 -276000: 3807622752 -275000: 4163730108 -274000: 1633425299 -273000: 1654241631 -272000: 1131025394 -271000: 1375475855 -270000: 553294237 -269000: 4091487177 -268000: 2841855980 -267000: 2997369904 -266000: 454385594 -265000: 3757482634 -264000: 3856197465 -263000: 1084605457 -262000: 2552759023 -261000: 3786548799 -260000: 272762545 -259000: 2670277860 -258000: 76233700 -257000: 476168167 -256000: 8969192 -255000: 1998841030 -254000: 1240074303 -253000: 1771564446 -252000: 710374418 -251000: 821383716 -250000: 3157726088 -249000: 3083379502 -248000: 2563632690 -247000: 33723341 -246000: 3303336748 -245000: 4110677892 -244000: 3811702913 -243000: 53856215 -242000: 243571468 -241000: 52177779 -240000: 46805590 -239000: 1622010618 -238000: 1321640849 -237000: 3106837291 -236000: 4102944642 -235000: 137904396 -234000: 339510135 -233000: 88415957 -232000: 3157666382 -231000: 2571005912 -230000: 3586247649 -229000: 4172761781 -228000: 2463305780 -227000: 956927307 -226000: 2169861547 -225000: 1751989251 -224000: 673059158 -223000: 2782464516 -222000: 3741392140 -221000: 2856154963 -220000: 3778376854 -219000: 1538476717 -218000: 2879698522 -217000: 3734645735 -216000: 1899042577 -215000: 371356008 -214000: 2416663698 -213000: 1595919347 -212000: 2816045438 -211000: 132438808 -210000: 1098603890 -209000: 834913667 -208000: 2707567283 -207000: 3154122448 -206000: 3696516104 -205000: 1427952551 -204000: 280496321 -203000: 1185678745 -202000: 3461951699 -201000: 1369208434 -200000: 3900136261 -199000: 870818876 -198000: 327248310 -197000: 3116959470 -196000: 1544241188 -195000: 1568248814 -194000: 2978831302 -193000: 205660429 -192000: 1704239501 -191000: 3570135474 -190000: 3878512103 -189000: 1212729210 -188000: 1873588815 -187000: 324853813 -186000: 432676298 -185000: 1641364437 -184000: 1568401301 -183000: 525792402 -182000: 861154382 -181000: 2357325066 -180000: 3626762590 -179000: 4172125462 -178000: 2108738993 -177000: 2084782857 -176000: 3956924509 -175000: 17183073 -174000: 3676839474 -173000: 458250029 -172000: 2635215219 -171000: 1801029767 -170000: 3602628987 -169000: 370704281 -168000: 177963345 -167000: 924067814 -166000: 3577678376 -165000: 3717789117 -164000: 3285809386 -163000: 3738962897 -162000: 3172510171 -161000: 417992786 -160000: 2591600214 -159000: 3315096579 -158000: 3590763949 -157000: 198872871 -156000: 2960653534 -155000: 2246563682 -154000: 2304045306 -153000: 2647353543 -152000: 2043381015 -151000: 3952056867 -150000: 2644058641 -149000: 3477151018 -148000: 1740210241 -147000: 3314851112 -146000: 1604832482 -145000: 2572410736 -144000: 1965059167 -143000: 889666293 -142000: 1024747903 -141000: 226685285 -140000: 3149168519 -139000: 403638872 -138000: 1725889104 -137000: 1417402331 -136000: 422304488 -135000: 2595894054 -134000: 4266597695 -133000: 1116326556 -132000: 3537080833 -131000: 2181246909 -130000: 1241997223 -129000: 628191304 -128000: 3074132403 -127000: 2112958836 -126000: 1371260930 -125000: 2272975771 -124000: 1379085607 -123000: 1998991877 -122000: 2760271255 -121000: 3784187756 -120000: 311188417 -119000: 1123593459 -118000: 1249155194 -117000: 908703020 -116000: 3765244393 -115000: 3040869794 -114000: 437536659 -113000: 3343598822 -112000: 2419089776 -111000: 1263143640 -110000: 1384687523 -109000: 1727931349 -108000: 2861733388 -107000: 963829093 -106000: 431354627 -105000: 3568623360 -104000: 2957399361 -103000: 1071045618 -102000: 3968457714 -101000: 3448338394 -100000: 2586060251 -99000: 3401651822 -98000: 1579089478 -97000: 3722618916 -96000: 759319595 -95000: 1269278712 -94000: 150489448 -93000: 390013662 -92000: 3663029784 -91000: 555197170 -90000: 166476858 -89000: 1658807720 -88000: 3430520531 -87000: 2946861093 -86000: 3000600326 -85000: 300034452 -84000: 2813719249 -83000: 3009927425 -82000: 1127728469 -81000: 2667791855 -80000: 2632316050 -79000: 2180301200 -78000: 418999983 -77000: 4254858933 -76000: 2728734498 -75000: 1863202698 -74000: 4226419921 -73000: 1917572494 -72000: 3117082625 -71000: 1032601538 -70000: 2992135524 -69000: 670119660 -68000: 638731522 -67000: 1460114012 -66000: 1232274665 -65000: 3667669961 -64000: 191277965 -63000: 3868442802 -62000: 700664540 -61000: 2271087482 -60000: 3274078227 -59000: 159900296 -58000: 2778747772 -57000: 2788477153 -56000: 3965957780 -55000: 2276993918 -54000: 1986966104 -53000: 3416414682 -52000: 2162594060 -51000: 2947744069 -50000: 4024793290 -49000: 631161701 -48000: 728285173 -47000: 1487641693 -46000: 4049519424 -45000: 613160608 -44000: 1566126172 -43000: 3731725133 -42000: 2746368727 -41000: 4168967735 -40000: 1319649932 -39000: 2964978784 -38000: 967937134 -37000: 3116555742 -36000: 2279790642 -35000: 2852914953 -34000: 1040410911 -33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 1288319411500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index b41b24d8c..000000000 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,571 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.288611 # Number of seconds simulated -sim_ticks 1288611150500 # Number of ticks simulated -final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2016883 # Simulator instruction rate (inst/s) -host_op_rate 2016883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2798849858 # Simulator tick rate (ticks/s) -host_mem_usage 261432 # Number of bytes of host memory used -host_seconds 460.41 # Real time elapsed on the host -sim_insts 928587629 # Number of instructions simulated -sim_ops 928587629 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18512320 # Number of bytes read from this memory -system.physmem.bytes_read::total 18649344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289255 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291396 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14366103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14472437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3311870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3311870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3311870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14366103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17784307 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237510597 # DTB read hits -system.cpu.dtb.read_misses 194650 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237705247 # DTB read accesses -system.cpu.dtb.write_hits 98301200 # DTB write hits -system.cpu.dtb.write_misses 6871 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98308071 # DTB write accesses -system.cpu.dtb.data_hits 335811797 # DTB hits -system.cpu.dtb.data_misses 201521 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336013318 # DTB accesses -system.cpu.itb.fetch_hits 928789151 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 928789256 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2577222301 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928587629 # Number of instructions committed -system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses -system.cpu.num_func_calls 37048314 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls -system.cpu.num_int_insts 822136244 # number of integer instructions -system.cpu.num_fp_insts 33439365 # number of float instructions -system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read -system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read -system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written -system.cpu.num_mem_refs 336013318 # number of memory refs -system.cpu.num_load_insts 237705247 # Number of load instructions -system.cpu.num_store_insts 98308071 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2577222301 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 123111018 # Number of branches fetched -system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction -system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction -system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction -system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction -system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 928789150 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.168779 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1112572500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.168779 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits -system.cpu.dcache.overall_hits::total 335031269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses -system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20380048000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20380048000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4229584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4229584000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24609632000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24609632000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24609632000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24609632000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28643.214329 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28643.214329 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61285.884024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61285.884024 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31529.467232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31529.467232 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88841 # number of writebacks -system.cpu.dcache.writebacks::total 88841 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19668534000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19668534000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4160570000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4160570000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23829104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23829104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23829104000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23829104000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27643.214329 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27643.214329 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60285.884024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60285.884024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.409268 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.409268 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits -system.cpu.icache.overall_hits::total 928782983 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses -system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 187267500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 187267500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 187267500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 187267500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 187267500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 187267500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30361.138132 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30361.138132 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30361.138132 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30361.138132 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4618 # number of writebacks -system.cpu.icache.writebacks::total 4618 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 181099500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 181099500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 181099500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 181099500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 181099500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 181099500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29361.138132 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29361.138132 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258865 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32717.214949 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1276112 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291633 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.375746 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4209362000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27.944200 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.856544 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32641.414205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000853 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001460 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.996137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998450 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31170 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12833601 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12833601 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88841 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88841 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488907 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488907 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491273 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495300 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491273 # number of overall hits -system.cpu.l2cache.overall_hits::total 495300 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222607 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222607 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289255 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291396 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289255 # number of overall misses -system.cpu.l2cache.overall_misses::total 291396 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4032205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4032205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 129556500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 129556500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13467735000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13467735000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 129556500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17499940000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17629496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 129556500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17499940000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17629496500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88841 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88841 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312864 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312864 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370589 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370405 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370589 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370405 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.051661 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.051661 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.132123 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.132123 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222607 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222607 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289255 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289255 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3365725000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3365725000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 108146500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 108146500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11241665000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11241665000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108146500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14607390000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14715536500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108146500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14607390000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14715536500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312864 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312864 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370405 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370405 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.051661 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.051661 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1726 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1726 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56329920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258865 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1045561 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.040596 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1043835 99.83% 99.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1726 0.17% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1045561 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877332000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 548536 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257140 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224748 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190457 # Transaction distribution -system.membus.trans_dist::ReadExReq 66648 # Transaction distribution -system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224748 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839932 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22917056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22917056 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 291396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 291396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 291396 # Request fanout histogram -system.membus.reqLayer0.occupancy 815280500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456980000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |