diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/alpha')
3 files changed, 1440 insertions, 1400 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index efccfaef5..f751a40d2 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.561049 # Number of seconds simulated -sim_ticks 561048999000 # Number of ticks simulated -final_tick 561048999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.560940 # Number of seconds simulated +sim_ticks 560939897000 # Number of ticks simulated +final_tick 560939897000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 327042 # Simulator instruction rate (inst/s) -host_op_rate 327042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 197554566 # Simulator tick rate (ticks/s) -host_mem_usage 305844 # Number of bytes of host memory used -host_seconds 2839.97 # Real time elapsed on the host +host_inst_rate 309766 # Simulator instruction rate (inst/s) +host_op_rate 309766 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 187082277 # Simulator tick rate (ticks/s) +host_mem_usage 305868 # Number of bytes of host memory used +host_seconds 2998.36 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 186944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470400 # Number of bytes read from this memory -system.physmem.bytes_read::total 18657344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186944 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 186880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18514240 # Number of bytes read from this memory +system.physmem.bytes_read::total 18701120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186880 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288600 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2920 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289285 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292205 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 32921189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33254393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333204 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7606665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7606665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7606665 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 32921189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40861059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291521 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 333155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33005746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33338902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333155 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333155 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7608145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7608145 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7608145 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 333155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33005746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40947046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292205 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291521 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292205 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18639104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18657344 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18680832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18701120 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17937 # Per bank write bursts -system.physmem.perBankRdBursts::1 18285 # Per bank write bursts -system.physmem.perBankRdBursts::2 18301 # Per bank write bursts -system.physmem.perBankRdBursts::3 18253 # Per bank write bursts -system.physmem.perBankRdBursts::4 18160 # Per bank write bursts -system.physmem.perBankRdBursts::5 18247 # Per bank write bursts -system.physmem.perBankRdBursts::6 18325 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18224 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18384 # Per bank write bursts -system.physmem.perBankRdBursts::12 18260 # Per bank write bursts -system.physmem.perBankRdBursts::13 18042 # Per bank write bursts -system.physmem.perBankRdBursts::14 17980 # Per bank write bursts -system.physmem.perBankRdBursts::15 18099 # Per bank write bursts +system.physmem.perBankRdBursts::0 18030 # Per bank write bursts +system.physmem.perBankRdBursts::1 18359 # Per bank write bursts +system.physmem.perBankRdBursts::2 18394 # Per bank write bursts +system.physmem.perBankRdBursts::3 18343 # Per bank write bursts +system.physmem.perBankRdBursts::4 18248 # Per bank write bursts +system.physmem.perBankRdBursts::5 18243 # Per bank write bursts +system.physmem.perBankRdBursts::6 18313 # Per bank write bursts +system.physmem.perBankRdBursts::7 18291 # Per bank write bursts +system.physmem.perBankRdBursts::8 18223 # Per bank write bursts +system.physmem.perBankRdBursts::9 18225 # Per bank write bursts +system.physmem.perBankRdBursts::10 18213 # Per bank write bursts +system.physmem.perBankRdBursts::11 18377 # Per bank write bursts +system.physmem.perBankRdBursts::12 18256 # Per bank write bursts +system.physmem.perBankRdBursts::13 18128 # Per bank write bursts +system.physmem.perBankRdBursts::14 18060 # Per bank write bursts +system.physmem.perBankRdBursts::15 18185 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4188 # Per bank write bursts +system.physmem.perBankWrBursts::9 4185 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 561048916000 # Total gap between requests +system.physmem.totGap 560939815000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291521 # Read request sizes (log2) +system.physmem.readPktSize::6 292205 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,7 +97,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291384 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,117 +193,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105209 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 217.703657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.847395 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 266.018983 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39852 37.88% 37.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43676 41.51% 79.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8737 8.30% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 846 0.80% 88.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1608 1.53% 90.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1088 1.03% 91.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 546 0.52% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 586 0.56% 92.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8270 7.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105209 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4041 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.193764 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.202156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.629260 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4034 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4041 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4041 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.496907 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.475096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.865198 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3038 75.18% 75.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1001 24.77% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4041 # Writes before turning the bus around for reads -system.physmem.totQLat 2859634000 # Total ticks spent queuing -system.physmem.totMemAccLat 8320309000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9818.96 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 103977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 220.682651 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.922946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 267.989820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 38271 36.81% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43979 42.30% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8888 8.55% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 756 0.73% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1408 1.35% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1167 1.12% 90.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 628 0.60% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 577 0.55% 92.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8303 7.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103977 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.413929 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.545155 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 755.096124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 3 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.442765 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.845366 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3112 76.86% 76.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 934 23.07% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads +system.physmem.totQLat 2918754250 # Total ticks spent queuing +system.physmem.totMemAccLat 8391654250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9999.57 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28568.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.25 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28749.57 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing -system.physmem.readRowHits 202235 # Number of row buffer hits during reads -system.physmem.writeRowHits 50448 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.65 # Row buffer hit rate for writes -system.physmem.avgGap 1566283.22 # Average gap between requests -system.physmem.pageHitRate 70.60 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 396718560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 216463500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1137021600 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing +system.physmem.readRowHits 202534 # Number of row buffer hits during reads +system.physmem.writeRowHits 52030 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes +system.physmem.avgGap 1562994.07 # Average gap between requests +system.physmem.pageHitRate 70.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 391812120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 213786375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140274200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 109036341675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240981860250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 388629643425 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.687306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 400213963500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18734560000 # Time in different power states +system.physmem_0.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 109227211875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240749028000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 388576230570 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.726692 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 399826633250 # Time in different power states +system.physmem_0.memoryStateTime::REF 18730920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142097780250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142379745750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 398601000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 217490625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134307200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215544240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36644799360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 109322809425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240730572750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 388664124600 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.748765 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399791677000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18734560000 # Time in different power states +system.physmem_1.actEnergy 394193520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 215085750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136148000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215524800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 109501586505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240508346250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 388608564345 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.784339 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399420466000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18730920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 142520871000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 142786637000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749073 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144364 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157127 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103970968 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513050 # Number of BTB hits +system.cpu.branchPred.lookups 125749081 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144339 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157133 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103971313 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513402 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.323432 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691036 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.323504 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691072 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9449 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237538495 # DTB read hits +system.cpu.dtb.read_hits 237538494 # DTB read hits system.cpu.dtb.read_misses 198467 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736962 # DTB read accesses -system.cpu.dtb.write_hits 98305062 # DTB write hits -system.cpu.dtb.write_misses 7206 # DTB write misses +system.cpu.dtb.read_accesses 237736961 # DTB read accesses +system.cpu.dtb.write_hits 98305022 # DTB write hits +system.cpu.dtb.write_misses 7216 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312268 # DTB write accesses -system.cpu.dtb.data_hits 335843557 # DTB hits -system.cpu.dtb.data_misses 205673 # DTB misses +system.cpu.dtb.write_accesses 98312238 # DTB write accesses +system.cpu.dtb.data_hits 335843516 # DTB hits +system.cpu.dtb.data_misses 205683 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336049230 # DTB accesses -system.cpu.itb.fetch_hits 316986664 # ITB hits +system.cpu.dtb.data_accesses 336049199 # DTB accesses +system.cpu.itb.fetch_hits 316987000 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 316986784 # ITB accesses +system.cpu.itb.fetch_accesses 316987120 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,67 +319,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1122097998 # number of cpu cycles simulated +system.cpu.numCycles 1121879794 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 30863568 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 30863449 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.208130 # CPI: cycles per instruction -system.cpu.ipc 0.827726 # IPC: instructions per cycle -system.cpu.tickCycles 1059712720 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62385278 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.207895 # CPI: cycles per instruction +system.cpu.ipc 0.827887 # IPC: instructions per cycle +system.cpu.tickCycles 1059714780 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62165014 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.688853 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322867255 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.723334 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322867251 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.599378 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 907886250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.688853 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999192 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999192 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 413.599373 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 899878500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.723334 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999200 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999200 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648213290 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648213290 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 224703202 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224703202 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164053 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164053 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 322867255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322867255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322867255 # number of overall hits -system.cpu.dcache.overall_hits::total 322867255 # number of overall hits +system.cpu.dcache.tags.tag_accesses 648213288 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648213288 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 224703201 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224703201 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164050 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164050 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 322867251 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322867251 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 322867251 # number of overall hits +system.cpu.dcache.overall_hits::total 322867251 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137147 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137147 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849076 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849076 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849076 # number of overall misses -system.cpu.dcache.overall_misses::total 849076 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24858122500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24858122500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10112031250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10112031250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34970153750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34970153750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34970153750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34970153750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 225415131 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225415131 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137150 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849079 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849079 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849079 # number of overall misses +system.cpu.dcache.overall_misses::total 849079 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24888612000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24888612000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9943107500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9943107500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34831719500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34831719500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34831719500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34831719500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 225415130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225415130 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 323716331 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323716331 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323716331 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323716331 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 323716330 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323716330 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 323716330 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323716330 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -386,14 +388,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34916.575248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34916.575248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73731.333897 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73731.333897 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41186.129098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41186.129098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41186.129098 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.401850 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.401850 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72498.049581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72498.049581 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41022.943095 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41022.943095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41022.943095 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41022.943095 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -402,16 +404,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91489 # number of writebacks -system.cpu.dcache.writebacks::total 91489 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88848 # number of writebacks +system.cpu.dcache.writebacks::total 88848 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68136 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68136 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68448 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68448 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68448 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68448 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68139 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68139 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68451 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68451 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68451 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68451 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -420,14 +422,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23712269000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23712269000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5006644750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5006644750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28718913750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28718913750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28718913750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28718913750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24170012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24170012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4987370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4987370000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29157382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29157382500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29157382500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29157382500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003157 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -436,24 +438,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002411 system.cpu.dcache.demand_mshr_miss_rate::total 0.002411 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002411 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002411 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33321.673035 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33321.673035 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72548.503137 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72548.503137 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36789.499928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36789.499928 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33964.917224 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33964.917224 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72269.203460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72269.203460 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37351.187121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37351.187121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37351.187121 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37351.187121 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10608 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.311703 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 316974313 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12350 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25665.936275 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10610 # number of replacements +system.cpu.icache.tags.tagsinuse 1686.330189 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 316974647 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12352 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25661.807562 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.311703 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823394 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1686.330189 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823403 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823403 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id @@ -461,44 +463,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 2 system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 633985678 # Number of tag accesses -system.cpu.icache.tags.data_accesses 633985678 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 316974313 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 316974313 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 316974313 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 316974313 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 316974313 # number of overall hits -system.cpu.icache.overall_hits::total 316974313 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12351 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12351 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12351 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12351 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12351 # number of overall misses -system.cpu.icache.overall_misses::total 12351 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 355440500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 355440500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 355440500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 355440500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 355440500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 355440500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 316986664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 316986664 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 316986664 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 316986664 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 316986664 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 316986664 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 633986352 # Number of tag accesses +system.cpu.icache.tags.data_accesses 633986352 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 316974647 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 316974647 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 316974647 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 316974647 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 316974647 # number of overall hits +system.cpu.icache.overall_hits::total 316974647 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12353 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12353 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12353 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12353 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12353 # number of overall misses +system.cpu.icache.overall_misses::total 12353 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 352286000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 352286000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 352286000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 352286000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 352286000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 352286000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 316987000 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 316987000 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 316987000 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 316987000 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 316987000 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 316987000 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28778.277063 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28778.277063 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28778.277063 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28778.277063 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28778.277063 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28778.277063 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28518.254675 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28518.254675 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28518.254675 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28518.254675 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28518.254675 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28518.254675 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,123 +509,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 335642500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 335642500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 335642500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 335642500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 335642500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 335642500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12353 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12353 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12353 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12353 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12353 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12353 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339934000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 339934000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339934000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 339934000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339934000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 339934000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27175.329933 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27175.329933 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27175.329933 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27175.329933 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27175.329933 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27175.329933 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27518.335627 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27518.335627 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27518.335627 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27518.335627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27518.335627 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27518.335627 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258742 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32592.002895 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 523848 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291478 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.797213 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259426 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32593.023927 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218366 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292162 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.170173 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2882.733111 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.797304 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29624.472480 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087974 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002588 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.904067 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994629 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2589.520333 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.221668 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29919.281926 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.079026 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002570 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.913064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994660 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2658 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29475 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7436233 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7436233 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 9429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 489662 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 499091 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 13002157 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13002157 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 88848 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 88848 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9429 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 492028 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501457 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9429 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 492028 # number of overall hits -system.cpu.l2cache.overall_hits::total 501457 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2922 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 221955 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224877 # number of ReadReq misses +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9432 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 9432 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488977 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488977 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 9432 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491343 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 500775 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9432 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 491343 # number of overall hits +system.cpu.l2cache.overall_hits::total 500775 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2922 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288600 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291522 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2922 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288600 # number of overall misses -system.cpu.l2cache.overall_misses::total 291522 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 224288000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17859188000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18083476000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4912763250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4912763250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 224288000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22771951250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22996239250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 224288000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22771951250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22996239250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12351 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 711617 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 723968 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 91489 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792979 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12351 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792981 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12353 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792979 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236580 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.310617 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 792981 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # 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miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236461 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.368491 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236461 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.368491 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72908.440243 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72908.440243 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76128.038343 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76128.038343 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80705.693047 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80705.693047 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76128.038343 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78909.374838 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78881.571563 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76128.038343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78909.374838 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78881.571563 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,103 +642,114 @@ system.cpu.l2cache.fast_writes 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19351356750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187662000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19163694750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19351356750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310617 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2921 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2921 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222640 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222640 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2921 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289285 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292206 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2921 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289285 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292206 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4192533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4192533000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193170000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193170000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15741915500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15741915500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193170000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19934448500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20127618500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193170000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19934448500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20127618500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.367629 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.367629 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64223.819302 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67961.136266 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67912.574430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61210.604697 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61210.604697 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64223.819302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66402.268711 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66380.433552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64223.819302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66402.268711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66380.433552 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.236461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312865 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368491 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368491 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62908.440243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62908.440243 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66131.461828 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66131.461828 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70705.693047 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70705.693047 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66131.461828 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68909.374838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68881.605785 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66131.461828 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68909.374838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68881.605785 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723968 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 891037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677446 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56605888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12353 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 711617 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337788 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2373103 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55646464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56436992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259426 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1839549 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.141027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.348049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1580123 85.90% 85.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 259426 14.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884468 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533723000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19161500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1839549 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 878909500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18528000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222147750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170942000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224876 # Transaction distribution -system.membus.trans_dist::ReadResp 224876 # Transaction distribution +system.membus.trans_dist::ReadResp 225560 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191116 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649725 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649725 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22925056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22925056 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225560 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842209 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22968832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22968832 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358204 # Request fanout histogram +system.membus.snoop_fanout::samples 550004 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358204 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 550004 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358204 # Request fanout histogram -system.membus.reqLayer0.occupancy 732288500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1552393250 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 550004 # Request fanout histogram +system.membus.reqLayer0.occupancy 918579000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1556120750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 887940ec1..7d418bd2e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279669 # Number of seconds simulated -sim_ticks 279668927000 # Number of ticks simulated -final_tick 279668927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279557 # Number of seconds simulated +sim_ticks 279556845500 # Number of ticks simulated +final_tick 279556845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172383 # Simulator instruction rate (inst/s) -host_op_rate 172383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57230702 # Simulator tick rate (ticks/s) -host_mem_usage 232716 # Number of bytes of host memory used -host_seconds 4886.69 # Real time elapsed on the host +host_inst_rate 180071 # Simulator instruction rate (inst/s) +host_op_rate 180071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59759118 # Simulator tick rate (ticks/s) +host_mem_usage 307148 # Number of bytes of host memory used +host_seconds 4678.06 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18476288 # Number of bytes read from this memory -system.physmem.bytes_read::total 18652544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18520448 # Number of bytes read from this memory +system.physmem.bytes_read::total 18696768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176320 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288692 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2755 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289382 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292137 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 630231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66064858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 66695089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 630231 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 630231 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15259872 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15259872 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15259872 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 630231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66064858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 81954961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291446 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 630713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66249310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 66880022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 630713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 630713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15265990 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15265990 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15265990 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 630713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66249310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82146012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292137 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292137 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18633664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18652544 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18678144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265920 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18696768 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17911 # Per bank write bursts -system.physmem.perBankRdBursts::1 18258 # Per bank write bursts -system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18250 # Per bank write bursts -system.physmem.perBankRdBursts::4 18158 # Per bank write bursts -system.physmem.perBankRdBursts::5 18224 # Per bank write bursts -system.physmem.perBankRdBursts::6 18321 # Per bank write bursts -system.physmem.perBankRdBursts::7 18307 # Per bank write bursts -system.physmem.perBankRdBursts::8 18228 # Per bank write bursts +system.physmem.perBankRdBursts::0 18015 # Per bank write bursts +system.physmem.perBankRdBursts::1 18332 # Per bank write bursts +system.physmem.perBankRdBursts::2 18407 # Per bank write bursts +system.physmem.perBankRdBursts::3 18336 # Per bank write bursts +system.physmem.perBankRdBursts::4 18249 # Per bank write bursts +system.physmem.perBankRdBursts::5 18230 # Per bank write bursts +system.physmem.perBankRdBursts::6 18323 # Per bank write bursts +system.physmem.perBankRdBursts::7 18299 # Per bank write bursts +system.physmem.perBankRdBursts::8 18226 # Per bank write bursts system.physmem.perBankRdBursts::9 18222 # Per bank write bursts -system.physmem.perBankRdBursts::10 18213 # Per bank write bursts +system.physmem.perBankRdBursts::10 18209 # Per bank write bursts system.physmem.perBankRdBursts::11 18393 # Per bank write bursts -system.physmem.perBankRdBursts::12 18247 # Per bank write bursts -system.physmem.perBankRdBursts::13 18043 # Per bank write bursts -system.physmem.perBankRdBursts::14 17966 # Per bank write bursts -system.physmem.perBankRdBursts::15 18104 # Per bank write bursts +system.physmem.perBankRdBursts::12 18246 # Per bank write bursts +system.physmem.perBankRdBursts::13 18127 # Per bank write bursts +system.physmem.perBankRdBursts::14 18048 # Per bank write bursts +system.physmem.perBankRdBursts::15 18184 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::6 4262 # Pe system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts system.physmem.perBankWrBursts::9 4180 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts +system.physmem.perBankWrBursts::10 4149 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 279668837500 # Total gap between requests +system.physmem.totGap 279556756000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291446 # Read request sizes (log2) +system.physmem.readPktSize::6 292137 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28307 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2144 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -193,117 +193,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 228.091007 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.320458 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.791024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 35777 35.64% 35.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42525 42.36% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10061 10.02% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 470 0.47% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 508 0.51% 89.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 391 0.39% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 492 0.49% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1510 1.50% 91.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8654 8.62% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100388 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.235658 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.129419 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 756.508896 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.482690 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.461191 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.859365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3072 75.96% 75.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 964 23.84% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 8 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads -system.physmem.totQLat 3601508250 # Total ticks spent queuing -system.physmem.totMemAccLat 9060589500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12369.90 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 99332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.959771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 149.026626 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.596004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 34426 34.66% 34.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42079 42.36% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10100 10.17% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 831 0.84% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1119 1.13% 89.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 640 0.64% 89.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 198 0.20% 89.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1366 1.38% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8573 8.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 99332 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4052 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.011846 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.507282 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 732.804018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4044 99.80% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4052 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4052 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.449901 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.429330 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.841533 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3145 77.62% 77.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 903 22.29% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4052 # Writes before turning the bus around for reads +system.physmem.totQLat 3589265250 # Total ticks spent queuing +system.physmem.totMemAccLat 9061377750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12298.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31119.90 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 66.63 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 66.70 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 15.26 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31048.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 66.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.27 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing -system.physmem.readRowHits 206952 # Number of row buffer hits during reads -system.physmem.writeRowHits 50458 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes -system.physmem.avgGap 780916.48 # Average gap between requests -system.physmem.pageHitRate 71.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378650160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206604750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136467800 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing +system.physmem.readRowHits 207190 # Number of row buffer hits during reads +system.physmem.writeRowHits 51966 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.93 # Row buffer hit rate for writes +system.physmem.avgGap 779100.26 # Average gap between requests +system.physmem.pageHitRate 72.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 374756760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204480375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1139564400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79892908290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97718574000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 197816101560 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.327829 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 162042939000 # Time in different power states -system.physmem_0.memoryStateTime::REF 9338680000 # Time in different power states +system.physmem_0.refreshEnergy 18258829680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80335161315 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97260556500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 197789787510 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.529215 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 161282435500 # Time in different power states +system.physmem_0.memoryStateTime::REF 9334780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108285182250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108932951500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 380207520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 207454500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134088800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80233432560 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 97419868500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 197857002360 # Total energy per rank (pJ) -system.physmem_1.averagePower 707.474077 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 161543146250 # Time in different power states -system.physmem_1.memoryStateTime::REF 9338680000 # Time in different power states +system.physmem_1.actEnergy 375943680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 205128000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1135750200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215485920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18258829680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80056140615 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 97505311500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 197752589595 # Total energy per rank (pJ) +system.physmem_1.averagePower 707.396151 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 161684152500 # Time in different power states +system.physmem_1.memoryStateTime::REF 9334780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108784975000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108531075000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192995150 # Number of BP lookups -system.cpu.branchPred.condPredicted 125739221 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11883936 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 145375032 # Number of BTB lookups -system.cpu.branchPred.BTBHits 127081867 # Number of BTB hits +system.cpu.branchPred.lookups 192642813 # Number of BP lookups +system.cpu.branchPred.condPredicted 125666016 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11886398 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 146763457 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126951211 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.416570 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 29018342 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 86.500559 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 29013974 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 143 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244533779 # DTB read hits -system.cpu.dtb.read_misses 309591 # DTB read misses +system.cpu.dtb.read_hits 244534581 # DTB read hits +system.cpu.dtb.read_misses 309538 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244843370 # DTB read accesses -system.cpu.dtb.write_hits 135671849 # DTB write hits -system.cpu.dtb.write_misses 31346 # DTB write misses +system.cpu.dtb.read_accesses 244844119 # DTB read accesses +system.cpu.dtb.write_hits 135677576 # DTB write hits +system.cpu.dtb.write_misses 31395 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135703195 # DTB write accesses -system.cpu.dtb.data_hits 380205628 # DTB hits -system.cpu.dtb.data_misses 340937 # DTB misses +system.cpu.dtb.write_accesses 135708971 # DTB write accesses +system.cpu.dtb.data_hits 380212157 # DTB hits +system.cpu.dtb.data_misses 340933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380546565 # DTB accesses -system.cpu.itb.fetch_hits 197011138 # ITB hits -system.cpu.itb.fetch_misses 297 # ITB misses +system.cpu.dtb.data_accesses 380553090 # DTB accesses +system.cpu.itb.fetch_hits 197116758 # ITB hits +system.cpu.itb.fetch_misses 277 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 197011435 # ITB accesses +system.cpu.itb.fetch_accesses 197117035 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -317,238 +320,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 559337855 # number of cpu cycles simulated +system.cpu.numCycles 559113692 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202154435 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1649182914 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192995150 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156100209 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 344813807 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24235896 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6519 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 197011138 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7083229 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 559092875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.949748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.175515 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 202267120 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1648589560 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192642813 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 155965185 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 344477338 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24241354 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6562 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 197116758 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7079440 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 558871871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949852 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.174628 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 239653225 42.86% 42.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30449692 5.45% 48.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22058642 3.95% 52.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36467190 6.52% 58.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 68017058 12.17% 70.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21431579 3.83% 74.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19299153 3.45% 78.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3537365 0.63% 78.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118178971 21.14% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 239606568 42.87% 42.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30232310 5.41% 48.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22062681 3.95% 52.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36416175 6.52% 58.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 68096392 12.18% 70.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21641580 3.87% 74.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19299985 3.45% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3539455 0.63% 78.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 117976725 21.11% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 559092875 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.345042 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.948456 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168803167 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 91739479 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273671215 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12767829 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12111185 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15522167 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 6976 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1584668893 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25197 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12111185 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176688622 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61751221 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14050 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278532777 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29995020 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1538585292 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9438 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2658750 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 20386888 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7267964 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1027382191 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1769248125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1729530138 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39717986 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 558871871 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344550 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.948577 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168941255 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 91534254 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273571884 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12710570 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12113908 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15306458 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 6991 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1583914254 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25227 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12113908 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176800339 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61738556 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14140 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278402636 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29802292 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538072104 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9577 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2573672 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 20322038 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7208635 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1027250775 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1768837330 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1729119220 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39718109 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 388415033 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1375 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 100 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9495582 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372551032 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175434243 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40723012 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11258595 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304972518 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1016009395 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8790765 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462590577 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427723515 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 559092875 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.817246 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.904787 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 388283617 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1370 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9395851 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372336921 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175495034 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40680070 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11286315 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304559063 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1015639240 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8789930 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462177116 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427685030 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 558871871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.817302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.903889 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 200119998 35.79% 35.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93029621 16.64% 52.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91384631 16.35% 68.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59843024 10.70% 79.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56522593 10.11% 89.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29852885 5.34% 94.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17077557 3.05% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7239227 1.29% 99.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4023339 0.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 199951896 35.78% 35.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 92994240 16.64% 52.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91399550 16.35% 68.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59708328 10.68% 79.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56828177 10.17% 89.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29755879 5.32% 94.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17031836 3.05% 98.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7177923 1.28% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4024042 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 559092875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 558871871 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2463450 10.43% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15566876 65.90% 76.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5592414 23.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2464205 10.45% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15633751 66.29% 76.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5485030 23.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579702610 57.06% 57.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7931 0.00% 57.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13180646 1.30% 58.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826544 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339801 0.33% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 277022873 27.27% 86.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138927710 13.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579358124 57.04% 57.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7924 0.00% 57.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13180764 1.30% 58.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339800 0.33% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 276992447 27.27% 86.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138932359 13.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1016009395 # Type of FU issued -system.cpu.iq.rate 1.816450 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23622740 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023251 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2552720615 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1726519951 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 940123896 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70804555 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41088367 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34423394 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1003270759 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36360100 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50476055 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1015639240 # Type of FU issued +system.cpu.iq.rate 1.816516 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23582986 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023220 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2551718253 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1725674688 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 939925074 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70805014 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41106869 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34423614 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1002860612 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36360338 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50469534 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 135040435 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1174528 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45615 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77133043 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 134826324 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1160001 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45767 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77193834 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2509 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4123 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2684 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4171 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12111185 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60760024 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 216464 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1479434002 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 17901 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372551032 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175434243 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 87 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21559 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 205996 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45615 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11877701 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16644 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11894345 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976302878 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244843546 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39706517 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12113908 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60768232 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 187260 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479124792 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 20793 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372336921 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175495034 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15841 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 182755 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45767 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11880363 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16467 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11896830 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976089984 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244844291 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39549256 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174461395 # number of nop insts executed -system.cpu.iew.exec_refs 380547191 # number of memory reference insts executed -system.cpu.iew.exec_branches 129259483 # Number of branches executed -system.cpu.iew.exec_stores 135703645 # Number of stores executed -system.cpu.iew.exec_rate 1.745462 # Inst execution rate -system.cpu.iew.wb_sent 975066188 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974547290 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556173359 # num instructions producing a value -system.cpu.iew.wb_consumers 831980820 # num instructions consuming a value +system.cpu.iew.exec_nop 174565646 # number of nop insts executed +system.cpu.iew.exec_refs 380553668 # number of memory reference insts executed +system.cpu.iew.exec_branches 129052167 # Number of branches executed +system.cpu.iew.exec_stores 135709377 # Number of stores executed +system.cpu.iew.exec_rate 1.745781 # Inst execution rate +system.cpu.iew.wb_sent 974867255 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974348688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556190036 # num instructions producing a value +system.cpu.iew.wb_consumers 832343662 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.742323 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668493 # average fanout of values written-back +system.cpu.iew.wb_rate 1.742666 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668222 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543601549 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543293982 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11877174 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 486379014 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.909185 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.596644 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11879630 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 486147412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.910095 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.597279 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 208258289 42.82% 42.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102386957 21.05% 63.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51676822 10.62% 74.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25636051 5.27% 79.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21554637 4.43% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9250657 1.90% 86.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10396507 2.14% 88.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6664753 1.37% 89.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50554341 10.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 208054375 42.80% 42.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102342395 21.05% 63.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51700065 10.63% 74.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25702081 5.29% 79.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21547094 4.43% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9129205 1.88% 86.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10401484 2.14% 88.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6670149 1.37% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50600564 10.41% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 486379014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 486147412 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -594,345 +597,335 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50554341 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1905392712 # The number of ROB reads -system.cpu.rob.rob_writes 3017093514 # The number of ROB writes -system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 244980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 50600564 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1904807320 # The number of ROB reads +system.cpu.rob.rob_writes 3016488956 # The number of ROB writes +system.cpu.timesIdled 3196 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 241821 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.663995 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.663995 # CPI: Total CPI of All Threads -system.cpu.ipc 1.506034 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.506034 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237178642 # number of integer regfile reads -system.cpu.int_regfile_writes 705781417 # number of integer regfile writes -system.cpu.fp_regfile_reads 36689419 # number of floating regfile reads -system.cpu.fp_regfile_writes 24410667 # number of floating regfile writes +system.cpu.cpi 0.663729 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.663729 # CPI: Total CPI of All Threads +system.cpu.ipc 1.506638 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.506638 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237184723 # number of integer regfile reads +system.cpu.int_regfile_writes 705784215 # number of integer regfile writes +system.cpu.fp_regfile_reads 36689750 # number of floating regfile reads +system.cpu.fp_regfile_writes 24410793 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777209 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.895157 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 289903947 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781305 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 371.050930 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 374093250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.895157 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777216 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.910211 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289913128 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781312 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 371.059357 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 371553500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.910211 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999246 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999246 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2498 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 253 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585486411 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585486411 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192496951 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192496951 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97406971 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97406971 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289903922 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289903922 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289903922 # number of overall hits -system.cpu.dcache.overall_hits::total 289903922 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1554376 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1554376 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 894229 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 894229 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2448605 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2448605 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2448605 # number of overall misses -system.cpu.dcache.overall_misses::total 2448605 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84529453750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84529453750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 62304618080 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 62304618080 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 100250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 100250 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 146834071830 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 146834071830 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 146834071830 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 146834071830 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194051327 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194051327 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 585500596 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585500596 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192503314 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192503314 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97409790 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97409790 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 24 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 24 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289913104 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289913104 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289913104 # number of overall hits +system.cpu.dcache.overall_hits::total 289913104 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1555104 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1555104 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 891410 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 891410 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2446514 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2446514 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2446514 # number of overall misses +system.cpu.dcache.overall_misses::total 2446514 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83796204000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83796204000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 61715896841 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 61715896841 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145512100841 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145512100841 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145512100841 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145512100841 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194058418 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194058418 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 26 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 26 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292352527 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292352527 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292352527 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292352527 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009097 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038462 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038462 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008376 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008376 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008376 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008376 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54381.599915 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54381.599915 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69674.119359 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69674.119359 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 100250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 100250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59966.418361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59966.418361 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21964 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 69527 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292359618 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292359618 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292359618 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292359618 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008014 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008014 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009068 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009068 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008368 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008368 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008368 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008368 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53884.630224 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53884.630224 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69234.018960 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69234.018960 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59477.321953 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59477.321953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59477.321953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59477.321953 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 67906 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 515 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.034985 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 135.003883 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.164265 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131.856311 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91524 # number of writebacks -system.cpu.dcache.writebacks::total 91524 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 841911 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 841911 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 825390 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 825390 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1667301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1667301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1667301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1667301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712465 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712465 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68839 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68839 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781304 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781304 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781304 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781304 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23794966500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23794966500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5675142998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5675142998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29470109498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29470109498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29470109498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29470109498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 88850 # number of writebacks +system.cpu.dcache.writebacks::total 88850 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842619 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 842619 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 822583 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 822583 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1665202 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1665202 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1665202 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1665202 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781312 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781312 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781312 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781312 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24145312000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24145312000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5651970498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5651970498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29797282498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29797282498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29797282498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29797282498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038462 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.038462 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33398.084818 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33398.084818 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82440.811139 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82440.811139 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33888.870643 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33888.870643 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82118.507243 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82118.507243 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38137.495006 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38137.495006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38137.495006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38137.495006 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4665 # number of replacements -system.cpu.icache.tags.tagsinuse 1651.262169 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 197002801 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6374 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30907.248353 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4695 # number of replacements +system.cpu.icache.tags.tagsinuse 1651.888032 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 197108400 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6404 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30778.950656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1651.262169 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.806280 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.806280 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1651.888032 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.806586 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.806586 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1547 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 394028650 # Number of tag accesses -system.cpu.icache.tags.data_accesses 394028650 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 197002801 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 197002801 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 197002801 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 197002801 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 197002801 # number of overall hits -system.cpu.icache.overall_hits::total 197002801 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8337 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8337 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8337 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8337 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8337 # number of overall misses -system.cpu.icache.overall_misses::total 8337 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 359956749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 359956749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 359956749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 359956749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 359956749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 359956749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 197011138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 197011138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 197011138 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 197011138 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 197011138 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 197011138 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 394239920 # Number of tag accesses +system.cpu.icache.tags.data_accesses 394239920 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 197108400 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 197108400 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 197108400 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 197108400 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 197108400 # number of overall hits +system.cpu.icache.overall_hits::total 197108400 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8358 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8358 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8358 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8358 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8358 # number of overall misses +system.cpu.icache.overall_misses::total 8358 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354830499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354830499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354830499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354830499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354830499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354830499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 197116758 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 197116758 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 197116758 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 197116758 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 197116758 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 197116758 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43175.812522 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43175.812522 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43175.812522 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43175.812522 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 938 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42453.996052 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42453.996052 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42453.996052 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42453.996052 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42453.996052 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42453.996052 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 620 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.533333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.363636 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1962 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1962 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1962 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1962 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1962 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1962 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6375 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6375 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6375 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6375 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6375 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6375 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 264410499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 264410499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 264410499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 264410499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 264410499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 264410499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1953 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1953 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1953 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1953 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1953 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1953 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6405 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6405 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6405 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6405 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6405 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6405 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268250499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 268250499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268250499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 268250499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268250499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 268250499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41476.156706 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41476.156706 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41476.156706 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41476.156706 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41476.156706 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41476.156706 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41881.420609 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259359 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32631.025486 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1208176 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292097 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.136215 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2805.006533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.921998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29756.513005 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.085602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002103 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2756 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2756 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222754 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222754 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2756 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289382 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 292138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2756 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289382 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 292138 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4859074500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4859074500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192753000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192753000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15700662500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15700662500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192753000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20559737000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20752490000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192753000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20559737000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20752490000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.968050 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.968050 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430289 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312644 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312644 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370867 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370380 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370867 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72928.415981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72928.415981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69939.404935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69939.404935 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70484.312291 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70484.312291 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69939.404935 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71047.048538 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71036.599142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69939.404935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71047.048538 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71036.599142 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 718841 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68839 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68839 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1666883 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 407936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56268992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 879204 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 718889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155533 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 885737 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712485 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339840 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2357344 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55690368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56100224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259359 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1828987 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.141805 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.348850 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 879204 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1569628 85.82% 85.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 259359 14.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 879204 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 531126000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10103500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1828987 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 873664000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 9606000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1213595000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1171968000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224818 # Transaction distribution -system.membus.trans_dist::ReadResp 224818 # Transaction distribution +system.membus.trans_dist::ReadResp 225509 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 191067 # Transaction distribution system.membus.trans_dist::ReadExReq 66628 # Transaction distribution system.membus.trans_dist::ReadExResp 66628 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649575 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649575 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22920256 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225509 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842024 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842024 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22964480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22964480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358129 # Request fanout histogram +system.membus.snoop_fanout::samples 549887 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358129 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 549887 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358129 # Request fanout histogram -system.membus.reqLayer0.occupancy 682357500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1548216750 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 549887 # Request fanout histogram +system.membus.reqLayer0.occupancy 853984000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1551628500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index eff48cf7e..07561ac8e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.286250 # Number of seconds simulated -sim_ticks 1286249817500 # Number of ticks simulated -final_tick 1286249817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.286279 # Number of seconds simulated +sim_ticks 1286278511500 # Number of ticks simulated +final_tick 1286278511500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1412500 # Simulator instruction rate (inst/s) -host_op_rate 1412500 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1956550284 # Simulator tick rate (ticks/s) -host_mem_usage 303116 # Number of bytes of host memory used -host_seconds 657.41 # Real time elapsed on the host +host_inst_rate 1355944 # Simulator instruction rate (inst/s) +host_op_rate 1355944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1878251411 # Simulator tick rate (ticks/s) +host_mem_usage 303804 # Number of bytes of host memory used +host_seconds 684.83 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18465664 # Number of bytes read from this memory -system.physmem.bytes_read::total 18603456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18509184 # Number of bytes read from this memory +system.physmem.bytes_read::total 18646976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288526 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290679 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289206 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291359 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14356203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14463330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3317950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3317950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3317950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14389717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14496842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3317876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3317876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3317876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 14389717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17814717 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2572499635 # number of cpu cycles simulated +system.cpu.numCycles 2572557023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2572499635 # Number of busy cycles +system.cpu.num_busy_cycles 2572557023 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -129,12 +129,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.261321 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4094.261358 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1046537000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261321 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 1046537500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261358 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -162,14 +162,14 @@ system.cpu.dcache.demand_misses::cpu.data 780528 # n system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568558000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18568558000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22264956000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22264956000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22264956000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22264956000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18597166000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18597166000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696410000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3696410000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22293576000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22293576000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22293576000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22293576000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) @@ -186,14 +186,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28525.505811 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26137.456185 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26137.456185 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.292115 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.292115 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28562.173298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28562.173298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28562.173298 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -202,8 +202,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks -system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.writebacks::writebacks 89031 # number of writebacks +system.cpu.dcache.writebacks::total 89031 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses @@ -212,14 +212,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780528 system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17501287000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17501287000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3592877000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3592877000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21094164000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21094164000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21094164000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17885652000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17885652000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3627396000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3627396000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21513048000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21513048000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21513048000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21513048000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -228,22 +228,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25137.456185 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25137.456185 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52560.292115 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52560.292115 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27562.173298 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27562.173298 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.486238 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.486224 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486238 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486224 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id @@ -266,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170610500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170610500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170610500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170610500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170610500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170684500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170684500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170684500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170684500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170684500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170684500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -284,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27660.586900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27660.586900 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27672.584306 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27672.584306 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27672.584306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27672.584306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27672.584306 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,38 +304,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161358500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 161358500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161358500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 161358500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161358500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 161358500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 164516500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 164516500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 164516500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 164516500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 164516500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 164516500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26672.584306 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26672.584306 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26672.584306 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26672.584306 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257900 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32657.894008 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258580 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32657.927159 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207050 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291314 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.143467 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249705 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996640 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2486.879631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.811890 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30121.235638 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.075894 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001520 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.919227 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996641 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id @@ -343,78 +343,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1144 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7386496 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7386496 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 4015 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 489636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 493651 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 91660 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 91660 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 12902296 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12902296 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 89031 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 89031 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4015 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4015 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488956 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 488956 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 4015 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 492002 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 496017 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 491322 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 495337 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 4015 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 492002 # number of overall hits -system.cpu.l2cache.overall_hits::total 496017 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2153 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 221878 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224031 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 491322 # number of overall hits +system.cpu.l2cache.overall_hits::total 495337 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2153 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 2153 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222558 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222558 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 2153 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288526 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290679 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 289206 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291359 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses -system.cpu.l2cache.overall_misses::total 290679 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113033000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11648595000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11761628000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499020000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3499020000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 113033000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15147615000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15260648000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 113033000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15147615000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15260648000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 91660 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 91660 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 289206 # number of overall misses +system.cpu.l2cache.overall_misses::total 291359 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499032000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3499032000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 113105000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 113105000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 11684343000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 11684343000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 113105000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15183375000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15296480000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 113105000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15183375000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15296480000 # number of overall miss cycles +system.cpu.l2cache.Writeback_accesses::writebacks 89031 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 89031 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311839 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.312159 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.349060 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.349060 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312795 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312795 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.349060 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369655 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.369493 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.370526 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370358 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.370526 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370358 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.180050 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.180050 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 52533.673943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 52533.673943 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 52500.215674 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 52500.215674 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.454765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52533.673943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.207465 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.454765 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -425,103 +431,114 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2153 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221878 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224031 # number of ReadReq MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 238 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 238 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2153 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2153 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222558 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222558 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288526 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290679 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 289206 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291359 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 87196500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8986059000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9073255500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699244000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699244000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87196500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11685303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11772499500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87196500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11685303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11772499500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 289206 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291359 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2832552000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2832552000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91575000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91575000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9458763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9458763000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91575000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12291315000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12382890000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91575000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12291315000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12382890000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.349060 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312795 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312795 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370358 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370526 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370358 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.180050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.180050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42533.673943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42533.673943 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42500.215674 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500.215674 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42533.673943 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500.207465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42500.454765 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155714 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 883916 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 878356 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55651776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56046528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258580 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1826326 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.141585 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.348624 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 878356 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1567746 85.84% 85.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 258580 14.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 878356 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1826326 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 872904000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224031 # Transaction distribution -system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224711 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::CleanEvict 190417 # Transaction distribution system.membus.trans_dist::ReadExReq 66648 # Transaction distribution system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 224711 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839818 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839818 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22914688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22914688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 357362 # Request fanout histogram +system.membus.snoop_fanout::samples 548514 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 548514 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 357362 # Request fanout histogram -system.membus.reqLayer0.occupancy 636219000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1453395500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 548514 # Request fanout histogram +system.membus.reqLayer0.occupancy 815261292 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1456808792 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |