diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 26 |
1 files changed, 21 insertions, 5 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index a4f9b9a0f..77ad5d4bc 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.326731 # Nu sim_ticks 326731324000 # Number of ticks simulated final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 188423 # Simulator instruction rate (inst/s) -host_op_rate 231974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96095829 # Simulator tick rate (ticks/s) -host_mem_usage 319396 # Number of bytes of host memory used -host_seconds 3400.06 # Real time elapsed on the host +host_inst_rate 187465 # Simulator instruction rate (inst/s) +host_op_rate 230795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 95607340 # Simulator tick rate (ticks/s) +host_mem_usage 320048 # Number of bytes of host memory used +host_seconds 3417.43 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory @@ -295,6 +296,7 @@ system.physmem_1.memoryStateTime::REF 10910120000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 174663372 # Number of BP lookups system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect @@ -309,6 +311,7 @@ system.cpu.branchPred.indirectHits 16701520 # Nu system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -338,6 +341,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -367,6 +371,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -396,6 +401,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -426,6 +432,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 326731324000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 653462649 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -716,6 +723,7 @@ system.cpu.cc_regfile_reads 3322370942 # nu system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes system.cpu.misc_regfile_reads 606830949 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2756452 # number of replacements system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. @@ -733,6 +741,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits @@ -863,6 +872,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1979880 # number of replacements system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. @@ -880,6 +890,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 333 system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits @@ -954,12 +965,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 301370 # number of replacements system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks. @@ -986,6 +999,7 @@ system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits @@ -1167,6 +1181,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution @@ -1202,6 +1217,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # La system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 326731324000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 951856 # Transaction distribution system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution system.membus.trans_dist::CleanEvict 227102 # Transaction distribution |