diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/o3-timing')
-rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1261 |
1 files changed, 631 insertions, 630 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 96fe6f71c..2843a5b3f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.625047 # Number of seconds simulated -sim_ticks 625047295000 # Number of ticks simulated -final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.627778 # Number of seconds simulated +sim_ticks 627777658000 # Number of ticks simulated +final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72768 # Simulator instruction rate (inst/s) -host_op_rate 99100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32855066 # Simulator tick rate (ticks/s) -host_mem_usage 309740 # Number of bytes of host memory used -host_seconds 19024.38 # Real time elapsed on the host +host_inst_rate 102547 # Simulator instruction rate (inst/s) +host_op_rate 139655 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46502403 # Simulator tick rate (ticks/s) +host_mem_usage 263380 # Number of bytes of host memory used +host_seconds 13499.90 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory -system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155456 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 30397824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2429 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474966 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 248711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48384947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48633657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 248711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 248711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6767923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6767923 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6767923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 248711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48384947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55401580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474974 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 246813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48174508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48421322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 246813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6738488 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6738488 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6738488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 246813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48174508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474966 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545412 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30398336 # Total number of bytes read from memory +system.physmem.cpureqs 545370 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30397824 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4340 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29693 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29628 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29731 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29793 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29624 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29606 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis +system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4306 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29720 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29627 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29652 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 625047219500 # Total gap between requests +system.physmem.totGap 627777588500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474974 # Categorize read packet sizes +system.physmem.readPktSize::6 474966 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -102,15 +102,15 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4340 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4306 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 407751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 302 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -138,7 +138,7 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see @@ -161,7 +161,7 @@ system.physmem.wrQLenPdf::19 2873 # Wh system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -171,36 +171,36 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3340611483 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 18115671483 # Sum of mem lat for all requests -system.physmem.totBusLat 1899232000 # Total cycles spent in databus access -system.physmem.totBankLat 12875828000 # Total cycles spent in bank access -system.physmem.avgQLat 7035.71 # Average queueing delay per request -system.physmem.avgBankLat 27117.97 # Average bank access latency per request -system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38153.68 # Average memory access latency -system.physmem.avgRdBW 48.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.totQLat 3183088396 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 21162955896 # Sum of mem lat for all requests +system.physmem.totBusLat 2374030000 # Total cycles spent in databus access +system.physmem.totBankLat 15605837500 # Total cycles spent in bank access +system.physmem.avgQLat 6703.98 # Average queueing delay per request +system.physmem.avgBankLat 32867.82 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 44571.80 # Average memory access latency +system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 17.44 # Average write queue length over time -system.physmem.readRowHits 249146 # Number of row buffer hits during reads -system.physmem.writeRowHits 48036 # Number of row buffer hits during writes -system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes -system.physmem.avgGap 1155201.56 # Average gap between requests -system.cpu.branchPred.lookups 438808047 # Number of BP lookups -system.cpu.branchPred.condPredicted 349805436 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30625316 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 249957064 # Number of BTB lookups -system.cpu.branchPred.BTBHits 227370417 # Number of BTB hits +system.physmem.avgWrQLen 17.42 # Average write queue length over time +system.physmem.readRowHits 143321 # Number of row buffer hits during reads +system.physmem.writeRowHits 45521 # Number of row buffer hits during writes +system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes +system.physmem.avgGap 1160264.94 # Average gap between requests +system.cpu.branchPred.lookups 438315949 # Number of BP lookups +system.cpu.branchPred.condPredicted 349727895 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30635218 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 247833729 # Number of BTB lookups +system.cpu.branchPred.BTBHits 226959272 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.963789 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52357585 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806128 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806740 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,238 +244,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1250094591 # number of cpu cycles simulated +system.cpu.numCycles 1255555317 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 279728002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 600743262 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 158308312 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133148695 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11515 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333206369 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10414827 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1215386936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.589820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.189306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 353470069 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2285596028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 438315949 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 279264186 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 600835407 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 132516295 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 333121638 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 10719820 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1213960668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592464 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 614688205 50.58% 50.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42445352 3.49% 54.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 95116159 7.83% 61.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55675580 4.58% 66.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 72776602 5.99% 72.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42276531 3.48% 75.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31131234 2.56% 78.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31565180 2.60% 81.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 229712093 18.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 613169619 50.51% 50.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42771995 3.52% 54.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71974347 5.93% 72.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 42167025 3.47% 75.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30997749 2.55% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 230060885 18.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1215386936 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351020 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.829826 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 402796361 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 106301870 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561862491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16807396 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 127618818 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44638184 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3046676123 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27895 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 127618818 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 438124604 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 35349497 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 425259 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 541326873 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72541885 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2975830632 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4806802 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56918075 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2945274289 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14167459331 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13596684512 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570774819 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1213960668 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 402973564 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105163486 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561876522 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16833920 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 127113176 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44705456 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3047243338 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 127113176 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 438520822 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34436909 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 439020 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 541081767 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 72368974 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2975054938 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4810929 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 57090218 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2946030157 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14164065012 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13593632114 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570432898 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 952134199 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23805 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 21281 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 197120926 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 972834043 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 492760757 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36385181 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 42690468 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2809386355 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28039 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2437787250 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13304140 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 911537771 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2374413817 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6655 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1215386936 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.005770 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875210 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 952890067 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25235 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 195466607 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 973207419 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 490834558 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40613994 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2806590548 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2437414927 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13391010 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 908731725 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2361150738 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1213960668 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875088 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 379434397 31.22% 31.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183109361 15.07% 46.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 202931100 16.70% 62.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 170113731 14.00% 76.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132526126 10.90% 87.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 93839529 7.72% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37911750 3.12% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12465689 1.03% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3055253 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 377941740 31.13% 31.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183591562 15.12% 46.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 202672032 16.70% 62.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169721528 13.98% 76.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132842997 10.94% 87.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 93759242 7.72% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37926001 3.12% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12454015 1.03% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1215386936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1213960668 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 714674 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24388 0.03% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55116913 62.89% 63.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31779800 36.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55152383 62.89% 63.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1108876695 45.49% 45.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11224297 0.46% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502220 0.23% 46.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23416324 0.96% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838276108 34.39% 81.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442239839 18.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1108357182 45.47% 45.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502589 0.23% 46.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23405387 0.96% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838249114 34.39% 81.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442425362 18.15% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2437787250 # Type of FU issued -system.cpu.iq.rate 1.950082 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87635775 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035949 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6069393440 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3638225906 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2254362609 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122507911 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82793715 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56449336 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2462106345 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63316680 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84343916 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2437414927 # Type of FU issued +system.cpu.iq.rate 1.941304 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87694307 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6067361460 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3632711634 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2254358298 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122514379 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82707337 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56439823 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2461788389 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63320845 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84306518 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341446862 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7743 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429272 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 215765460 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 341820238 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8584 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429957 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 213839261 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 127618818 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 13752826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1562574 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2809426795 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1398231 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 972834043 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 492760757 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18053 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1558945 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429272 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32529008 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1513965 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 34042973 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2363631235 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792642751 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 74156015 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 127113176 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12638060 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1558330 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2806632420 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 973207419 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 490834558 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1554339 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1429957 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32461973 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33956379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2363518803 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792548176 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12401 # number of nop insts executed -system.cpu.iew.exec_refs 1216279993 # number of memory reference insts executed -system.cpu.iew.exec_branches 322475744 # Number of branches executed -system.cpu.iew.exec_stores 423637242 # Number of stores executed -system.cpu.iew.exec_rate 1.890762 # Inst execution rate -system.cpu.iew.wb_sent 2336496726 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310811945 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347866502 # num instructions producing a value -system.cpu.iew.wb_consumers 2524860722 # num instructions consuming a value +system.cpu.iew.exec_nop 12468 # number of nop insts executed +system.cpu.iew.exec_refs 1216269109 # number of memory reference insts executed +system.cpu.iew.exec_branches 322574295 # Number of branches executed +system.cpu.iew.exec_stores 423720933 # Number of stores executed +system.cpu.iew.exec_rate 1.882449 # Inst execution rate +system.cpu.iew.wb_sent 2336489279 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2310798121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347631532 # num instructions producing a value +system.cpu.iew.wb_consumers 2523967593 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.848510 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533838 # average fanout of values written-back +system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 924090552 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 921296208 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30613261 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1087768118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.733215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398367 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30621417 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1086847492 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734683 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398806 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 447474994 41.14% 41.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288616071 26.53% 67.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95091930 8.74% 76.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70192926 6.45% 82.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46475898 4.27% 87.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22197093 2.04% 89.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15849951 1.46% 90.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10985154 1.01% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884101 8.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 446547765 41.09% 41.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288590720 26.55% 67.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95114963 8.75% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46461872 4.27% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22187807 2.04% 89.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15847038 1.46% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10983680 1.01% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884052 8.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1087768118 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1086847492 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -486,200 +487,200 @@ system.cpu.commit.branches 299634395 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884101 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884052 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3806292582 # The number of ROB reads -system.cpu.rob.rob_writes 5746483501 # The number of ROB writes -system.cpu.timesIdled 353075 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34707655 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3802577661 # The number of ROB reads +system.cpu.rob.rob_writes 5740389540 # The number of ROB writes +system.cpu.timesIdled 353175 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 41594649 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.903006 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.903006 # CPI: Total CPI of All Threads -system.cpu.ipc 1.107413 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.107413 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11775193288 # number of integer regfile reads -system.cpu.int_regfile_writes 2227107160 # number of integer regfile writes -system.cpu.fp_regfile_reads 68795849 # number of floating regfile reads -system.cpu.fp_regfile_writes 49561296 # number of floating regfile writes -system.cpu.misc_regfile_reads 1363965830 # number of misc regfile reads +system.cpu.cpi 0.906950 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11774707522 # number of integer regfile reads +system.cpu.int_regfile_writes 2226782313 # number of integer regfile writes +system.cpu.fp_regfile_reads 68797358 # number of floating regfile reads +system.cpu.fp_regfile_writes 49551948 # number of floating regfile writes +system.cpu.misc_regfile_reads 1364040381 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.icache.replacements 22468 # number of replacements -system.cpu.icache.tagsinuse 1641.255803 # Cycle average of tags in use -system.cpu.icache.total_refs 333171598 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24150 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13795.925383 # Average number of references to valid blocks. +system.cpu.icache.replacements 22740 # number of replacements +system.cpu.icache.tagsinuse 1642.119595 # Cycle average of tags in use +system.cpu.icache.total_refs 333085984 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13639.884685 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1641.255803 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801394 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801394 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 333175666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 333175666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 333175666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 333175666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 333175666 # number of overall hits -system.cpu.icache.overall_hits::total 333175666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 30702 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 30702 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 30702 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 30702 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 30702 # number of overall misses -system.cpu.icache.overall_misses::total 30702 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 468488500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 468488500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 468488500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 468488500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 468488500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 468488500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333206368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333206368 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333206368 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333206368 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333206368 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333206368 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15259.217641 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15259.217641 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15259.217641 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15259.217641 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1109 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1642.119595 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 333090009 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 333090009 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 333090009 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 333090009 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 333090009 # number of overall hits +system.cpu.icache.overall_hits::total 333090009 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31628 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31628 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31628 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31628 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31628 # number of overall misses +system.cpu.icache.overall_misses::total 31628 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 481224999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 481224999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 481224999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 481224999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 481224999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 481224999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 333121637 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 333121637 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 333121637 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 333121637 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 333121637 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 333121637 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15215.157424 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15215.157424 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15215.157424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15215.157424 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15215.157424 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.607143 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 32.692308 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 474974 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2429 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 474966 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2421 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96251295 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20717048717 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20813300012 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43404340 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43404340 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2393684509 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2393684509 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96251295 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23110733226 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23206984521 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96251295 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23110733226 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23206984521 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277545 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274674 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999309 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999309 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_misses::total 474966 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103136612 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23729331565 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23832468177 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43064306 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43064306 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2356932012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2356932012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103136612 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26086263577 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26189400189 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103136612 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26086263577 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26189400189 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277510 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999304 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999304 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.304239 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.304239 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39625.893372 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50968.210980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50900.833732 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.304145 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099136 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.304145 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42600.831062 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58379.047814 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58285.626676 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36226.780310 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36226.780310 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35670.556368 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35670.556368 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42600.831062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55203.765942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55139.526175 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532939 # number of replacements -system.cpu.dcache.tagsinuse 4094.623683 # Cycle average of tags in use -system.cpu.dcache.total_refs 970042937 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537035 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.113109 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 332181000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.623683 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999664 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693909081 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693909081 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276100966 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276100966 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1533127 # number of replacements +system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use +system.cpu.dcache.total_refs 969988260 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.000356 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 693861551 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693861551 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093814 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093814 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 970010047 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 970010047 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 970010047 # number of overall hits -system.cpu.dcache.overall_hits::total 970010047 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953320 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953320 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 834712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 834712 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 969955365 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969955365 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969955365 # number of overall hits +system.cpu.dcache.overall_hits::total 969955365 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 841864 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 841864 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2788032 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2788032 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2788032 # number of overall misses -system.cpu.dcache.overall_misses::total 2788032 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 67394089000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 67394089000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39986185470 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39986185470 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 171500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 107380274470 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 107380274470 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 107380274470 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 107380274470 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695862401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695862401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2795405 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795405 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795405 # number of overall misses +system.cpu.dcache.overall_misses::total 2795405 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66482799000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66482799000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39425610969 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39425610969 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105908409969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105908409969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105908409969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105908409969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695815092 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695815092 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972798079 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972798079 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972798079 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972798079 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972750770 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972750770 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972750770 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972750770 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003040 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34502.328855 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34502.328855 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47904.169905 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47904.169905 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38514.720947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38514.720947 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2182 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 795 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 88 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.964286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.034091 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34031.944556 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34031.944556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46831.330202 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46831.330202 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37886.606760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37886.606760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37886.606760 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 90 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807018 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.300000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96308 # number of writebacks -system.cpu.dcache.writebacks::total 96308 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488800 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488800 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757854 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 757854 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks +system.cpu.dcache.writebacks::total 96321 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765039 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765039 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1246654 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1246654 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1246654 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1246654 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464520 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464520 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76858 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76858 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541378 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541378 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541378 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541378 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37907812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 37907812500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3481886500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3481886500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41389699000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41389699000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41389699000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41389699000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1253873 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1253873 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1253873 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1253873 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76825 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76825 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541532 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541532 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541532 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541532 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831551000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831551000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240718500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44240718500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240718500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44240718500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25884.120736 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25884.120736 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45302.850712 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45302.850712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.941259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.941259 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44375.756590 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44375.756590 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.189183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.189183 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |