diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 659 |
1 files changed, 659 insertions, 0 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e69de29bb..a634350c6 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -0,0 +1,659 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 1.045756 # Number of seconds simulated +sim_ticks 1045756396500 # Number of ticks simulated +final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 554447 # Simulator instruction rate (inst/s) +host_op_rate 681172 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 906860836 # Simulator tick rate (ticks/s) +host_mem_usage 273604 # Number of bytes of host memory used +host_seconds 1153.16 # Real time elapsed on the host +sim_insts 639366787 # Number of instructions simulated +sim_ops 785501035 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory +system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 673 # Number of system calls +system.cpu.numCycles 2091512793 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 639366787 # Number of instructions committed +system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses +system.cpu.num_func_calls 37261296 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls +system.cpu.num_int_insts 682251400 # number of integer instructions +system.cpu.num_fp_insts 24239771 # number of float instructions +system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read +system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written +system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read +system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written +system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read +system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written +system.cpu.num_mem_refs 381221435 # number of memory refs +system.cpu.num_load_insts 252240938 # Number of load instructions +system.cpu.num_store_insts 128980497 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 137364860 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction +system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction +system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction +system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 788730744 # Class of executed instruction +system.cpu.dcache.tags.replacements 778046 # number of replacements +system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits +system.cpu.dcache.overall_hits::total 378498833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses +system.cpu.dcache.overall_misses::total 782143 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks +system.cpu.dcache.writebacks::total 88995 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27300.708593 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27300.708593 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58717.719949 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58717.719949 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12705.035971 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12705.035971 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency +system.cpu.icache.tags.replacements 8769 # number of replacements +system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 643367692 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 643367692 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 643367692 # number of overall hits +system.cpu.icache.overall_hits::total 643367692 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses +system.cpu.icache.overall_misses::total 10208 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 219076500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 219076500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 219076500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 219076500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 8769 # number of writebacks +system.cpu.icache.writebacks::total 8769 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency +system.cpu.l2cache.tags.replacements 257772 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits +system.cpu.l2cache.overall_hits::total 501982 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1759 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1759 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222516 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 222516 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1759 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288609 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 290368 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1759 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288609 # number of overall misses +system.cpu.l2cache.overall_misses::total 290368 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3932586500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17277322500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 88995 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 8752 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 8752 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 69323 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 10208 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59556.281978 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59501.233619 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59501.233619 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59501.468826 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59556.281978 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.134753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59501.468826 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks +system.cpu.l2cache.writebacks::total 66098 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1759 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1759 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222516 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 257772 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 224275 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution +system.membus.trans_dist::CleanEvict 190094 # Transaction distribution +system.membus.trans_dist::ReadExReq 66093 # Transaction distribution +system.membus.trans_dist::ReadExResp 66093 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 546561 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 546561 # Request fanout histogram +system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |