diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 87 |
1 files changed, 72 insertions, 15 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 6675fca21..4610b3f7b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 2.369902 # Nu sim_ticks 2369901960000 # Number of ticks simulated final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 495417 # Simulator instruction rate (inst/s) -host_op_rate 672068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 849801430 # Simulator tick rate (ticks/s) -host_mem_usage 234976 # Number of bytes of host memory used -host_seconds 2788.77 # Real time elapsed on the host +host_inst_rate 768078 # Simulator instruction rate (inst/s) +host_op_rate 1041952 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1317503901 # Simulator tick rate (ticks/s) +host_mem_usage 235416 # Number of bytes of host memory used +host_seconds 1798.78 # Real time elapsed on the host sim_insts 1381604347 # Number of instructions simulated sim_ops 1874244950 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 94696320 # Number of bytes read from this memory -system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory -system.physmem.bytes_written 4230336 # Number of bytes written to this memory -system.physmem.num_reads 1479630 # Number of read requests responded to by this memory -system.physmem.num_writes 66099 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 39957906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 41742932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94551872 # Number of bytes read from this memory +system.physmem.bytes_read::total 94696320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1477373 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479630 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 60951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39896955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39957906 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60951 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1785026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1785026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1785026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39896955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41742932 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 1390271511 # nu system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18786.850477 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18786.850477 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18786.850477 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 312627000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312627000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 312627000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15786.850477 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 897271092 # nu system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54574.204602 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54458.738711 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54458.738711 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51574.204602 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1478755 # number of replacements system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 1533653 system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.954657 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.963303 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.952476 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.952476 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59094920000 system.cpu.l2cache.overall_mshr_miss_latency::total 59185200000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966052 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.954657 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.952476 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.952476 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |