diff options
Diffstat (limited to 'tests/long/se/40.perlbmk/ref/arm')
6 files changed, 1224 insertions, 1183 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini index 4149684ba..bcc7e805c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout index 99e686564..2e501adb4 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:40:10 -gem5 executing on e108600-lin, pid 23109 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 21:05:24 +gem5 executing on e108600-lin, pid 17596 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second @@ -650,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 512588680500 because target called exit() +Exiting @ tick 525654485500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 228ad0113..d38edd9f8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.512877 # Number of seconds simulated -sim_ticks 512876814500 # Number of ticks simulated -final_tick 512876814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.525654 # Number of seconds simulated +sim_ticks 525654485500 # Number of ticks simulated +final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169706 # Simulator instruction rate (inst/s) -host_op_rate 208931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 135858559 # Simulator tick rate (ticks/s) -host_mem_usage 281524 # Number of bytes of host memory used -host_seconds 3775.08 # Real time elapsed on the host +host_inst_rate 213828 # Simulator instruction rate (inst/s) +host_op_rate 263250 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175444467 # Simulator tick rate (ticks/s) +host_mem_usage 278324 # Number of bytes of host memory used +host_seconds 2996.13 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory @@ -26,64 +26,64 @@ system.physmem.num_reads::cpu.data 288664 # Nu system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 320077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36021312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36341389 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 320077 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 320077 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8248125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8248125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8248125 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 320077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36021312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44589514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291229 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18616640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228352 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue +system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18285 # Per bank write bursts -system.physmem.perBankRdBursts::1 18130 # Per bank write bursts -system.physmem.perBankRdBursts::2 18219 # Per bank write bursts -system.physmem.perBankRdBursts::3 18177 # Per bank write bursts +system.physmem.perBankRdBursts::0 18281 # Per bank write bursts +system.physmem.perBankRdBursts::1 18133 # Per bank write bursts +system.physmem.perBankRdBursts::2 18221 # Per bank write bursts +system.physmem.perBankRdBursts::3 18176 # Per bank write bursts system.physmem.perBankRdBursts::4 18285 # Per bank write bursts -system.physmem.perBankRdBursts::5 18413 # Per bank write bursts -system.physmem.perBankRdBursts::6 18173 # Per bank write bursts -system.physmem.perBankRdBursts::7 17985 # Per bank write bursts -system.physmem.perBankRdBursts::8 18026 # Per bank write bursts -system.physmem.perBankRdBursts::9 18055 # Per bank write bursts -system.physmem.perBankRdBursts::10 18102 # Per bank write bursts -system.physmem.perBankRdBursts::11 18206 # Per bank write bursts -system.physmem.perBankRdBursts::12 18220 # Per bank write bursts -system.physmem.perBankRdBursts::13 18274 # Per bank write bursts -system.physmem.perBankRdBursts::14 18073 # Per bank write bursts -system.physmem.perBankRdBursts::15 18262 # Per bank write bursts +system.physmem.perBankRdBursts::5 18412 # Per bank write bursts +system.physmem.perBankRdBursts::6 18178 # Per bank write bursts +system.physmem.perBankRdBursts::7 17990 # Per bank write bursts +system.physmem.perBankRdBursts::8 18034 # Per bank write bursts +system.physmem.perBankRdBursts::9 18056 # Per bank write bursts +system.physmem.perBankRdBursts::10 18101 # Per bank write bursts +system.physmem.perBankRdBursts::11 18200 # Per bank write bursts +system.physmem.perBankRdBursts::12 18218 # Per bank write bursts +system.physmem.perBankRdBursts::13 18271 # Per bank write bursts +system.physmem.perBankRdBursts::14 18077 # Per bank write bursts +system.physmem.perBankRdBursts::15 18258 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts -system.physmem.perBankWrBursts::1 4098 # Per bank write bursts -system.physmem.perBankWrBursts::2 4134 # Per bank write bursts +system.physmem.perBankWrBursts::1 4099 # Per bank write bursts +system.physmem.perBankWrBursts::2 4135 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4223 # Per bank write bursts +system.physmem.perBankWrBursts::4 4224 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4092 # Per bank write bursts -system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4095 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4138 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 512876719500 # Total gap between requests +system.physmem.totGap 525654384500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,91 +194,101 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 110420 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 206.874986 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.678155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.334201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45202 40.94% 40.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43704 39.58% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9014 8.16% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2046 1.85% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 604 0.55% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 569 0.52% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 621 0.56% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 527 0.48% 92.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8133 7.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 110420 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4015 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.540971 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.171361 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.693530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4013 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4015 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4015 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.455293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.434809 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.838731 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3101 77.24% 77.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 914 22.76% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4015 # Writes before turning the bus around for reads -system.physmem.totQLat 2756382250 # Total ticks spent queuing -system.physmem.totMemAccLat 8210476000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9475.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads +system.physmem.totQLat 15538679500 # Total ticks spent queuing +system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers +system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28225.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 36.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 36.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.35 # Data bus utilization in percentage +system.physmem.busUtil 0.34 # Data bus utilization in percentage system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.56 # Average write queue length when enqueuing -system.physmem.readRowHits 194946 # Number of row buffer hits during reads -system.physmem.writeRowHits 51576 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes -system.physmem.avgGap 1435314.77 # Average gap between requests -system.physmem.pageHitRate 69.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 418362840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 228273375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136124600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 103989168945 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 216505087500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 355990887180 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.111511 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 359471319000 # Time in different power states -system.physmem_0.memoryStateTime::REF 17125940000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 136275516000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 416336760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 227167875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 33498338640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 103752790515 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216712437000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 355952056350 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.035798 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359820444250 # Time in different power states -system.physmem_1.memoryStateTime::REF 17125940000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 135926935750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 147261658 # Number of BP lookups +system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing +system.physmem.readRowHits 202495 # Number of row buffer hits during reads +system.physmem.writeRowHits 51707 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes +system.physmem.avgGap 1471073.79 # Average gap between requests +system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ) +system.physmem_0.averagePower 407.411950 # Core power per rank (mW) +system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states +system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ) +system.physmem_1.averagePower 406.546781 # Core power per rank (mW) +system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states +system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 147261657 # Number of BP lookups system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups -system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits +system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups +system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. @@ -288,7 +298,7 @@ system.cpu.branchPred.indirectHits 15988941 # Nu system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -318,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -348,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -378,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,16 +419,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 512876814500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1025753629 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1051308971 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.601101 # CPI: cycles per instruction -system.cpu.ipc 0.624570 # IPC: instructions per cycle +system.cpu.cpi 1.640991 # CPI: cycles per instruction +system.cpu.ipc 0.609388 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction @@ -454,28 +464,28 @@ system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 955906199 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69847430 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778100 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.223033 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 804340500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.223033 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999078 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999078 # Average percentage of cache occupancy +system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits @@ -500,14 +510,14 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24857030500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24857030500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10252359000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10252359000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35109389500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35109389500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35109389500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35109389500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) @@ -532,14 +542,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34853.209935 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34853.209935 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74447.825898 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74447.825898 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41261.281531 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41261.281531 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41254.445417 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41254.445417 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -566,16 +576,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057 system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24135855500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24135855500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5141186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5141186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1790000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1790000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29277041500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29277041500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29278831500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29278831500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -586,70 +596,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33863.715827 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33863.715827 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74163.844090 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74163.844090 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12877.697842 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12877.697842 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37435.943288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37435.943288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37431.579169 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37431.579169 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 24885 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.965016 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 257789646 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9678.241703 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.965016 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835920 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835920 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 515659202 # Number of tag accesses -system.cpu.icache.tags.data_accesses 515659202 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 257789646 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 257789646 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 257789646 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 257789646 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 257789646 # number of overall hits -system.cpu.icache.overall_hits::total 257789646 # number of overall hits +system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses +system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits +system.cpu.icache.overall_hits::total 257789639 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses system.cpu.icache.overall_misses::total 26637 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 518689000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 518689000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 518689000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 518689000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 518689000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 518689000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 257816283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 257816283 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 257816283 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 257816283 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 257816283 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 257816283 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19472.500657 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19472.500657 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19472.500657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19472.500657 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19472.500657 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20268.442392 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20268.442392 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20268.442392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20268.442392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20268.442392 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -664,48 +674,48 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 26637 system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 492053000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 492053000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 492053000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 492053000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 492053000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 492053000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 513254500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 513254500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 513254500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 513254500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 513254500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 513254500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18472.538199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18472.538199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18472.538199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18472.538199 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19268.479934 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19268.479934 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19268.479934 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19268.479934 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 258837 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32655.350813 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32651.524409 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1316948 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291605 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.516205 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 3732066000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 41.642986 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.982590 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32524.725237 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001271 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002716 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.992576 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996562 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 3958369000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 41.514151 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.268254 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.742004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.001267 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002724 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.992454 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996445 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29221 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 13160277 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 13160277 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 88688 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits @@ -734,18 +744,18 @@ system.cpu.l2cache.demand_misses::total 291260 # nu system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses system.cpu.l2cache.overall_misses::total 291260 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5003275000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5003275000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 198116500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 198116500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17918475000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17918475000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 198116500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 22921750000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23119866500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 198116500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 22921750000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23119866500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5351609000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5351609000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 219318000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 219318000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30330402000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 30330402000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 219318000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 35682011000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35901329000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 219318000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 35682011000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35901329000 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 88688 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) @@ -774,18 +784,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.360099 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.360099 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75702.818841 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75702.818841 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77088.132296 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77088.132296 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80496.655421 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80496.655421 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 79378.790428 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77088.132296 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79399.182514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 79378.790428 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80973.339789 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80973.339789 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85337.743191 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85337.743191 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136255.787313 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136255.787313 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 123262.133489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85337.743191 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123599.747134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 123262.133489 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -816,18 +826,18 @@ system.cpu.l2cache.demand_mshr_misses::total 291230 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4342365000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4342365000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 172194500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 172194500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15690918500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15690918500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 172194500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20033283500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20205478000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 172194500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20033283500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20205478000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses @@ -840,25 +850,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65702.818841 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65702.818841 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67106.196415 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67106.196415 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70497.852390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70497.852390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67106.196415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69400.006582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69379.796037 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution @@ -898,7 +908,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 512876814500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 225138 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution system.membus.trans_dist::CleanEvict 190702 # Transaction distribution @@ -921,9 +931,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 291229 # Request fanout histogram -system.membus.reqLayer0.occupancy 917201000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554703000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 2ff40d14a..155d03811 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 0920df90d..4ad08cdbb 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:20:09 -gem5 executing on e108600-lin, pid 12407 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:55:26 +gem5 executing on e108600-lin, pid 17505 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -650,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 326731324000 because target called exit() +Exiting @ tick 339012932000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2975218ad..0a89473ad 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.327896 # Number of seconds simulated -sim_ticks 327895638000 # Number of ticks simulated -final_tick 327895638000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.339013 # Number of seconds simulated +sim_ticks 339012932000 # Number of ticks simulated +final_tick 339012932000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125299 # Simulator instruction rate (inst/s) -host_op_rate 154259 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64130088 # Simulator tick rate (ticks/s) -host_mem_usage 277300 # Number of bytes of host memory used -host_seconds 5112.98 # Real time elapsed on the host +host_inst_rate 140345 # Simulator instruction rate (inst/s) +host_op_rate 172783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74266222 # Simulator tick rate (ticks/s) +host_mem_usage 275384 # Number of bytes of host memory used +host_seconds 4564.83 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 266368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48003200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12980224 # Number of bytes read from this memory -system.physmem.bytes_read::total 61249792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 266368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 266368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244096 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244096 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750050 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202816 # Number of read requests responded to by this memory -system.physmem.num_reads::total 957028 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66314 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66314 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 812356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146397800 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 39586449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186796605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 812356 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 812356 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12943435 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12943435 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12943435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 812356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146397800 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 39586449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 199740040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 957029 # Number of read requests accepted -system.physmem.writeReqs 66314 # Number of write requests accepted -system.physmem.readBursts 957029 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66314 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61231232 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue -system.physmem.bytesWritten 4237440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61249856 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 72 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 269632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48043328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12965504 # Number of bytes read from this memory +system.physmem.bytes_read::total 61278464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 269632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 269632 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4245696 # Number of bytes written to this memory +system.physmem.bytes_written::total 4245696 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4213 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750677 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202586 # Number of read requests responded to by this memory +system.physmem.num_reads::total 957476 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66339 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66339 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 795344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141715325 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 38244866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 180755535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 795344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 795344 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12523699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12523699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12523699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 795344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141715325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 38244866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193279235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 957477 # Number of read requests accepted +system.physmem.writeReqs 66339 # Number of write requests accepted +system.physmem.readBursts 957477 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66339 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61258752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19776 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240576 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61278528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4245696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 309 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 54 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19913 # Per bank write bursts -system.physmem.perBankRdBursts::1 19609 # Per bank write bursts -system.physmem.perBankRdBursts::2 657177 # Per bank write bursts -system.physmem.perBankRdBursts::3 20974 # Per bank write bursts -system.physmem.perBankRdBursts::4 19738 # Per bank write bursts -system.physmem.perBankRdBursts::5 20841 # Per bank write bursts -system.physmem.perBankRdBursts::6 19544 # Per bank write bursts -system.physmem.perBankRdBursts::7 20056 # Per bank write bursts -system.physmem.perBankRdBursts::8 19527 # Per bank write bursts -system.physmem.perBankRdBursts::9 20071 # Per bank write bursts -system.physmem.perBankRdBursts::10 19467 # Per bank write bursts -system.physmem.perBankRdBursts::11 19786 # Per bank write bursts -system.physmem.perBankRdBursts::12 19618 # Per bank write bursts -system.physmem.perBankRdBursts::13 21115 # Per bank write bursts -system.physmem.perBankRdBursts::14 19501 # Per bank write bursts -system.physmem.perBankRdBursts::15 19801 # Per bank write bursts -system.physmem.perBankWrBursts::0 4241 # Per bank write bursts -system.physmem.perBankWrBursts::1 4104 # Per bank write bursts -system.physmem.perBankWrBursts::2 4141 # Per bank write bursts -system.physmem.perBankWrBursts::3 4151 # Per bank write bursts -system.physmem.perBankWrBursts::4 4245 # Per bank write bursts -system.physmem.perBankWrBursts::5 4233 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankRdBursts::0 19910 # Per bank write bursts +system.physmem.perBankRdBursts::1 19533 # Per bank write bursts +system.physmem.perBankRdBursts::2 657271 # Per bank write bursts +system.physmem.perBankRdBursts::3 20982 # Per bank write bursts +system.physmem.perBankRdBursts::4 19710 # Per bank write bursts +system.physmem.perBankRdBursts::5 21143 # Per bank write bursts +system.physmem.perBankRdBursts::6 19634 # Per bank write bursts +system.physmem.perBankRdBursts::7 20055 # Per bank write bursts +system.physmem.perBankRdBursts::8 19495 # Per bank write bursts +system.physmem.perBankRdBursts::9 20079 # Per bank write bursts +system.physmem.perBankRdBursts::10 19428 # Per bank write bursts +system.physmem.perBankRdBursts::11 19728 # Per bank write bursts +system.physmem.perBankRdBursts::12 19649 # Per bank write bursts +system.physmem.perBankRdBursts::13 21208 # Per bank write bursts +system.physmem.perBankRdBursts::14 19490 # Per bank write bursts +system.physmem.perBankRdBursts::15 19853 # Per bank write bursts +system.physmem.perBankWrBursts::0 4286 # Per bank write bursts +system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.perBankWrBursts::2 4145 # Per bank write bursts +system.physmem.perBankWrBursts::3 4153 # Per bank write bursts +system.physmem.perBankWrBursts::4 4249 # Per bank write bursts +system.physmem.perBankWrBursts::5 4230 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::10 4094 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4151 # Per bank write bursts +system.physmem.perBankWrBursts::15 4149 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 327895627500 # Total gap between requests +system.physmem.totGap 339012921500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 957029 # Read request sizes (log2) +system.physmem.readPktSize::6 957477 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66314 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 765529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6427 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2470 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1057 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 621 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66339 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 764538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6841 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -149,175 +149,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 627 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 194181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 337.148207 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.280987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 364.158297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 64676 33.31% 33.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60636 31.23% 64.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15729 8.10% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3217 1.66% 74.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3574 1.84% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2317 1.19% 77.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2364 1.22% 78.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 21831 11.24% 89.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19837 10.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 194181 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3990 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 177.226065 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.842577 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1813.556545 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 3969 99.47% 99.47% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 4 0.10% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 2 0.05% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-32767 2 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::86016-90111 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3990 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3990 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.593985 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.513577 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.886226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3332 83.51% 83.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 5 0.13% 83.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 452 11.33% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 50 1.25% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 19 0.48% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 17 0.43% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.25% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 19 0.48% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.30% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 15 0.38% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 16 0.40% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.38% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 9 0.23% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.13% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.10% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.08% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.03% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 3 0.08% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3990 # Writes before turning the bus around for reads -system.physmem.totQLat 12587538724 # Total ticks spent queuing -system.physmem.totMemAccLat 30526376224 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4783690000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13156.72 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 195212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 335.517735 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.597798 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.506182 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 64341 32.96% 32.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 60661 31.07% 64.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15753 8.07% 72.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3211 1.64% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3578 1.83% 75.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2458 1.26% 76.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2478 1.27% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34211 17.53% 95.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8521 4.36% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 195212 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3994 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 204.692539 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.349556 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2360.542955 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3971 99.42% 99.42% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 10 0.25% 99.67% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 5 0.13% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 1 0.03% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-32767 1 0.03% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::69632-73727 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::98304-102399 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3994 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3994 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.589634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.506417 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.926291 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3368 84.33% 84.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 17 0.43% 84.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 396 9.91% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 46 1.15% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.60% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 17 0.43% 96.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.53% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.45% 97.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 15 0.38% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.43% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.33% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 10 0.25% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.18% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 8 0.20% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 8 0.20% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 4 0.10% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3994 # Writes before turning the bus around for reads +system.physmem.totQLat 27473404757 # Total ticks spent queuing +system.physmem.totMemAccLat 45420304757 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4785840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28702.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31906.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 186.74 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 186.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 12.94 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47452.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 180.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 12.51 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 180.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.56 # Data bus utilization in percentage -system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing -system.physmem.readRowHits 805843 # Number of row buffer hits during reads -system.physmem.writeRowHits 22921 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.23 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.60 # Row buffer hit rate for writes -system.physmem.avgGap 320416.15 # Average gap between requests -system.physmem.pageHitRate 81.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 934317720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 509796375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6223237800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216334800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 220944760020 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2925699000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 253170624435 # Total energy per rank (pJ) -system.physmem_0.averagePower 772.109253 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3595093339 # Time in different power states -system.physmem_0.memoryStateTime::REF 10949120000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 313351421161 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 533690640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 291200250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1239209400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 21416478720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88116969465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 119441319000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 231251573475 # Total energy per rank (pJ) -system.physmem_1.averagePower 705.261391 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 198129163855 # Time in different power states -system.physmem_1.memoryStateTime::REF 10949120000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 118816573145 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174659739 # Number of BP lookups -system.cpu.branchPred.condPredicted 119113225 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015668 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720974 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67755362 # Number of BTB hits +system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing +system.physmem.readRowHits 805066 # Number of row buffer hits during reads +system.physmem.writeRowHits 23137 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.91 # Row buffer hit rate for writes +system.physmem.avgGap 331126.81 # Average gap between requests +system.physmem.pageHitRate 80.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 894020820 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 475164360 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5699412180 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174541140 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27331811520.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14462317590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 674820000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 138340924320 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 704060640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 673701120.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 189477322380 # Total energy per rank (pJ) +system.physmem_0.averagePower 558.908824 # Core power per rank (mW) +system.physmem_0.totalIdleTime 305437641889 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 528629764 # Time in different power states +system.physmem_0.memoryStateTime::REF 11569144000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 223118500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1833570381 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21477516347 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 303380953008 # Time in different power states +system.physmem_1.actEnergy 499878540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 265665180 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134760200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171330840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 25420895760.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 7011060990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1362065280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 70491607590 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 31027049280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 25487678070 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 162872491950 # Total energy per rank (pJ) +system.physmem_1.averagePower 480.431501 # Core power per rank (mW) +system.physmem_1.totalIdleTime 320089357075 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2604072271 # Time in different power states +system.physmem_1.memoryStateTime::REF 10809446000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 84703185250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 80799625521 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5510033904 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 154586569054 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174656775 # Number of BP lookups +system.cpu.branchPred.condPredicted 119110803 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4015685 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96721345 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67754534 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.052398 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18785155 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716286 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16701799 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14487 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279501 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 70.051274 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18785121 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299599 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16716580 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16702336 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14244 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279516 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -347,7 +359,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -377,7 +389,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -407,7 +419,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -438,85 +450,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 655791277 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678025865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 34353189 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824276690 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174659739 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103242316 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 616975428 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 34354212 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824273790 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174656775 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103241991 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 639159762 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8068079 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2457 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3170 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247740649 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12515 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 655368010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.551156 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.253828 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3206 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247740942 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12520 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 677553693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.500365 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.263651 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 193301276 29.50% 29.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148337850 22.63% 52.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72946568 11.13% 63.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240782316 36.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 215486043 31.80% 31.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148340760 21.89% 53.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72943473 10.77% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240783417 35.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 655368010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.266334 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.256919 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75112130 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 236493276 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277761287 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61980307 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021010 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20809608 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13112 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924575224 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11804312 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021010 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118055519 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 135785787 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 212608 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 294557237 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102735849 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906541412 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891100 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27959034 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218150 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49337765 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 468731 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980926815 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4318009248 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001835221 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457086 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 677553693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257596 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215697 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75112537 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258679606 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277758053 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 61982472 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4021025 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 20810112 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13117 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924576668 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 11804380 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4021025 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118056358 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 157938220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 213059 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 294555904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102769127 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906541450 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6890856 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27990855 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2220094 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49338949 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 500517 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980921468 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318014727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001837715 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106148585 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6844 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6835 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138814111 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271882035 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160585921 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6159068 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12159693 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899827224 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12580 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860029296 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216848 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111114846 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244387313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 426 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 655368010 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.312285 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.094624 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 106143238 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6838 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138815476 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271882151 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160587217 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6164479 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12153288 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899827421 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860030622 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9216880 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111115045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244388609 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 677553693 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.269317 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101593 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 192710599 29.40% 29.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182406257 27.83% 57.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 175554116 26.79% 84.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 92275656 14.08% 98.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12419071 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 214894884 31.72% 31.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182407403 26.92% 58.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 175555467 25.91% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 92273782 13.62% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12419846 1.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -524,9 +536,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 655368010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 677553693 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66605310 24.62% 24.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66603323 24.62% 24.62% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available @@ -555,13 +567,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 134121363 49.58% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69112589 25.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 134116736 49.58% 74.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 69116750 25.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413090005 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187656 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413090046 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187659 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -583,88 +595,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550150 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478194 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 266665504 31.01% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 157232585 18.28% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 266665907 31.01% 81.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 157233466 18.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860029296 # Type of FU issued -system.cpu.iq.rate 1.311438 # Inst issue rate -system.cpu.iq.fu_busy_cnt 270494293 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314518 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2597595667 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980331886 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820082893 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 57542076 # Number of floating instruction queue reads +system.cpu.iq.FU_type_0::total 860030622 # Type of FU issued +system.cpu.iq.rate 1.268433 # Inst issue rate +system.cpu.iq.fu_busy_cnt 270491840 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2619781164 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980332291 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820083655 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 57542493 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 30641581 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878673 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1098503163 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32020426 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13986768 # Number of loads that had data forwarded from stores +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878671 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1098501615 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 32020847 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13986301 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19641097 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18820 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31605425 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19641213 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 120 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18827 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31606721 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17201 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918912 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 17820 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021010 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10590461 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6281 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899849934 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4021025 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10591534 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6199 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899849877 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271882035 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160585921 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6840 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 959 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3423 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18820 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295129 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290187 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585316 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850173752 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263373804 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855544 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271882151 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160587217 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 967 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3331 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18827 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3295145 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3289956 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6585101 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850175089 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263374398 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9855533 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10130 # number of nop insts executed -system.cpu.iew.exec_refs 416063188 # number of memory reference insts executed -system.cpu.iew.exec_branches 143381327 # Number of branches executed -system.cpu.iew.exec_stores 152689384 # Number of stores executed -system.cpu.iew.exec_rate 1.296409 # Inst execution rate -system.cpu.iew.wb_sent 846297655 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844961566 # cumulative count of insts written-back -system.cpu.iew.wb_producers 487343298 # num instructions producing a value -system.cpu.iew.wb_consumers 808106626 # num instructions consuming a value -system.cpu.iew.wb_rate 1.288461 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.603068 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103169122 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9874 # number of nop insts executed +system.cpu.iew.exec_refs 416064413 # number of memory reference insts executed +system.cpu.iew.exec_branches 143381564 # Number of branches executed +system.cpu.iew.exec_stores 152690015 # Number of stores executed +system.cpu.iew.exec_rate 1.253898 # Inst execution rate +system.cpu.iew.wb_sent 846298256 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844962326 # cumulative count of insts written-back +system.cpu.iew.wb_producers 487342605 # num instructions producing a value +system.cpu.iew.wb_consumers 808106527 # num instructions consuming a value +system.cpu.iew.wb_rate 1.246210 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.603067 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103169288 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002654 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 640787345 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.230876 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.070419 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4002671 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 662973012 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.047483 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 350447626 54.69% 54.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137241088 21.42% 76.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51341072 8.01% 84.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28220230 4.40% 88.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14380949 2.24% 90.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774505 2.31% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871971 1.23% 94.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561231 1.02% 95.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29948673 4.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 372633677 56.21% 56.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137240232 20.70% 76.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51341106 7.74% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28220443 4.26% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14381462 2.17% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14774618 2.23% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871678 1.19% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6561077 0.99% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29948719 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 640787345 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 662973012 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -710,82 +722,82 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29948673 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1502729113 # The number of ROB reads -system.cpu.rob.rob_writes 1798382436 # The number of ROB writes -system.cpu.timesIdled 10485 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 423267 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29948719 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1524914900 # The number of ROB reads +system.cpu.rob.rob_writes 1798382781 # The number of ROB writes +system.cpu.timesIdled 10519 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 472172 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.023635 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.023635 # CPI: Total CPI of All Threads -system.cpu.ipc 0.976910 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.976910 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868461212 # number of integer regfile reads -system.cpu.int_regfile_writes 500699124 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616064 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959493 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322386264 # number of cc regfile reads -system.cpu.cc_regfile_writes 369207629 # number of cc regfile writes -system.cpu.misc_regfile_reads 606832888 # number of misc regfile reads +system.cpu.cpi 1.058342 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.058342 # CPI: Total CPI of All Threads +system.cpu.ipc 0.944874 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944874 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868463326 # number of integer regfile reads +system.cpu.int_regfile_writes 500698648 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616063 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959490 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322389826 # number of cc regfile reads +system.cpu.cc_regfile_writes 369207773 # number of cc regfile writes +system.cpu.misc_regfile_reads 606833337 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756458 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.912011 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371050492 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756970 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.586336 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 274880000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.912011 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999828 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999828 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756453 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.911144 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371050846 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756965 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.586709 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 285699000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.911144 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751746846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751746846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243126867 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243126867 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907624 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907624 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751747893 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751747893 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243127355 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243127355 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127907428 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127907428 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371034491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371034491 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371037648 # number of overall hits -system.cpu.dcache.overall_hits::total 371037648 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1043853 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1043853 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371034783 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371034783 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371037940 # number of overall hits +system.cpu.dcache.overall_hits::total 371037940 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2401348 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2401348 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044049 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044049 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3445163 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3445163 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3445810 # number of overall misses -system.cpu.dcache.overall_misses::total 3445810 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 69278020000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 69278020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9882341350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9882341350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 168500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 168500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 79160361350 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 79160361350 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 79160361350 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 79160361350 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245528177 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245528177 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3445397 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3445397 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3446044 # number of overall misses +system.cpu.dcache.overall_misses::total 3446044 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80462385500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80462385500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10017236850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10017236850 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 90479622350 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90479622350 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90479622350 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90479622350 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245528703 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245528703 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -794,469 +806,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374479654 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374479654 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374483458 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374483458 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 374480180 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374480180 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374483984 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374483984 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008096 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008096 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.009200 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.009200 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28850.094324 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28850.094324 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9467.177227 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9467.177227 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22977.247042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22977.247042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22972.932736 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22972.932736 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 322646 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4628 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 69.716076 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756458 # number of writebacks -system.cpu.dcache.writebacks::total 2756458 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365828 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365828 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 322833 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 322833 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 688661 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 688661 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 688661 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 688661 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035482 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035482 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721020 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721020 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33507.174096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33507.174096 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9594.604133 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9594.604133 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26261.015015 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26261.015015 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26256.084470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26256.084470 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 71 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 355259 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4691 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 75.732040 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2756453 # number of writebacks +system.cpu.dcache.writebacks::total 2756453 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365871 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 365871 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323013 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323013 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 688884 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 688884 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 688884 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 688884 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035477 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035477 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721036 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 721036 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756502 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756502 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2757144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2757144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64102936000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64102936000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5940509850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5940509850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5561000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5561000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 70043445850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 70043445850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 70049006850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 70049006850 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756513 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756513 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2757155 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2757155 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75218139500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75218139500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5959023850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5959023850 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5957500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5957500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 81177163350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 81177163350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 81183120850 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 81183120850 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005592 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005592 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31492.755033 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31492.755033 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8239.036157 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8239.036157 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8661.993769 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8661.993769 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25410.264839 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25410.264839 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25406.365010 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25406.365010 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36953.568869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36953.568869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8264.530273 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8264.530273 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9279.595016 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9279.595016 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29449.222024 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29449.222024 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29444.525553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29444.525553 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1979522 # number of replacements -system.cpu.icache.tags.tagsinuse 510.874726 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245757404 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 510.550232 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 245757624 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1980032 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.117895 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 264413500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.874726 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997802 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy +system.cpu.icache.tags.avg_refs 124.118006 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 275112500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.550232 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997168 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997168 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497461440 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497461440 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 245757408 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245757408 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245757408 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245757408 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245757408 # number of overall hits -system.cpu.icache.overall_hits::total 245757408 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1983209 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1983209 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1983209 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1983209 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1983209 # number of overall misses -system.cpu.icache.overall_misses::total 1983209 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16177953926 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16177953926 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16177953926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16177953926 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16177953926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16177953926 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 247740617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247740617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247740617 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247740617 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247740617 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247740617 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 497462038 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497462038 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 245757684 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245757684 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245757684 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245757684 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245757684 # number of overall hits +system.cpu.icache.overall_hits::total 245757684 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1983224 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1983224 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1983224 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1983224 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1983224 # number of overall misses +system.cpu.icache.overall_misses::total 1983224 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16215368926 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16215368926 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16215368926 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16215368926 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16215368926 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16215368926 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247740908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247740908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247740908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247740908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247740908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247740908 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.008005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.008005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.008005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.008005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.008005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8157.462943 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8157.462943 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8157.462943 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8157.462943 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8157.462943 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 75964 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 122 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2856 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.598039 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.400000 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8176.266991 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8176.266991 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8176.266991 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.266991 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8176.266991 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 83168 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 761 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2904 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.639118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 108.714286 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 1979522 # number of writebacks system.cpu.icache.writebacks::total 1979522 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3001 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3001 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3001 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3001 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3001 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3001 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980208 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1980208 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1980208 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1980208 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1980208 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1980208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15149087440 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15149087440 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15149087440 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15149087440 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15149087440 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15149087440 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3000 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3000 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3000 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3000 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3000 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3000 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980224 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1980224 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1980224 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1980224 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1980224 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1980224 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15180539440 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15180539440 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15180539440 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15180539440 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15180539440 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15180539440 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007993 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.007993 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007993 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.007993 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7650.250600 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7650.250600 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7650.250600 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7650.250600 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7650.250600 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7650.250600 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350340 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355050 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 4121 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7666.071838 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7666.071838 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7666.071838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7666.071838 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350153 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355017 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 4256 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790102 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 297234 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16098.063865 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3815891 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 313429 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.174658 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4789879 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 297323 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16097.800949 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3937547 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 313525 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 12.558957 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15670.505298 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 427.558566 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.956452 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.026096 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982548 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 418 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15777 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15677.943381 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 419.857568 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.956906 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.025626 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.982532 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 424 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15778 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 92 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1577 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3842 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9849 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025513 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962952 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145585225 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145585225 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 735545 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 735545 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3357840 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3357840 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718742 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718742 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975871 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1975871 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1286733 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1286733 # 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number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 749391 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4164 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 751495 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 755659 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4164 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 751495 # number of overall misses -system.cpu.l2cache.overall_misses::total 755659 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 179065000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 179065000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 319741500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 319741500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 52681851500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 52681851500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 319741500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 52860916500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 53180658000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 319741500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 52860916500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 53180658000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 735545 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 735545 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3357840 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3357840 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 174 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 174 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 273 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1549 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3670 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10056 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.025879 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963013 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145579085 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145579085 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 735952 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 735952 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 3357075 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 3357075 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718660 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718660 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1975820 # 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number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4215 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 4215 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 750316 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 750316 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4215 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 752502 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 756717 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4215 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 752502 # number of overall misses +system.cpu.l2cache.overall_misses::total 756717 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 197785000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 197785000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 351484000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 351484000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 63803558500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 63803558500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 351484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 64001343500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 64352827500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 351484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 64001343500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 64352827500 # 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number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036124 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2036124 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036119 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 2036119 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 1980035 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756970 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 4737005 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2756965 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 4737000 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 1980035 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756970 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 4737005 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2756965 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 4737000 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002919 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002919 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002103 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002103 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368048 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368048 # 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average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70299.551903 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70376.529625 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76787.103746 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70341.008922 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70376.529625 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003033 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003033 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.002129 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.002129 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.368503 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.368503 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.002129 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.272946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.159746 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.002129 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.272946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.159746 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90478.042086 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90478.042086 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83388.849348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83388.849348 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85035.583008 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85035.583008 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85042.132660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83388.849348 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85051.393219 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85042.132660 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3678 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 66314 # number of writebacks -system.cpu.l2cache.writebacks::total 66314 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 742 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 742 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 3567 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 66339 # number of writebacks +system.cpu.l2cache.writebacks::total 66339 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 48582269000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 294714000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 48287555000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16536801285 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 65119070285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 1825 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1826 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202675 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202675 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 190 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 190 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4214 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4214 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 749290 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 749290 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4214 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 750677 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 754891 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4214 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 750677 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202675 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 957566 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 20310287954 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2871000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2871000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 146425000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 146425000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 326144500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 326144500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59240775500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59240775500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 326144500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59387200500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59713345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 326144500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59387200500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 20310287954 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80023632954 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002102 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367703 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367703 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.159217 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272056 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.002128 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367999 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.159361 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.002128 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272284 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202053 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 81496.600949 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15114.942529 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15114.942529 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97808.002937 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97808.002937 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70793.658419 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70793.658419 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64318.301482 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64318.301482 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64414.520832 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70793.658419 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64379.114726 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 81496.600949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68035.976715 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9473332 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736180 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 642769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202146 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100211.116092 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15110.526316 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15110.526316 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 105569.574621 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 105569.574621 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77395.467489 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77395.467489 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79062.546544 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79062.546544 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79101.943194 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77395.467489 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79111.522666 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100211.116092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83569.835347 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9473354 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736191 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 89 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 88 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016330 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801859 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 230920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 258553 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4016341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 802291 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4000023 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 230984 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 255300 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 190 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036124 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939763 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270746 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14210509 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5939779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270763 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14210542 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253411520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606270912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 555960 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4255168 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5293139 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.121491 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.326697 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606270272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 552812 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4257792 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5290002 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121634 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.326863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4650072 87.85% 87.85% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 643066 12.15% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4646559 87.84% 87.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 643442 12.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5293139 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9472646000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2970310996 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5290002 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9472652000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2970335495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135552978 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1254437 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 940010 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 4135554975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1254990 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 940467 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 327895638000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 955666 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66314 # Transaction distribution -system.membus.trans_dist::CleanEvict 230920 # Transaction distribution -system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 1362 # Transaction distribution -system.membus.trans_dist::ReadExResp 1362 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 955667 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211465 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2211465 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65493888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65493888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 339012932000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 956088 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66339 # Transaction distribution +system.membus.trans_dist::CleanEvict 230984 # Transaction distribution +system.membus.trans_dist::UpgradeReq 190 # Transaction distribution +system.membus.trans_dist::ReadExReq 1387 # Transaction distribution +system.membus.trans_dist::ReadExResp 1387 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 956090 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2212465 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2212465 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65524096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65524096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957203 # Request fanout histogram +system.membus.snoop_fanout::samples 957667 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957203 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 957667 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957203 # Request fanout histogram -system.membus.reqLayer0.occupancy 1755655982 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 957667 # Request fanout histogram +system.membus.reqLayer0.occupancy 1758860478 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5035261795 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5031633569 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |