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-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini90
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr1
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout10
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt1011
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini89
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr1
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout10
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt12
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini27
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr1
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout8
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt11
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini82
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr1
-rwxr-xr-xtests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt12
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini111
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr1
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout10
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt1063
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini82
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt12
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini42
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt11
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini77
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout8
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt12
32 files changed, 1698 insertions, 1126 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
index cd33c8a8d..ca9122542 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -55,6 +64,7 @@ decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -97,12 +107,17 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
+threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -118,11 +133,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -130,13 +152,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -146,6 +173,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -154,8 +182,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -553,13 +586,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -569,6 +607,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -577,8 +616,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -602,13 +646,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -618,6 +667,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -626,19 +676,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -646,6 +708,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -660,7 +729,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
kvmInSE=false
@@ -692,9 +761,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -738,6 +813,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -749,7 +825,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr
index 41d370561..8954fa36f 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr
@@ -1,5 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
index 0aa9c6519..b5d01fab2 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 20:54:01
-gem5 started Sep 14 2015 21:30:12
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:28
+gem5 executing on e108600-lin, pid 4301
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
2000: 2845746745
1000: 2068042552
0: 290958364
-Exiting @ tick 560939659000 because target called exit()
+Exiting @ tick 508215534000 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index 383495cbc..f21f0115d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,70 +1,70 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.504258 # Number of seconds simulated
-sim_ticks 504258263000 # Number of ticks simulated
-final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.508216 # Number of seconds simulated
+sim_ticks 508215534000 # Number of ticks simulated
+final_tick 508215534000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 532728 # Simulator instruction rate (inst/s)
-host_op_rate 532728 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 289228716 # Simulator tick rate (ticks/s)
-host_mem_usage 306284 # Number of bytes of host memory used
-host_seconds 1743.46 # Real time elapsed on the host
+host_inst_rate 266071 # Simulator instruction rate (inst/s)
+host_op_rate 266071 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 145588775 # Simulator tick rate (ticks/s)
+host_mem_usage 258712 # Number of bytes of host memory used
+host_seconds 3490.76 # Real time elapsed on the host
sim_insts 928789150 # Number of instructions simulated
sim_ops 928789150 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory
-system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 185088 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 185088 # Number of instructions bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 185920 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 18520192 # Number of bytes read from this memory
+system.physmem.bytes_read::total 18706112 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 185920 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 185920 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2892 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 289375 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 292267 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2905 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 289378 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 292283 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 367050 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 36727212 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 37094262 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 367050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 367050 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 8463346 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 8463346 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 8463346 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 367050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 36727212 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 45557607 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 292267 # Number of read requests accepted
+system.physmem.bw_read::cpu.inst 365829 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 36441609 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 36807438 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 365829 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 365829 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 8397445 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 8397445 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 8397445 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 365829 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 36441609 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 45204883 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 292283 # Number of read requests accepted
system.physmem.writeReqs 66683 # Number of write requests accepted
-system.physmem.readBursts 292267 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 292283 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 18685248 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4266176 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 18705088 # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM 18687040 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 19072 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 18706112 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 298 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 18033 # Per bank write bursts
-system.physmem.perBankRdBursts::1 18363 # Per bank write bursts
-system.physmem.perBankRdBursts::2 18394 # Per bank write bursts
-system.physmem.perBankRdBursts::3 18341 # Per bank write bursts
-system.physmem.perBankRdBursts::4 18245 # Per bank write bursts
-system.physmem.perBankRdBursts::5 18249 # Per bank write bursts
-system.physmem.perBankRdBursts::6 18313 # Per bank write bursts
-system.physmem.perBankRdBursts::7 18290 # Per bank write bursts
-system.physmem.perBankRdBursts::8 18231 # Per bank write bursts
-system.physmem.perBankRdBursts::9 18232 # Per bank write bursts
-system.physmem.perBankRdBursts::10 18229 # Per bank write bursts
-system.physmem.perBankRdBursts::11 18376 # Per bank write bursts
-system.physmem.perBankRdBursts::12 18272 # Per bank write bursts
-system.physmem.perBankRdBursts::13 18137 # Per bank write bursts
-system.physmem.perBankRdBursts::14 18064 # Per bank write bursts
-system.physmem.perBankRdBursts::15 18188 # Per bank write bursts
+system.physmem.perBankRdBursts::0 18032 # Per bank write bursts
+system.physmem.perBankRdBursts::1 18362 # Per bank write bursts
+system.physmem.perBankRdBursts::2 18398 # Per bank write bursts
+system.physmem.perBankRdBursts::3 18335 # Per bank write bursts
+system.physmem.perBankRdBursts::4 18250 # Per bank write bursts
+system.physmem.perBankRdBursts::5 18255 # Per bank write bursts
+system.physmem.perBankRdBursts::6 18321 # Per bank write bursts
+system.physmem.perBankRdBursts::7 18295 # Per bank write bursts
+system.physmem.perBankRdBursts::8 18232 # Per bank write bursts
+system.physmem.perBankRdBursts::9 18236 # Per bank write bursts
+system.physmem.perBankRdBursts::10 18232 # Per bank write bursts
+system.physmem.perBankRdBursts::11 18379 # Per bank write bursts
+system.physmem.perBankRdBursts::12 18271 # Per bank write bursts
+system.physmem.perBankRdBursts::13 18134 # Per bank write bursts
+system.physmem.perBankRdBursts::14 18060 # Per bank write bursts
+system.physmem.perBankRdBursts::15 18193 # Per bank write bursts
system.physmem.perBankWrBursts::0 4125 # Per bank write bursts
system.physmem.perBankWrBursts::1 4164 # Per bank write bursts
system.physmem.perBankWrBursts::2 4223 # Per bank write bursts
@@ -74,7 +74,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe
system.physmem.perBankWrBursts::6 4262 # Per bank write bursts
system.physmem.perBankWrBursts::7 4226 # Per bank write bursts
system.physmem.perBankWrBursts::8 4233 # Per bank write bursts
-system.physmem.perBankWrBursts::9 4183 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4180 # Per bank write bursts
system.physmem.perBankWrBursts::10 4150 # Per bank write bursts
system.physmem.perBankWrBursts::11 4241 # Per bank write bursts
system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
@@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe
system.physmem.perBankWrBursts::15 4157 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 504258181000 # Total gap between requests
+system.physmem.totGap 508215452500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 292267 # Read request sizes (log2)
+system.physmem.readPktSize::6 292283 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66683 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 291455 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 291508 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 465 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -147,23 +147,23 @@ system.physmem.wrQLenPdf::13 1 # Wh
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4045 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4046 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4051 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 4050 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 4051 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
@@ -194,126 +194,123 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 103155 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 222.473443 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 144.311324 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 268.647767 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 37345 36.20% 36.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 43741 42.40% 78.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9241 8.96% 87.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 735 0.71% 88.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1396 1.35% 89.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1157 1.12% 90.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 662 0.64% 91.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 564 0.55% 91.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8314 8.06% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 103155 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 103603 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 221.521925 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 143.541969 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 268.372247 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 37864 36.55% 36.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 43808 42.28% 78.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 9097 8.78% 87.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 745 0.72% 88.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1395 1.35% 89.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1153 1.11% 90.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 627 0.61% 91.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 610 0.59% 91.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8304 8.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 103603 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 69.893801 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 34.549322 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 747.524050 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 69.361324 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 34.573478 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 739.455375 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.463077 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.442287 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.845052 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.462336 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.441628 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.843264 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 933 23.04% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 936 23.12% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads
-system.physmem.totQLat 3567632750 # Total ticks spent queuing
-system.physmem.totMemAccLat 9041826500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1459785000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12219.72 # Average queueing delay per DRAM burst
+system.physmem.totQLat 2518388500 # Total ticks spent queuing
+system.physmem.totMemAccLat 7993107250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1459925000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8625.06 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30969.72 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 37.05 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 8.46 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 37.09 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 8.46 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 27375.06 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 36.77 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 8.39 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 36.81 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 8.40 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.36 # Data bus utilization in percentage
+system.physmem.busUtil 0.35 # Data bus utilization in percentage
system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing
-system.physmem.readRowHits 203404 # Number of row buffer hits during reads
-system.physmem.writeRowHits 52048 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 69.67 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes
-system.physmem.avgGap 1404814.55 # Average gap between requests
-system.physmem.pageHitRate 71.23 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 388939320 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 212218875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1140243000 # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing
+system.physmem.readRowHits 203026 # Number of row buffer hits during reads
+system.physmem.writeRowHits 52001 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 69.53 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes
+system.physmem.avgGap 1415776.01 # Average gap between requests
+system.physmem.pageHitRate 71.10 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 390708360 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 213184125 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1140250800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 104730111945 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 210683510250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 350306824590 # Total energy per rank (pJ)
-system.physmem_0.averagePower 694.703966 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 349825620000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 16838120000 # Time in different power states
+system.physmem_0.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 103572972045 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 214071794250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 352799059260 # Total energy per rank (pJ)
+system.physmem_0.averagePower 694.201008 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 355459552750 # Time in different power states
+system.physmem_0.memoryStateTime::REF 16970200000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 137589656250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 135779058500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 390829320 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 213250125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1136538000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 215511840 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 105447215835 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 210054471750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 350393179590 # Total energy per rank (pJ)
-system.physmem_1.averagePower 694.875219 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 348773258750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 16838120000 # Time in different power states
+system.physmem_1.actEnergy 392424480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 214120500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1136545800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 33193711200 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 103467236760 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 214164544500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 352784075640 # Total energy per rank (pJ)
+system.physmem_1.averagePower 694.171524 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 355611467750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 16970200000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 135627775750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 123840342 # Number of BP lookups
-system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 102061444 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 68186680 # Number of BTB hits
+system.pwrStateResidencyTicks::UNDEFINED 508215534000 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 123851653 # Number of BP lookups
+system.cpu.branchPred.condPredicted 79872946 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 686743 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 102066131 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 68190141 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 66.809441 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 18691358 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 9446 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 14052117 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 14048642 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 3475 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 11780 # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct 66.809764 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 18697400 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 11224 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 14052177 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 14048616 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 3561 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 11655 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 237538322 # DTB read hits
-system.cpu.dtb.read_misses 198467 # DTB read misses
+system.cpu.dtb.read_hits 237539296 # DTB read hits
+system.cpu.dtb.read_misses 195211 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 237736789 # DTB read accesses
-system.cpu.dtb.write_hits 98305180 # DTB write hits
-system.cpu.dtb.write_misses 7178 # DTB write misses
+system.cpu.dtb.read_accesses 237734507 # DTB read accesses
+system.cpu.dtb.write_hits 98305020 # DTB write hits
+system.cpu.dtb.write_misses 7170 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 98312358 # DTB write accesses
-system.cpu.dtb.data_hits 335843502 # DTB hits
-system.cpu.dtb.data_misses 205645 # DTB misses
+system.cpu.dtb.write_accesses 98312190 # DTB write accesses
+system.cpu.dtb.data_hits 335844316 # DTB hits
+system.cpu.dtb.data_misses 202381 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 336049147 # DTB accesses
-system.cpu.itb.fetch_hits 285763790 # ITB hits
+system.cpu.dtb.data_accesses 336046697 # DTB accesses
+system.cpu.itb.fetch_hits 286584409 # ITB hits
system.cpu.itb.fetch_misses 119 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 285763909 # ITB accesses
+system.cpu.itb.fetch_accesses 286584528 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -327,16 +324,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 37 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 504258263000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1008516526 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 508215534000 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 1016431068 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 928789150 # Number of instructions committed
system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 316849 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 319592 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.085840 # CPI: cycles per instruction
-system.cpu.ipc 0.920946 # IPC: instructions per cycle
+system.cpu.cpi 1.094361 # CPI: cycles per instruction
+system.cpu.ipc 0.913775 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction
system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction
system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction
@@ -372,316 +369,316 @@ system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 928789150 # Class of committed instruction
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -694,118 +691,120 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1
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system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
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system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
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system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1052876 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 18463500 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 504258263000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 225622 # Transaction distribution
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system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution
-system.membus.trans_dist::CleanEvict 191176 # Transaction distribution
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system.membus.trans_dist::ReadExReq 66645 # Transaction distribution
system.membus.trans_dist::ReadExResp 66645 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 225622 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842393 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 842393 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972800 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22972800 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 225638 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842439 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 842439 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22973824 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22973824 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 550126 # Request fanout histogram
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 550156 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 550126 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 550156 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 550126 # Request fanout histogram
-system.membus.reqLayer0.occupancy 918516000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 550156 # Request fanout histogram
+system.membus.reqLayer0.occupancy 925402000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1556053500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1556718500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 0cac95bfa..0e87d435d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -68,6 +77,7 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
+default_p_state=UNDEFINED
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
@@ -104,6 +114,10 @@ numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -143,11 +157,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -155,13 +176,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -171,6 +197,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -179,8 +206,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -502,13 +534,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -518,6 +555,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -526,8 +564,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -551,13 +594,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -567,6 +615,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -575,19 +624,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -595,6 +656,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -609,7 +677,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
kvmInSE=false
@@ -641,9 +709,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -687,6 +761,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -698,7 +773,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
index 41d370561..8954fa36f 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
@@ -1,5 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index c3e095b5a..8e7b7a0be 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-ti
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 20:54:01
-gem5 started Sep 14 2015 20:54:31
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:28
+gem5 executing on e108600-lin, pid 4303
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
2000: 2845746745
1000: 2068042552
0: 290958364
-Exiting @ tick 276406029500 because target called exit()
+Exiting @ tick 174766258500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 82cf197ab..577d97331 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.174766 # Nu
sim_ticks 174766258500 # Number of ticks simulated
final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 383088 # Simulator instruction rate (inst/s)
-host_op_rate 383088 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 79477968 # Simulator tick rate (ticks/s)
-host_mem_usage 307308 # Number of bytes of host memory used
-host_seconds 2198.93 # Real time elapsed on the host
+host_inst_rate 215097 # Simulator instruction rate (inst/s)
+host_op_rate 215097 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44625570 # Simulator tick rate (ticks/s)
+host_mem_usage 260248 # Number of bytes of host memory used
+host_seconds 3916.28 # Real time elapsed on the host
sim_insts 842382029 # Number of instructions simulated
sim_ops 842382029 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -1019,6 +1019,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639552 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56339648 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 259794 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 4267648 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1046881 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001913 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.043699 # Request fanout histogram
@@ -1048,6 +1049,7 @@ system.membus.pkt_count::total 842124 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966272 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22966272 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 549958 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index bcb4e48fb..0452b264c 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=atomic
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -51,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -67,6 +77,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -114,7 +128,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
kvmInSE=false
@@ -146,9 +160,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -163,11 +183,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
index cf5d2b5cc..54e31201a 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 0dd51a4d4..3f843823b 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simpl
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 3 2015 14:54:12
-gem5 started Jul 3 2015 15:11:16
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:28
+gem5 executing on e108600-lin, pid 4304
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
index 31542f021..b6b81e33b 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.464395 # Nu
sim_ticks 464394627000 # Number of ticks simulated
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3142131 # Simulator instruction rate (inst/s)
-host_op_rate 3142131 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1571406745 # Simulator tick rate (ticks/s)
-host_mem_usage 294224 # Number of bytes of host memory used
-host_seconds 295.53 # Real time elapsed on the host
+host_inst_rate 2033284 # Simulator instruction rate (inst/s)
+host_op_rate 2033284 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1016862727 # Simulator tick rate (ticks/s)
+host_mem_usage 248468 # Number of bytes of host memory used
+host_seconds 456.69 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -142,6 +142,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram
system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index 82e107e36..b6ac9fa01 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -51,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -66,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -83,13 +97,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -99,6 +118,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -107,8 +127,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -123,13 +148,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -139,6 +169,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -147,8 +178,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -172,13 +208,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -188,6 +229,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -196,19 +238,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -216,6 +270,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -230,7 +291,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
kvmInSE=false
@@ -262,9 +323,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -279,11 +346,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
index cf5d2b5cc..54e31201a 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index 9bc789b35..6564d4aeb 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simpl
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 3 2015 14:54:12
-gem5 started Jul 3 2015 15:04:10
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:29
+gem5 executing on e108600-lin, pid 4305
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
2000: 2845746745
1000: 2068042552
0: 290958364
-Exiting @ tick 1286278511500 because target called exit()
+Exiting @ tick 1288319411500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index ba8d8610f..f13a4ce2b 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.288319 # Nu
sim_ticks 1288319411500 # Number of ticks simulated
final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1791468 # Simulator instruction rate (inst/s)
-host_op_rate 1791468 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2485477121 # Simulator tick rate (ticks/s)
-host_mem_usage 303212 # Number of bytes of host memory used
-host_seconds 518.34 # Real time elapsed on the host
+host_inst_rate 1112167 # Simulator instruction rate (inst/s)
+host_op_rate 1112167 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1543016447 # Simulator tick rate (ticks/s)
+host_mem_usage 257436 # Number of bytes of host memory used
+host_seconds 834.94 # Real time elapsed on the host
sim_insts 928587629 # Number of instructions simulated
sim_ops 928587629 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -512,6 +512,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 258847 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram
@@ -541,6 +542,7 @@ system.membus.pkt_count::total 839908 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 548519 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
index bd7f67190..4149684ba 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
@@ -14,7 +14,9 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
@@ -24,9 +26,16 @@ mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -55,6 +64,7 @@ decodeCycleInput=true
decodeInputBufferSize=3
decodeInputWidth=2
decodeToExecuteForwardDelay=1
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -99,12 +109,17 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
system=system
+threadPolicy=RoundRobin
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -120,11 +135,18 @@ choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
+useIndirect=true
[system.cpu.dcache]
type=Cache
@@ -132,13 +154,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -148,6 +175,7 @@ system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -156,8 +184,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -180,9 +213,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.dtb]
@@ -196,9 +234,14 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -591,13 +634,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -607,6 +655,7 @@ system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
+writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
@@ -615,8 +664,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -626,6 +680,7 @@ eventq_index=0
[system.cpu.isa]
type=ArmISA
+decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
@@ -673,9 +728,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.itb]
@@ -689,9 +749,14 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -701,13 +766,18 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -717,6 +787,7 @@ system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
+writeback_clean=false
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
@@ -725,19 +796,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
@@ -745,6 +828,13 @@ width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
@@ -759,7 +849,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
@@ -791,9 +881,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -837,6 +933,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -848,7 +945,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr
index 2e6ab1e7e..c1f3592f9 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr
@@ -1,3 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: fcntl64(3, 2) passed through to host
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
index d77f0dbd5..99e686564 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 15 2015 03:24:21
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:40:10
+gem5 executing on e108600-lin, pid 23109
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -650,4 +650,4 @@ info: Increasing stack size by one page.
2000: 2845746745
1000: 2068042552
0: 290958364
-Exiting @ tick 542257602500 because target called exit()
+Exiting @ tick 512588680500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index eb3e6af6a..031a11fd6 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,96 +1,96 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.489946 # Number of seconds simulated
-sim_ticks 489945697500 # Number of ticks simulated
-final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.512589 # Number of seconds simulated
+sim_ticks 512588680500 # Number of ticks simulated
+final_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 287135 # Simulator instruction rate (inst/s)
-host_op_rate 353501 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 219588415 # Simulator tick rate (ticks/s)
-host_mem_usage 322476 # Number of bytes of host memory used
-host_seconds 2231.20 # Real time elapsed on the host
+host_inst_rate 180394 # Simulator instruction rate (inst/s)
+host_op_rate 222088 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 144333179 # Simulator tick rate (ticks/s)
+host_mem_usage 275860 # Number of bytes of host memory used
+host_seconds 3551.43 # Real time elapsed on the host
sim_insts 640655085 # Number of instructions simulated
sim_ops 788730744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory
-system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory
+system.physmem.bytes_read::total 18638208 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 288654 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 291212 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 291222 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 334143 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 37705926 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 38040069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 334143 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 334143 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 8634165 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 8634165 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 8634165 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 334143 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 37705926 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 46674234 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 291212 # Number of read requests accepted
+system.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 291222 # Number of read requests accepted
system.physmem.writeReqs 66098 # Number of write requests accepted
-system.physmem.readBursts 291212 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue
system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 18637568 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 18282 # Per bank write bursts
-system.physmem.perBankRdBursts::1 18130 # Per bank write bursts
-system.physmem.perBankRdBursts::2 18217 # Per bank write bursts
+system.physmem.perBankRdBursts::0 18288 # Per bank write bursts
+system.physmem.perBankRdBursts::1 18133 # Per bank write bursts
+system.physmem.perBankRdBursts::2 18220 # Per bank write bursts
system.physmem.perBankRdBursts::3 18178 # Per bank write bursts
-system.physmem.perBankRdBursts::4 18288 # Per bank write bursts
-system.physmem.perBankRdBursts::5 18411 # Per bank write bursts
-system.physmem.perBankRdBursts::6 18177 # Per bank write bursts
-system.physmem.perBankRdBursts::7 17990 # Per bank write bursts
-system.physmem.perBankRdBursts::8 18028 # Per bank write bursts
-system.physmem.perBankRdBursts::9 18056 # Per bank write bursts
-system.physmem.perBankRdBursts::10 18107 # Per bank write bursts
-system.physmem.perBankRdBursts::11 18202 # Per bank write bursts
-system.physmem.perBankRdBursts::12 18216 # Per bank write bursts
-system.physmem.perBankRdBursts::13 18274 # Per bank write bursts
+system.physmem.perBankRdBursts::4 18281 # Per bank write bursts
+system.physmem.perBankRdBursts::5 18410 # Per bank write bursts
+system.physmem.perBankRdBursts::6 18174 # Per bank write bursts
+system.physmem.perBankRdBursts::7 17993 # Per bank write bursts
+system.physmem.perBankRdBursts::8 18029 # Per bank write bursts
+system.physmem.perBankRdBursts::9 18057 # Per bank write bursts
+system.physmem.perBankRdBursts::10 18103 # Per bank write bursts
+system.physmem.perBankRdBursts::11 18205 # Per bank write bursts
+system.physmem.perBankRdBursts::12 18223 # Per bank write bursts
+system.physmem.perBankRdBursts::13 18272 # Per bank write bursts
system.physmem.perBankRdBursts::14 18077 # Per bank write bursts
-system.physmem.perBankRdBursts::15 18258 # Per bank write bursts
+system.physmem.perBankRdBursts::15 18257 # Per bank write bursts
system.physmem.perBankWrBursts::0 4171 # Per bank write bursts
system.physmem.perBankWrBursts::1 4099 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4134 # Per bank write bursts
+system.physmem.perBankWrBursts::2 4135 # Per bank write bursts
system.physmem.perBankWrBursts::3 4146 # Per bank write bursts
-system.physmem.perBankWrBursts::4 4225 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4224 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4223 # Per bank write bursts
+system.physmem.perBankWrBursts::5 4222 # Per bank write bursts
system.physmem.perBankWrBursts::6 4173 # Per bank write bursts
system.physmem.perBankWrBursts::7 4094 # Per bank write bursts
system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
system.physmem.perBankWrBursts::10 4096 # Per bank write bursts
system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
-system.physmem.perBankWrBursts::12 4095 # Per bank write bursts
+system.physmem.perBankWrBursts::12 4098 # Per bank write bursts
system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
system.physmem.perBankWrBursts::15 4138 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 489945603000 # Total gap between requests
+system.physmem.totGap 512588586500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 291212 # Read request sizes (log2)
+system.physmem.readPktSize::6 291222 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66098 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 290509 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -145,24 +145,24 @@ system.physmem.wrQLenPdf::11 1 # Wh
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 903 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 903 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4017 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4017 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4017 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 4019 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 4017 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
@@ -194,101 +194,102 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 110179 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 207.337369 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 135.107709 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 257.005441 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 44928 40.78% 40.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 43473 39.46% 80.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9308 8.45% 88.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1919 1.74% 90.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 694 0.63% 91.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 753 0.68% 91.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 467 0.42% 92.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 575 0.52% 92.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8062 7.32% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 110179 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 48.520538 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 34.272045 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 506.481387 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.449091 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.428808 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.834669 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 3115 77.55% 77.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 902 22.45% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads
-system.physmem.totQLat 3297540750 # Total ticks spent queuing
-system.physmem.totMemAccLat 8751747000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11336.00 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads
+system.physmem.totQLat 2758807250 # Total ticks spent queuing
+system.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30086.00 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 38.00 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 8.63 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 38.04 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 8.63 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.36 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.30 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes
+system.physmem.busUtil 0.35 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.85 # Average write queue length when enqueuing
-system.physmem.readRowHits 195161 # Number of row buffer hits during reads
-system.physmem.writeRowHits 51618 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 67.09 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 78.09 # Row buffer hit rate for writes
-system.physmem.avgGap 1371205.96 # Average gap between requests
-system.physmem.pageHitRate 69.13 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 417417840 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 227757750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1136210400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 215563680 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 104435392590 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 202355359500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 340788331200 # Total energy per rank (pJ)
-system.physmem_0.averagePower 695.568361 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 335944764000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 16360240000 # Time in different power states
+system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing
+system.physmem.readRowHits 195021 # Number of row buffer hits during reads
+system.physmem.writeRowHits 51610 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes
+system.physmem.avgGap 1434536.51 # Average gap between requests
+system.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ)
+system.physmem_0.averagePower 694.106023 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states
+system.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 137638069000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 415474920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 226697625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 212608800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 104010891930 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ)
-system.physmem_1.averagePower 695.442012 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states
+system.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ)
+system.physmem_1.averagePower 694.023062 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states
+system.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 144591747 # Number of BP lookups
-system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits
+system.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 147261658 # Number of BP lookups
+system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches.
+system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -318,7 +319,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -348,7 +349,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -378,7 +379,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -409,16 +410,16 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 489945697500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 979891395 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 1025177361 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 640655085 # Number of instructions committed
system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 1.529515 # CPI: cycles per instruction
-system.cpu.ipc 0.653802 # IPC: instructions per cycle
+system.cpu.cpi 1.600202 # CPI: cycles per instruction
+system.cpu.ipc 0.624921 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction
system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
@@ -454,62 +455,62 @@ system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 788730744 # Class of committed instruction
-system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 778302 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy
+system.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.replacements 778100 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 378433272 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 378433272 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 378436756 # number of overall hits
-system.cpu.dcache.overall_hits::total 378436756 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 713841 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 713841 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 378434445 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 378434445 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 378437929 # number of overall hits
+system.cpu.dcache.overall_hits::total 378437929 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 851552 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 851552 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 851693 # number of overall misses
-system.cpu.dcache.overall_misses::total 851693 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 25188260500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 25188260500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 10109820000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 10109820000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35298080500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35298080500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35298080500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35298080500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 250333347 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 250333347 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses
+system.cpu.dcache.overall_misses::total 851045 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses)
@@ -518,274 +519,274 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 379284824 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 379284824 # number of demand (read+write) accesses
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system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 26 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 26 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2559 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2559 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222563 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222563 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2559 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 288654 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 291213 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2559 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 288654 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 291213 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4271219000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4271219000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170500500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170500500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16012410500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16012410500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170500500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20283629500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 20454130000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170500500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20283629500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 20454130000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096156 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312117 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312117 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.359962 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.359962 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency
+system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78084 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343098 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 2421182 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3294144 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55751040 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 59045184 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 258808 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 1067819 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.005072 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.071235 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78158 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 258816 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes)
+system.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 1062418 99.49% 99.49% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 5386 0.50% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 489945697500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 225121 # Transaction distribution
+system.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states
+system.membus.trans_dist::ReadResp 225131 # Transaction distribution
system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution
-system.membus.trans_dist::CleanEvict 190682 # Transaction distribution
+system.membus.trans_dist::CleanEvict 190690 # Transaction distribution
system.membus.trans_dist::ReadExReq 66091 # Transaction distribution
system.membus.trans_dist::ReadExResp 66091 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22867840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22867840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 547992 # Request fanout histogram
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 548010 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 547992 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 547992 # Request fanout histogram
-system.membus.reqLayer0.occupancy 916865000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 548010 # Request fanout histogram
+system.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1554037500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 1c8fe2c03..b1c9ef7ec 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -72,6 +77,7 @@ cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=2
decodeWidth=3
+default_p_state=UNDEFINED
dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
@@ -110,6 +116,10 @@ numPhysIntRegs=128
numROBEntries=40
numRobs=1
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
renameToDecodeDelay=1
@@ -166,12 +176,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -190,8 +205,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=32768
@@ -214,9 +234,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.dtb]
@@ -230,9 +255,14 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -508,12 +538,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=1
@@ -532,8 +567,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=32768
@@ -591,9 +631,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.itb]
@@ -607,9 +652,14 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -620,12 +670,17 @@ addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=true
prefetcher=system.cpu.l2cache.prefetcher
response_latency=12
@@ -643,6 +698,7 @@ mem_side=system.membus.slave[1]
type=StridePrefetcher
cache_snoop=false
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
degree=8
eventq_index=0
latency=1
@@ -653,6 +709,10 @@ on_inst=true
on_miss=false
on_read=true
on_write=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
queue_filter=true
queue_size=32
queue_squash=true
@@ -669,8 +729,13 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=12
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=1048576
@@ -678,10 +743,15 @@ size=1048576
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -712,7 +782,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
@@ -744,10 +814,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -791,6 +866,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -802,7 +878,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
index 2e6ab1e7e..c1f3592f9 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
@@ -1,3 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: fcntl64(3, 2) passed through to host
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 17f97ea42..d9571e5e1 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 15 2016 19:53:43
-gem5 started Mar 15 2016 20:24:49
-gem5 executing on dinar2c11, pid 10851
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:38:22
+gem5 executing on e108600-lin, pid 23079
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 77ad5d4bc..f24017e10 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.326731 # Nu
sim_ticks 326731324000 # Number of ticks simulated
final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 187465 # Simulator instruction rate (inst/s)
-host_op_rate 230795 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 95607340 # Simulator tick rate (ticks/s)
-host_mem_usage 320048 # Number of bytes of host memory used
-host_seconds 3417.43 # Real time elapsed on the host
+host_inst_rate 137546 # Simulator instruction rate (inst/s)
+host_op_rate 169337 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 70148373 # Simulator tick rate (ticks/s)
+host_mem_usage 272916 # Number of bytes of host memory used
+host_seconds 4657.72 # Real time elapsed on the host
sim_insts 640649299 # Number of instructions simulated
sim_ops 788724958 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -1200,6 +1200,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1296784 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 4257152 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram
@@ -1230,6 +1231,7 @@ system.membus.pkt_count::total 2200100 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1246861 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 844cbdea4..5997dda79 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -73,6 +79,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.dtb]
@@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.membus.slave[4]
@@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.itb]
@@ -198,9 +223,14 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.membus.slave[3]
@@ -218,7 +248,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
@@ -250,10 +280,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -268,11 +303,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
index 2de5e2759..937e051a4 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: fcntl64(3, 2) passed through to host
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 82929fd24..74eea3e5b 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-at
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 3 2015 17:56:07
-gem5 started Jul 3 2015 22:26:16
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:51:02
+gem5 executing on e108600-lin, pid 23320
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index e2d47dff8..889d833d4 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu
sim_ticks 395726778500 # Number of ticks simulated
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1817115 # Simulator instruction rate (inst/s)
-host_op_rate 2237108 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1122416416 # Simulator tick rate (ticks/s)
-host_mem_usage 311336 # Number of bytes of host memory used
-host_seconds 352.57 # Real time elapsed on the host
+host_inst_rate 860032 # Simulator instruction rate (inst/s)
+host_op_rate 1058813 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 531234389 # Simulator tick rate (ticks/s)
+host_mem_usage 264584 # Number of bytes of host memory used
+host_seconds 744.92 # Real time elapsed on the host
sim_insts 640654411 # Number of instructions simulated
sim_ops 788730070 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -237,6 +237,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index b8d9750e5..ab5a083f3 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -72,6 +78,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -114,8 +129,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.dtb]
@@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -191,8 +226,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.itb]
@@ -266,9 +311,14 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -303,8 +358,13 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
@@ -312,10 +372,15 @@ size=2097152
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -346,7 +411,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
@@ -378,10 +443,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -396,11 +466,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
index 2de5e2759..937e051a4 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: fcntl64(3, 2) passed through to host
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index 918fa3cf1..75004ec86 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-ti
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 3 2015 17:56:07
-gem5 started Jul 3 2015 18:33:02
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:46:39
+gem5 executing on e108600-lin, pid 23194
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index fc47d4b38..3a062984a 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.045756 # Nu
sim_ticks 1045756396500 # Number of ticks simulated
final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1150404 # Simulator instruction rate (inst/s)
-host_op_rate 1413341 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1881615398 # Simulator tick rate (ticks/s)
-host_mem_usage 320304 # Number of bytes of host memory used
-host_seconds 555.78 # Real time elapsed on the host
+host_inst_rate 546786 # Simulator instruction rate (inst/s)
+host_op_rate 671760 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 894330624 # Simulator tick rate (ticks/s)
+host_mem_usage 273552 # Number of bytes of host memory used
+host_seconds 1169.32 # Real time elapsed on the host
sim_insts 639366787 # Number of instructions simulated
sim_ops 785501035 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -627,6 +627,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 257772 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram
@@ -656,6 +657,7 @@ system.membus.pkt_count::total 836928 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 546561 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram