diff options
Diffstat (limited to 'tests/long/se/40.perlbmk')
18 files changed, 455 insertions, 415 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 219e926d0..9c3d68df5 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,22 +31,18 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -56,7 +53,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -69,23 +65,15 @@ forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -97,7 +85,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -116,6 +103,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -125,6 +113,24 @@ workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -132,21 +138,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -426,21 +427,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -463,21 +459,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -504,7 +495,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 319c358f1..b07774dbb 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:02:14 -gem5 started Oct 30 2012 12:07:24 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 13:57:22 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index cc561b02c..8443dfdcb 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.626365 # Nu sim_ticks 626365181000 # Number of ticks simulated final_tick 626365181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141169 # Simulator instruction rate (inst/s) -host_op_rate 141169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48503245 # Simulator tick rate (ticks/s) -host_mem_usage 240100 # Number of bytes of host memory used -host_seconds 12913.88 # Real time elapsed on the host +host_inst_rate 114572 # Simulator instruction rate (inst/s) +host_op_rate 114572 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39364843 # Simulator tick rate (ticks/s) +host_mem_usage 295992 # Number of bytes of host memory used +host_seconds 15911.79 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory @@ -192,6 +192,15 @@ system.physmem.writeRowHits 48790 # Nu system.physmem.readRowHitRate 55.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate 72.92 # Row buffer hit rate for writes system.physmem.avgGap 1153499.31 # Average gap between requests +system.cpu.branchPred.lookups 388924238 # Number of BP lookups +system.cpu.branchPred.condPredicted 255857711 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25855826 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 319270007 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258448229 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 80.949736 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57345473 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6929 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -228,14 +237,6 @@ system.cpu.workload.num_syscalls 39 # Nu system.cpu.numCycles 1252730363 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 388924238 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 255857711 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 25855826 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 319270007 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 258448229 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57345473 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6929 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 410516643 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 3276851782 # Number of instructions fetch has processed system.cpu.fetch.Branches 388924238 # Number of branches that fetch encountered diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index aa91216e8..98e511e60 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -29,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts itb tracer workload +children=dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -42,17 +44,18 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu.tracer width=1 @@ -67,6 +70,9 @@ size=64 [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -82,7 +88,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -99,14 +105,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 073913775..76e77727d 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:31:15 -gem5 executing on zizzer +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 14:44:11 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 8a7012f1d..7637d378a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.004711 # Nu sim_ticks 1004710587000 # Number of ticks simulated final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3539563 # Simulator instruction rate (inst/s) -host_op_rate 3539563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1770163280 # Simulator tick rate (ticks/s) -host_mem_usage 211940 # Number of bytes of host memory used -host_seconds 567.58 # Real time elapsed on the host +host_inst_rate 2509174 # Simulator instruction rate (inst/s) +host_op_rate 2509174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1254857691 # Simulator tick rate (ticks/s) +host_mem_usage 273968 # Number of bytes of host memory used +host_seconds 800.66 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 77bc7da26..be88a9856 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -10,10 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -29,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -41,15 +43,16 @@ dtb=system.cpu.dtb function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -61,21 +64,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=262144 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -90,21 +90,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=2 is_top_level=true -latency=1000 max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=2 size=131072 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -113,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -120,23 +120,20 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 +clock=500 forward_snoops=true -hash_delay=1 +hit_latency=20 is_top_level=false -latency=10000 max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null +response_latency=20 size=2097152 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -145,10 +142,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -158,12 +155,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -181,13 +178,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1000 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index af38cd121..c7b42c8e2 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:50:30 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 13:29:25 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1387,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2813572242000 because target called exit() +Exiting @ tick 2769739533000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index c58eb2bea..f8a5c16cd 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.769740 # Nu sim_ticks 2769739533000 # Number of ticks simulated final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1761560 # Simulator instruction rate (inst/s) -host_op_rate 1761559 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2428616742 # Simulator tick rate (ticks/s) -host_mem_usage 226024 # Number of bytes of host memory used -host_seconds 1140.46 # Real time elapsed on the host +host_inst_rate 964642 # Simulator instruction rate (inst/s) +host_op_rate 964642 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1329927483 # Simulator tick rate (ticks/s) +host_mem_usage 281524 # Number of bytes of host memory used +host_seconds 2082.62 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory @@ -167,106 +167,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use -system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits -system.cpu.dcache.overall_hits::total 720334778 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses -system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks -system.cpu.dcache.writebacks::total 96129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 442570 # number of replacements system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks. @@ -405,5 +305,105 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1526048 # number of replacements +system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use +system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits +system.cpu.dcache.overall_hits::total 720334778 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses +system.cpu.dcache.overall_misses::total 1530144 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks +system.cpu.dcache.writebacks::total 96129 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 735e1f1d5..89ba10791 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -31,22 +31,18 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -69,23 +65,15 @@ forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu.interrupts isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -97,7 +85,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -126,6 +113,24 @@ workload=system.cpu.workload dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +predType=tournament + [system.cpu.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -522,7 +527,7 @@ egid=100 env= errout=cerr euid=100 -executable=/gem5/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 638fa449a..63003fae2 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 4 2013 21:17:24 -gem5 started Jan 5 2013 00:23:14 -gem5 executing on u200540 +gem5 compiled Jan 23 2013 19:43:25 +gem5 started Jan 23 2013 20:27:21 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1385,4 +1387,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 624867585500 because target called exit() +Exiting @ tick 625047295000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 3f51a9ebc..96fe6f71c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.625047 # Nu sim_ticks 625047295000 # Number of ticks simulated final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94484 # Simulator instruction rate (inst/s) -host_op_rate 128674 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42659692 # Simulator tick rate (ticks/s) -host_mem_usage 264788 # Number of bytes of host memory used -host_seconds 14651.94 # Real time elapsed on the host +host_inst_rate 72768 # Simulator instruction rate (inst/s) +host_op_rate 99100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32855066 # Simulator tick rate (ticks/s) +host_mem_usage 309740 # Number of bytes of host memory used +host_seconds 19024.38 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory @@ -192,6 +192,15 @@ system.physmem.writeRowHits 48036 # Nu system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes system.physmem.avgGap 1155201.56 # Average gap between requests +system.cpu.branchPred.lookups 438808047 # Number of BP lookups +system.cpu.branchPred.condPredicted 349805436 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30625316 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 249957064 # Number of BTB lookups +system.cpu.branchPred.BTBHits 227370417 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 90.963789 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52357585 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806128 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -238,14 +247,6 @@ system.cpu.workload.num_syscalls 1411 # Nu system.cpu.numCycles 1250094591 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 438808047 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 349805436 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 30625316 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 249957064 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 227370417 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 52357585 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2806128 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 6368ff37d..821ff54be 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=AtomicSimpleCPU -children=dtb interrupts itb tracer workload +children=dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -43,6 +44,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -53,6 +55,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu.tracer width=1 @@ -68,7 +71,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -76,6 +79,23 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -84,7 +104,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -100,7 +120,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -124,7 +144,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 303ba43b2..542af2be2 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:53:48 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 19:43:25 +gem5 started Jan 23 2013 20:32:44 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 72c04a2c0..72ddef8e3 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu sim_ticks 945613126000 # Number of ticks simulated final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1877363 # Simulator instruction rate (inst/s) -host_op_rate 2556708 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1282347761 # Simulator tick rate (ticks/s) -host_mem_usage 223904 # Number of bytes of host memory used -host_seconds 737.41 # Real time elapsed on the host +host_inst_rate 1270703 # Simulator instruction rate (inst/s) +host_op_rate 1730522 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 867964073 # Simulator tick rate (ticks/s) +host_mem_usage 286692 # Number of bytes of host memory used +host_seconds 1089.46 # Real time elapsed on the host sim_insts 1384381606 # Number of instructions simulated sim_ops 1885336358 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 2fc919fb9..28c3943fd 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -42,6 +43,7 @@ dtb=system.cpu.dtb function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -50,6 +52,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -61,23 +64,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=262144 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -101,23 +99,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=131072 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -134,7 +144,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 +response_latency=20 size=2097152 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -169,10 +174,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -187,7 +192,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index eb0b38c6c..32f62cb45 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 12:04:21 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 19:43:25 +gem5 started Jan 23 2013 20:51:04 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1385,4 +1387,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2369931974000 because target called exit() +Exiting @ tick 2326118592000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index ac5d108eb..dc10302b1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu sim_ticks 2326118592000 # Number of ticks simulated final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 541548 # Simulator instruction rate (inst/s) -host_op_rate 734649 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 911769830 # Simulator tick rate (ticks/s) -host_mem_usage 240408 # Number of bytes of host memory used -host_seconds 2551.21 # Real time elapsed on the host +host_inst_rate 664911 # Simulator instruction rate (inst/s) +host_op_rate 901999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1119467924 # Simulator tick rate (ticks/s) +host_mem_usage 296296 # Number of bytes of host memory used +host_seconds 2077.88 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory @@ -177,114 +177,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use -system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits -system.cpu.dcache.overall_hits::total 895737438 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses -system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks -system.cpu.dcache.writebacks::total 96257 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 441378 # number of replacements system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks. @@ -423,5 +315,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 1529557 # number of replacements +system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use +system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits +system.cpu.dcache.overall_hits::total 895737438 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses +system.cpu.dcache.overall_misses::total 1533653 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks +system.cpu.dcache.writebacks::total 96257 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |