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-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt1327
-rw-r--r--tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt62
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt1377
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt62
4 files changed, 1405 insertions, 1423 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index c480587dc..fb55fbe0e 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,64 +1,64 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.631301 # Number of seconds simulated
-sim_ticks 631300530000 # Number of ticks simulated
-final_tick 631300530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.631883 # Number of seconds simulated
+sim_ticks 631883288500 # Number of ticks simulated
+final_tick 631883288500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153163 # Simulator instruction rate (inst/s)
-host_op_rate 153163 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53038574 # Simulator tick rate (ticks/s)
-host_mem_usage 237176 # Number of bytes of host memory used
-host_seconds 11902.67 # Real time elapsed on the host
+host_inst_rate 129491 # Simulator instruction rate (inst/s)
+host_op_rate 129491 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44882876 # Simulator tick rate (ticks/s)
+host_mem_usage 237188 # Number of bytes of host memory used
+host_seconds 14078.49 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30295296 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30472576 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30295168 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30471232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 176064 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 176064 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 473364 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 476134 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2751 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 473362 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 476113 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 280817 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 47988707 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48269524 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 280817 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 280817 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6783001 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6783001 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6783001 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 280817 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 47988707 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55052525 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 476134 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 278634 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 47944246 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 48222880 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 278634 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 278634 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6776745 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6776745 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6776745 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 278634 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 47944246 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54999625 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 476114 # Total number of read requests seen
system.physmem.writeReqs 66908 # Total number of write requests seen
-system.physmem.cpureqs 543042 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30472576 # Total number of bytes read from memory
+system.physmem.cpureqs 543022 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30471232 # Total number of bytes read from memory
system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30472576 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30471232 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29446 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29796 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29856 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29790 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29772 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29865 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29863 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29774 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29887 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 29447 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29799 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29852 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 29789 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 29768 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 29869 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 29858 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 29771 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 29890 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 29849 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29919 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29794 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29585 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29511 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29633 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 29915 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29796 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29583 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 29509 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 29637 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4125 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 4164 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4223 # Track writes on a per bank basis
@@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4096 # Tr
system.physmem.perBankWrReqs::15 4157 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 631300447500 # Total gap between requests
+system.physmem.totGap 631883258500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 476134 # Categorize read packet sizes
+system.physmem.readPktSize::6 476114 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
@@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 66908 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 408382 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66876 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 628 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 408378 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66892 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 126 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -156,40 +156,40 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 166615 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 208.530564 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 137.079554 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 536.352711 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65 52781 31.68% 31.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129 42583 25.56% 57.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193 39981 24.00% 81.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257 25354 15.22% 96.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321 274 0.16% 96.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385 129 0.08% 96.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449 97 0.06% 96.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513 83 0.05% 96.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577 81 0.05% 96.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641 95 0.06% 96.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705 108 0.06% 96.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769 114 0.07% 97.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833 86 0.05% 97.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 166584 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 208.562071 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 137.103843 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 536.299000 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 52740 31.66% 31.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 42613 25.58% 57.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 39946 23.98% 81.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 25368 15.23% 96.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 277 0.17% 96.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 122 0.07% 96.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 95 0.06% 96.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 87 0.05% 96.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 83 0.05% 96.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 94 0.06% 96.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 111 0.07% 96.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 115 0.07% 97.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 83 0.05% 97.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 90 0.05% 97.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961 79 0.05% 97.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025 79 0.05% 97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1088-1089 75 0.05% 97.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 77 0.05% 97.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 81 0.05% 97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 76 0.05% 97.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217 77 0.05% 97.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281 76 0.05% 97.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 74 0.04% 97.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 77 0.05% 97.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409 81 0.05% 97.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 82 0.05% 97.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 3443 2.07% 99.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 36 0.02% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 1 0.00% 99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1664-1665 1 0.00% 99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1728-1729 2 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 2 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 1 0.00% 99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 2 0.00% 99.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 3 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.61% # Bytes accessed per row activation
@@ -197,11 +197,12 @@ system.physmem.bytesPerActivate::2432-2433 2 0.00% 99.61% #
system.physmem.bytesPerActivate::2560-2561 3 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3200-3201 2 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::3264-3265 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 2 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.62% # Bytes accessed per row activation
@@ -209,7 +210,7 @@ system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.62% #
system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.63% # Bytes accessed per row activation
@@ -233,73 +234,73 @@ system.physmem.bytesPerActivate::8000-8001 4 0.00% 99.65% #
system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129 1 0.00% 99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 586 0.35% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 166615 # Bytes accessed per row activation
-system.physmem.totQLat 1512536000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 14445141000 # Sum of mem lat for all requests
-system.physmem.totBusLat 2380195000 # Total cycles spent in databus access
-system.physmem.totBankLat 10552410000 # Total cycles spent in bank access
-system.physmem.avgQLat 3177.34 # Average queueing delay per request
-system.physmem.avgBankLat 22167.11 # Average bank access latency per request
+system.physmem.bytesPerActivate::total 166584 # Bytes accessed per row activation
+system.physmem.totQLat 1351239750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 14292404750 # Sum of mem lat for all requests
+system.physmem.totBusLat 2380120000 # Total cycles spent in databus access
+system.physmem.totBankLat 10561045000 # Total cycles spent in bank access
+system.physmem.avgQLat 2838.60 # Average queueing delay per request
+system.physmem.avgBankLat 22185.95 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30344.45 # Average memory access latency
-system.physmem.avgRdBW 48.27 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 30024.55 # Average memory access latency
+system.physmem.avgRdBW 48.22 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 48.27 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 48.22 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.78 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 10.99 # Average write queue length over time
+system.physmem.avgWrQLen 11.01 # Average write queue length over time
system.physmem.readRowHits 326147 # Number of row buffer hits during reads
-system.physmem.writeRowHits 50184 # Number of row buffer hits during writes
+system.physmem.writeRowHits 50200 # Number of row buffer hits during writes
system.physmem.readRowHitRate 68.51 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.00 # Row buffer hit rate for writes
-system.physmem.avgGap 1162526.01 # Average gap between requests
-system.membus.throughput 55052525 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 409284 # Transaction distribution
-system.membus.trans_dist::ReadResp 409284 # Transaction distribution
+system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes
+system.physmem.avgGap 1163642.10 # Average gap between requests
+system.membus.throughput 54999625 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 409258 # Transaction distribution
+system.membus.trans_dist::ReadResp 409257 # Transaction distribution
system.membus.trans_dist::Writeback 66908 # Transaction distribution
-system.membus.trans_dist::ReadExReq 66850 # Transaction distribution
-system.membus.trans_dist::ReadExResp 66850 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 1019176 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 1019176 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34754688 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 34754688 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 34754688 # Total data (bytes)
+system.membus.trans_dist::ReadExReq 66856 # Transaction distribution
+system.membus.trans_dist::ReadExResp 66856 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 1019135 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1019135 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34753344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 34753344 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34753344 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1238262500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1232718500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4532735250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4527448500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
-system.cpu.branchPred.lookups 388673605 # Number of BP lookups
-system.cpu.branchPred.condPredicted 255878326 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 25733265 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 278525299 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 258256723 # Number of BTB hits
+system.cpu.branchPred.lookups 388901077 # Number of BP lookups
+system.cpu.branchPred.condPredicted 255997466 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 25785874 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 315302493 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 258353491 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.722896 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 57195432 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 6738 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.938296 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 57247417 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6895 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 521844087 # DTB read hits
-system.cpu.dtb.read_misses 593644 # DTB read misses
+system.cpu.dtb.read_hits 522159380 # DTB read hits
+system.cpu.dtb.read_misses 590851 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 522437731 # DTB read accesses
-system.cpu.dtb.write_hits 282954606 # DTB write hits
-system.cpu.dtb.write_misses 50165 # DTB write misses
+system.cpu.dtb.read_accesses 522750231 # DTB read accesses
+system.cpu.dtb.write_hits 283002528 # DTB write hits
+system.cpu.dtb.write_misses 50162 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 283004771 # DTB write accesses
-system.cpu.dtb.data_hits 804798693 # DTB hits
-system.cpu.dtb.data_misses 643809 # DTB misses
+system.cpu.dtb.write_accesses 283052690 # DTB write accesses
+system.cpu.dtb.data_hits 805161908 # DTB hits
+system.cpu.dtb.data_misses 641013 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 805442502 # DTB accesses
-system.cpu.itb.fetch_hits 394528514 # ITB hits
-system.cpu.itb.fetch_misses 534 # ITB misses
+system.cpu.dtb.data_accesses 805802921 # DTB accesses
+system.cpu.itb.fetch_hits 394748041 # ITB hits
+system.cpu.itb.fetch_misses 630 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 394529048 # ITB accesses
+system.cpu.itb.fetch_accesses 394748671 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -313,238 +314,238 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
-system.cpu.numCycles 1262601061 # number of cpu cycles simulated
+system.cpu.numCycles 1263766578 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 409498007 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3272810217 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 388673605 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 315452155 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 629699645 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 157846800 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 75851008 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 7336 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 394528514 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11392908 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1246680714 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.625219 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.138755 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 409917284 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3274493634 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 388901077 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 315600908 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 630100236 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 157853545 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 75868728 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 6965 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 394748041 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11243258 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1247472116 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.624903 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.139302 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 616981069 49.49% 49.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 57198279 4.59% 54.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 43039078 3.45% 57.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 71977388 5.77% 63.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 129322230 10.37% 73.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46258105 3.71% 77.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 41218514 3.31% 80.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 7777319 0.62% 81.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 232908732 18.68% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 617371880 49.49% 49.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 57447684 4.61% 54.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 43286408 3.47% 57.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 71838123 5.76% 63.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 129156368 10.35% 73.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46178870 3.70% 77.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 41219816 3.30% 80.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7663689 0.61% 81.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 233309278 18.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1246680714 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.307836 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.592117 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 437789893 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 62140482 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 606005534 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9132317 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 131612488 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 31510475 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12424 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3192799837 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 46361 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 131612488 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 467284900 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 27231873 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 27253 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 585294370 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 35229830 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3093290625 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 1247472116 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.307732 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.591059 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 438201536 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 62209215 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 606414230 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9080438 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 131566697 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 31709739 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12402 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3193700667 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 46294 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 131566697 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 467502237 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 27351671 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 28189 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 585846018 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 35177304 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3094945067 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 14758 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 28928557 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2053350484 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3577730264 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3457415406 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 120314858 # Number of floating rename lookups
+system.cpu.rename.IQFullEvents 15191 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 28875434 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2054257390 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3579193509 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3458491340 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 120702169 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 668381414 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4231 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 109772702 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 743605283 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 351355021 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 69106055 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8779755 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2622263880 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2159577480 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 17944946 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 799158217 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 726204094 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1246680714 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.732262 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.802997 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 669288320 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4234 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 98 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 109722880 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 743716097 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 351305913 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 69009362 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8819654 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2623113984 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 93 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2159995607 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 17916537 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 800006156 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 726205656 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 54 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1247472116 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.731498 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.803359 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 450451444 36.13% 36.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 196386892 15.75% 51.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 251435205 20.17% 72.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 120817476 9.69% 81.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 104827933 8.41% 90.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 79080340 6.34% 96.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 24383702 1.96% 98.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 17529670 1.41% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1768052 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 450995748 36.15% 36.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 196797874 15.78% 51.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 251286832 20.14% 72.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 120757727 9.68% 81.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 104717605 8.39% 90.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 79196335 6.35% 96.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 24309118 1.95% 98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 17642931 1.41% 99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1767946 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1246680714 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1247472116 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1146168 3.12% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 25530327 69.57% 72.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 10022787 27.31% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1146304 3.11% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.11% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 25641829 69.66% 72.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 10023004 27.23% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1233812197 57.13% 57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 27851163 1.29% 58.42% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.80% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 589396274 27.29% 86.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 293038648 13.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1234267096 57.14% 57.14% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 17095 0.00% 57.14% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 27851364 1.29% 58.43% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 7204649 0.33% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.15% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 589311123 27.28% 86.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 293086828 13.57% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2159577480 # Type of FU issued
-system.cpu.iq.rate 1.710420 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 36699282 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016994 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5469378913 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3334207188 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1989129090 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 151100989 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 87288283 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 73609749 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2118824418 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 77449592 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62141857 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2159995607 # Type of FU issued
+system.cpu.iq.rate 1.709173 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 36811137 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.017042 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5471089482 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3335131409 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1989836434 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 151101522 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 88062076 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 73609987 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2119354134 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 77449858 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 62153092 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 232535257 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 18630 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 75784 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 140560125 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 232646071 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 31940 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 75814 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 140511017 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4408 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 2802 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4421 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 2886 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 131612488 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 13139012 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 539946 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2986122932 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 725503 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 743605283 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 351355021 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 196101 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1503 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 75784 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 25727396 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 27151 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 25754547 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2065136857 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 522437892 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 94440623 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 131566697 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 13318869 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 540046 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2986589244 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 731786 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 743716097 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 351305913 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 93 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 134266 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1522 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 75814 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 25780444 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 27789 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 25808233 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2065907774 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 522750367 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 94087833 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 363858964 # number of nop insts executed
-system.cpu.iew.exec_refs 805443124 # number of memory reference insts executed
-system.cpu.iew.exec_branches 277347977 # Number of branches executed
-system.cpu.iew.exec_stores 283005232 # Number of stores executed
-system.cpu.iew.exec_rate 1.635621 # Inst execution rate
-system.cpu.iew.wb_sent 2065019944 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2062738839 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1180752690 # num instructions producing a value
-system.cpu.iew.wb_consumers 1753366082 # num instructions consuming a value
+system.cpu.iew.exec_nop 363475167 # number of nop insts executed
+system.cpu.iew.exec_refs 805803501 # number of memory reference insts executed
+system.cpu.iew.exec_branches 277598296 # Number of branches executed
+system.cpu.iew.exec_stores 283053134 # Number of stores executed
+system.cpu.iew.exec_rate 1.634723 # Inst execution rate
+system.cpu.iew.wb_sent 2065776472 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2063446421 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1180901001 # num instructions producing a value
+system.cpu.iew.wb_consumers 1753223374 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.633722 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.673421 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.632775 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.673560 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 960178624 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 960640976 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 25721232 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1115068226 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.801672 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.508434 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 25773841 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1115905419 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.800321 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.507651 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 496151769 44.50% 44.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 228465229 20.49% 64.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 119927421 10.76% 75.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 58951874 5.29% 81.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 50411669 4.52% 85.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 24161138 2.17% 87.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19007626 1.70% 89.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 16618211 1.49% 90.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 101373289 9.09% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 496848865 44.52% 44.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 228666687 20.49% 65.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 119877587 10.74% 75.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 58838951 5.27% 81.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 50501288 4.53% 85.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 24162159 2.17% 87.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 19119877 1.71% 89.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 16606359 1.49% 90.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 101283646 9.08% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1115068226 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1115905419 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -555,212 +556,212 @@ system.cpu.commit.branches 266706457 # Nu
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 101373289 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 101283646 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3977224755 # The number of ROB reads
-system.cpu.rob.rob_writes 6069947076 # The number of ROB writes
-system.cpu.timesIdled 341189 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 15920347 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3978613943 # The number of ROB reads
+system.cpu.rob.rob_writes 6070825883 # The number of ROB writes
+system.cpu.timesIdled 341889 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 16294462 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
-system.cpu.cpi 0.692579 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.692579 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.443879 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.443879 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2627113034 # number of integer regfile reads
-system.cpu.int_regfile_writes 1496009216 # number of integer regfile writes
-system.cpu.fp_regfile_reads 78810922 # number of floating regfile reads
-system.cpu.fp_regfile_writes 52660839 # number of floating regfile writes
+system.cpu.cpi 0.693218 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.693218 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.442548 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.442548 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2627733458 # number of integer regfile reads
+system.cpu.int_regfile_writes 1496469824 # number of integer regfile writes
+system.cpu.fp_regfile_reads 78811377 # number of floating regfile reads
+system.cpu.fp_regfile_writes 52661114 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 166051525 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1470336 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1470335 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 71638 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 71638 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20109 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159809 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 3179918 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 643456 # Cumulative packet size per connected master and slave (bytes)
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-system.cpu.toL2Bus.tot_pkt_size 104828416 # Cumulative packet size per connected master and slave (bytes)
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+system.cpu.dcache.demand_miss_latency::total 121327034104 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 121327034104 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 121327034104 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 459999146 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 459999146 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 670490085 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 670490085 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 670490085 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 670490085 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004189 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004189 # miss rate for ReadReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 25 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 25 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 670794042 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 670794042 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 670794042 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 670794042 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004186 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004186 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.083333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.083333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.004456 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.004456 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004456 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.004456 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39298.296685 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 39298.296685 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42472.937393 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 42472.937393 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66750 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40426.646276 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40426.646276 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 17832 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 107 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 375 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.004454 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.004454 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.004454 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.004454 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39634.374224 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39634.374224 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42377.238101 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42377.238101 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40609.248714 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40609.248714 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40609.248714 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 18768 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.552000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.086455 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks
-system.cpu.dcache.writebacks::total 95971 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465494 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 465494 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990257 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 990257 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1455751 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1455751 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1455751 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1455751 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460280 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1460280 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1531918 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1531918 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1531918 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1531918 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41822016500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 41822016500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5130364000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130364000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46952380500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 46952380500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46952380500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 46952380500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003177 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003177 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 95986 # number of writebacks
+system.cpu.dcache.writebacks::total 95986 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465536 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 465536 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990239 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 990239 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1455775 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1455775 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1455775 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1455775 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460250 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1460250 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71645 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 71645 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1531895 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1531895 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1531895 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1531895 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41766827000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 41766827000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5159100250 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5159100250 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46925927250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 46925927250 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46925927250 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 46925927250 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003174 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003174 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002285 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002285 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28639.724231 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28639.724231 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71615.120467 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71615.120467 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002284 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002284 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002284 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28602.518062 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28602.518062 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72009.215577 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72009.215577 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30632.600309 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30632.600309 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
index 217f3cee7..3b39f56f2 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
@@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 5539479066 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.replacements 9046 # number of replacements
-system.cpu.icache.tagsinuse 1478.418050 # Cycle average of tags in use
-system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.721884 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 9046 # number of replacements
+system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
@@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 442570 # number of replacements
-system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 475302 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.292151 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.998134 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements 442570 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits
@@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1526048 # number of replacements
-system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use
-system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 1526048 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 54c03f73f..68bfe2c31 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,64 +1,64 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.629145 # Number of seconds simulated
-sim_ticks 629144850500 # Number of ticks simulated
-final_tick 629144850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.640648 # Number of seconds simulated
+sim_ticks 640648369500 # Number of ticks simulated
+final_tick 640648369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 104232 # Simulator instruction rate (inst/s)
-host_op_rate 141949 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47369420 # Simulator tick rate (ticks/s)
-host_mem_usage 254336 # Number of bytes of host memory used
-host_seconds 13281.67 # Real time elapsed on the host
+host_inst_rate 99606 # Simulator instruction rate (inst/s)
+host_op_rate 135651 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46095119 # Simulator tick rate (ticks/s)
+host_mem_usage 254320 # Number of bytes of host memory used
+host_seconds 13898.40 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 155072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30241984 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30397056 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 155072 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 155072 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 155648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30243840 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30399488 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 155648 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 155648 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2423 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 472531 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 474954 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2432 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 472560 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 474992 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 246481 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48068396 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48314877 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 246481 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 246481 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6723844 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6723844 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6723844 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 246481 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48068396 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55038721 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 474954 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 242954 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 47208174 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 47451128 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 242954 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 242954 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6603111 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6603111 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6603111 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 242954 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 47208174 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54054239 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 474992 # Total number of read requests seen
system.physmem.writeReqs 66098 # Total number of write requests seen
-system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30397056 # Total number of bytes read from memory
+system.physmem.cpureqs 545451 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30399488 # Total number of bytes read from memory
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30397056 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30399488 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 163 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4296 # Reqs where no action is needed
+system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4361 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29676 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29740 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29705 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29805 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29834 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29631 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29439 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29482 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29490 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 29536 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29644 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29703 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29807 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29631 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29795 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29675 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29741 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 29701 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29814 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 29838 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 29642 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 29441 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 29488 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 29488 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 29538 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 29646 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29708 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29815 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 29628 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 29804 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis
@@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4096 # Tr
system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 629144781500 # Total gap between requests
+system.physmem.totGap 640648293500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 474954 # Categorize read packet sizes
+system.physmem.readPktSize::6 474992 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
@@ -92,12 +92,12 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 66098 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 407688 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66635 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 380 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 407729 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66641 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 384 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 67 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
@@ -156,49 +156,47 @@ system.physmem.wrQLenPdf::28 0 # Wh
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 173211 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 199.837655 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 132.549683 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 508.405937 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::64-65 59600 34.41% 34.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-129 42691 24.65% 59.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::192-193 39909 23.04% 82.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-257 25367 14.65% 96.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::320-321 276 0.16% 96.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-385 104 0.06% 96.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::448-449 98 0.06% 97.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-513 91 0.05% 97.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::576-577 88 0.05% 97.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-641 83 0.05% 97.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::704-705 78 0.05% 97.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-769 81 0.05% 97.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::832-833 73 0.04% 97.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-897 74 0.04% 97.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::960-961 79 0.05% 97.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1025 80 0.05% 97.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 173268 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 199.789644 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 132.514067 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 508.333416 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 59669 34.44% 34.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 42666 24.62% 59.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 39942 23.05% 82.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 25325 14.62% 96.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 291 0.17% 96.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 110 0.06% 96.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 103 0.06% 97.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 89 0.05% 97.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 94 0.05% 97.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 79 0.05% 97.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 78 0.05% 97.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 80 0.05% 97.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 70 0.04% 97.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 76 0.04% 97.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 80 0.05% 97.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 77 0.04% 97.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1216-1217 80 0.05% 97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1280-1281 73 0.04% 97.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1408-1409 73 0.04% 97.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1472-1473 3309 1.91% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1536-1537 4 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1600-1601 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 81 0.05% 97.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 72 0.04% 97.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 72 0.04% 97.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 3310 1.91% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 3 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 3 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2240-2241 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 3 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2432-2433 3 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 4 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2624-2625 1 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2688-2689 2 0.00% 99.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::2752-2753 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 3 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation
@@ -209,62 +207,62 @@ system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% #
system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 173211 # Bytes accessed per row activation
-system.physmem.totQLat 2060605250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 15116660250 # Sum of mem lat for all requests
-system.physmem.totBusLat 2373955000 # Total cycles spent in databus access
-system.physmem.totBankLat 10682100000 # Total cycles spent in bank access
-system.physmem.avgQLat 4340.03 # Average queueing delay per request
-system.physmem.avgBankLat 22498.53 # Average bank access latency per request
+system.physmem.bytesPerActivate::total 173268 # Bytes accessed per row activation
+system.physmem.totQLat 1888421000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 14966831000 # Sum of mem lat for all requests
+system.physmem.totBusLat 2374200000 # Total cycles spent in databus access
+system.physmem.totBankLat 10704210000 # Total cycles spent in bank access
+system.physmem.avgQLat 3976.96 # Average queueing delay per request
+system.physmem.avgBankLat 22542.77 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31838.56 # Average memory access latency
-system.physmem.avgRdBW 48.31 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 48.31 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.72 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31519.74 # Average memory access latency
+system.physmem.avgRdBW 47.45 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 6.60 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 47.45 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.60 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.43 # Data bus utilization in percentage
+system.physmem.busUtil 0.42 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 17.41 # Average write queue length over time
-system.physmem.readRowHits 318020 # Number of row buffer hits during reads
-system.physmem.writeRowHits 49639 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 66.98 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.10 # Row buffer hit rate for writes
-system.physmem.avgGap 1162817.59 # Average gap between requests
-system.membus.throughput 55038619 # Throughput (bytes/s)
-system.membus.trans_dist::ReadReq 408879 # Transaction distribution
-system.membus.trans_dist::ReadResp 408878 # Transaction distribution
+system.physmem.avgWrQLen 17.45 # Average write queue length over time
+system.physmem.readRowHits 318007 # Number of row buffer hits during reads
+system.physmem.writeRowHits 49644 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 66.97 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes
+system.physmem.avgGap 1183995.81 # Average gap between requests
+system.membus.throughput 54054139 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 408917 # Transaction distribution
+system.membus.trans_dist::ReadResp 408916 # Transaction distribution
system.membus.trans_dist::Writeback 66098 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4361 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4361 # Transaction distribution
system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side 1024597 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count 1024597 # Packet count per connected master and slave (bytes)
-system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34627264 # Cumulative packet size per connected master and slave (bytes)
-system.membus.tot_pkt_size 34627264 # Cumulative packet size per connected master and slave (bytes)
-system.membus.data_through_bus 34627264 # Total data (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side 1024803 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1024803 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34629696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 34629696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34629696 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
-system.membus.reqLayer0.occupancy 1206768500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 1215067500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4481136954 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 4480877139 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
-system.cpu.branchPred.lookups 441633744 # Number of BP lookups
-system.cpu.branchPred.condPredicted 353245820 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 30626910 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 253291175 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 229518524 # Number of BTB hits
+system.cpu.branchPred.lookups 451070712 # Number of BP lookups
+system.cpu.branchPred.condPredicted 361199071 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 31575662 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 266989928 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 238695746 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 90.614497 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 52707299 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2806413 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 89.402528 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 53258278 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2806364 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -308,238 +306,239 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1258289702 # number of cpu cycles simulated
+system.cpu.numCycles 1281296740 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 355059035 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2281679265 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 441633744 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 282225823 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 601500993 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 156584245 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 133257591 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 11034 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 167 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 335655020 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11657170 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1215734936 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.578441 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.176596 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 365834433 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2312845521 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 451070712 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 291954024 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 613483563 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 162414515 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 128244265 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 613 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 11411 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 346004157 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 12181247 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1238361342 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.567207 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.166964 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 614278728 50.53% 50.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 43031217 3.54% 54.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 96058050 7.90% 61.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55653458 4.58% 66.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 73683625 6.06% 72.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 43835223 3.61% 76.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31015132 2.55% 78.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 32844314 2.70% 81.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 225335189 18.53% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 624922537 50.46% 50.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 43984122 3.55% 54.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 100783073 8.14% 62.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 58015364 4.68% 66.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 73986941 5.97% 72.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 44117238 3.56% 76.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31886448 2.57% 78.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 33644071 2.72% 81.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 227021548 18.33% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1215734936 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.350979 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.813318 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 405408112 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105525155 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 562197495 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16710779 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 125893395 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 45735070 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12243 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3027450313 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 24999 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 125893395 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 441381944 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37599884 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 466637 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 540742593 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 69650483 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2947282074 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 91 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4813438 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 54199144 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2931640163 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14025190740 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13455020985 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 570169755 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1238361342 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.352042 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.805082 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 416001710 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 101876756 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 574960463 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 14748325 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 130774088 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46845433 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 13115 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3066767432 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 27354 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 130774088 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 450873553 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37362667 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 459915 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 552824643 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 66066476 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2984722482 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 106 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4345913 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 52259250 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 16 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2968696668 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14208671481 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13600947598 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 607723883 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 938500073 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 22029 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 19516 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 179002715 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 971623898 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 487434291 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36825257 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 41359268 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2792194659 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 28248 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2432796766 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13281338 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 894337134 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2316040320 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 6864 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1215734936 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.001091 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 975556578 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 21287 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 18729 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 172024073 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 975055963 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 496398991 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 36275443 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 40590257 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2826416078 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 28152 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2457324643 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 15915709 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 928556403 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2380098621 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 6768 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1238361342 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.984336 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.868331 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 379743334 31.24% 31.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 183587297 15.10% 46.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 204204940 16.80% 63.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 169567149 13.95% 77.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 132821991 10.93% 88.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 92473374 7.61% 95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 37933065 3.12% 98.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12385370 1.02% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 3018416 0.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 394006079 31.82% 31.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 183256590 14.80% 46.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 205523874 16.60% 63.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 174394872 14.08% 77.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 137878376 11.13% 88.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 90899666 7.34% 95.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 36275985 2.93% 98.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12839255 1.04% 99.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 3286645 0.27% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1215734936 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1238361342 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 717080 0.82% 0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 24380 0.03% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 55165781 62.93% 63.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 31749638 36.22% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 691696 0.78% 0.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 24382 0.03% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 55024342 62.24% 63.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 32666949 36.95% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1103940359 45.38% 45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11224025 0.46% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5502268 0.23% 46.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23395329 0.96% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 838660213 34.47% 81.84% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 441822804 18.16% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1118619814 45.52% 45.52% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11223087 0.46% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.98% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.03% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 6876474 0.28% 46.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5501669 0.22% 46.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.54% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23389012 0.95% 47.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.49% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 843037947 34.31% 81.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 447301347 18.20% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2432796766 # Type of FU issued
-system.cpu.iq.rate 1.933415 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 87656879 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.036031 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6059775624 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3603986878 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2248220965 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 122491061 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 82640163 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56428970 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2457145320 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63308325 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 84445856 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2457324643 # Type of FU issued
+system.cpu.iq.rate 1.917842 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 88407369 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.035977 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6133604202 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3666175191 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2269813505 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 123729504 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 88892403 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 56421926 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2481804628 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 63927384 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 85672552 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 340236717 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 10068 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1429873 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 210438994 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 343668782 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 27729 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1429255 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 219403694 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 345 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 304 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 125893395 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 15644195 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1562618 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2792235356 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1396921 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 971623898 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 487434291 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 18262 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1558827 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2523 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1429873 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 32450935 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1518228 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 33969163 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2357455643 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 792848546 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 75341123 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 130774088 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 15649984 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1558990 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2826456693 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 641968 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 975055963 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 496398991 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 18166 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1553675 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 1429255 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 33789507 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 2118647 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 35908154 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2378923796 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 796860173 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 78400847 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12449 # number of nop insts executed
-system.cpu.iew.exec_refs 1216025241 # number of memory reference insts executed
-system.cpu.iew.exec_branches 319732380 # Number of branches executed
-system.cpu.iew.exec_stores 423176695 # Number of stores executed
-system.cpu.iew.exec_rate 1.873540 # Inst execution rate
-system.cpu.iew.wb_sent 2330413186 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2304649935 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1347862197 # num instructions producing a value
-system.cpu.iew.wb_consumers 2523443205 # num instructions consuming a value
+system.cpu.iew.exec_nop 12463 # number of nop insts executed
+system.cpu.iew.exec_refs 1223764024 # number of memory reference insts executed
+system.cpu.iew.exec_branches 324680497 # Number of branches executed
+system.cpu.iew.exec_stores 426903851 # Number of stores executed
+system.cpu.iew.exec_rate 1.856653 # Inst execution rate
+system.cpu.iew.wb_sent 2351973532 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2326235431 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1354756756 # num instructions producing a value
+system.cpu.iew.wb_consumers 2530303455 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.831573 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.534136 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.815532 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535413 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 906899118 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 941120455 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 30614902 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1089841541 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.729918 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.397219 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 31562826 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1107587254 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.702201 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.378361 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 449517068 41.25% 41.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 288638854 26.48% 67.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 95107207 8.73% 76.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 70204085 6.44% 82.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 46459856 4.26% 87.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22200640 2.04% 89.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15848625 1.45% 90.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10985187 1.01% 91.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 90880019 8.34% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 463154673 41.82% 41.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 291887882 26.35% 68.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 96478924 8.71% 76.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 70059146 6.33% 83.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 46846853 4.23% 87.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22330225 2.02% 89.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 15798039 1.43% 90.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11765677 1.06% 91.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 89265835 8.06% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1089841541 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1107587254 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -550,222 +549,222 @@ system.cpu.commit.branches 298259106 # Nu
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 90880019 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 89265835 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3791178653 # The number of ROB reads
-system.cpu.rob.rob_writes 5710375191 # The number of ROB writes
-system.cpu.timesIdled 353026 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 42554766 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3844759887 # The number of ROB reads
+system.cpu.rob.rob_writes 5783698867 # The number of ROB writes
+system.cpu.timesIdled 353367 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 42935398 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
-system.cpu.cpi 0.908925 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.908925 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.100200 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.100200 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11755248902 # number of integer regfile reads
-system.cpu.int_regfile_writes 2218571084 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68795959 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49541079 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1363718123 # number of misc regfile reads
+system.cpu.cpi 0.925545 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.925545 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.080445 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.080445 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 11851555490 # number of integer regfile reads
+system.cpu.int_regfile_writes 2239006966 # number of integer regfile writes
+system.cpu.fp_regfile_reads 68795802 # number of floating regfile reads
+system.cpu.fp_regfile_writes 49533000 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1371543913 # number of misc regfile reads
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
-system.cpu.toL2Bus.throughput 169026080 # Throughput (bytes/s)
-system.cpu.toL2Bus.trans_dist::ReadReq 1492742 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1492741 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 96335 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 72516 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 72516 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52382 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178768 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count 3231150 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1538688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104528128 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.tot_pkt_size 106066816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.data_through_bus 106066816 # Total data (bytes)
-system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes)
-system.cpu.toL2Bus.reqLayer0.occupancy 929281000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.throughput 165989839 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1492758 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1492757 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 96304 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 4364 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 4364 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 72519 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 72519 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52387 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178835 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 3231222 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1536768 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104525120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 106061888 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 106061888 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 279232 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 929276999 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 42510998 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 43029998 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2307535978 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 2407943085 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.cpu.icache.replacements 22361 # number of replacements
-system.cpu.icache.tagsinuse 1639.588858 # Cycle average of tags in use
-system.cpu.icache.total_refs 335620121 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 24041 # Sample count of references to valid blocks.
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@@ -777,192 +776,192 @@ system.cpu.l2cache.cache_copies 0 # nu
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+system.cpu.dcache.WriteReq_misses::total 842462 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2795420 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2795420 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2795420 # number of overall misses
-system.cpu.dcache.overall_misses::total 2795420 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 79048557500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 79048557500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 56325650469 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 56325650469 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 203500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 135374207969 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 135374207969 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 135374207969 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 135374207969 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 695943005 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 695943005 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 2796350 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2796350 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2796350 # number of overall misses
+system.cpu.dcache.overall_misses::total 2796350 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 79173694807 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 79173694807 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 56852278531 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 56852278531 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204750 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 204750 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 136025973338 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 136025973338 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 136025973338 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 136025973338 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 698744373 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 698744373 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 972878683 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 972878683 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 972878683 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 972878683 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002806 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002806 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 975680051 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 975680051 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 975680051 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 975680051 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002796 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002796 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002873 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002873 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002873 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002873 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40475.306796 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40475.306796 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66862.275949 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 66862.275949 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67833.333333 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 48427.144389 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 48427.144389 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 2558 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 879 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 58 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40521.101930 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40521.101930 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67483.493061 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 67483.493061 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 68250 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 68250 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 48644.115843 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 48644.115843 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 48644.115843 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2745 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 62 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.103448 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 9.876404 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.274194 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 9.584270 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96335 # number of writebacks
-system.cpu.dcache.writebacks::total 96335 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488604 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 488604 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765599 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 765599 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 96304 # number of writebacks
+system.cpu.dcache.writebacks::total 96304 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 489504 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 489504 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765580 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 765580 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1254203 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1254203 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1254203 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1254203 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464403 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1464403 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541217 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541217 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541217 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541217 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42813858522 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 42813858522 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4818359000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4818359000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47632217522 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 47632217522 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47632217522 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 47632217522 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002104 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29236.390886 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29236.390886 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62727.614758 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62727.614758 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 1255084 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1255084 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1255084 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1255084 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464384 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1464384 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76882 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76882 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541266 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541266 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541266 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541266 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42754567776 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 42754567776 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4832230139 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4832230139 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47586797915 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 47586797915 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47586797915 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 47586797915 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002096 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002096 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001580 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001580 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001580 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29196.281697 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29196.281697 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62852.555071 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62852.555071 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30875.136359 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30875.136359 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index 6e9e09ef8..b119e8929 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu
system.cpu.num_busy_cycles 4652237184 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.icache.replacements 18364 # number of replacements
-system.cpu.icache.tagsinuse 1392.317060 # Cycle average of tags in use
-system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.679842 # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements 18364 # number of replacements
+system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits
@@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 441378 # number of replacements
-system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 474121 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.325596 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.997708 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements 441378 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits
@@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1529557 # number of replacements
-system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use
-system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 1529557 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits