diff options
Diffstat (limited to 'tests/long/se/40.perlbmk')
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 1272 | ||||
| -rw-r--r-- | tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1372 |
2 files changed, 1475 insertions, 1169 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 76fb7aa81..bd567cfd0 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,217 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.644314 # Number of seconds simulated -sim_ticks 644314104000 # Number of ticks simulated -final_tick 644314104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.652381 # Number of seconds simulated +sim_ticks 652381344000 # Number of ticks simulated +final_tick 652381344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164548 # Simulator instruction rate (inst/s) -host_op_rate 164548 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58155841 # Simulator tick rate (ticks/s) -host_mem_usage 223896 # Number of bytes of host memory used -host_seconds 11079.10 # Real time elapsed on the host +host_inst_rate 170851 # Simulator instruction rate (inst/s) +host_op_rate 170851 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 61139648 # Simulator tick rate (ticks/s) +host_mem_usage 240236 # Number of bytes of host memory used +host_seconds 10670.35 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 190848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94463936 # Number of bytes read from this memory -system.physmem.bytes_read::total 94654784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 190848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 190848 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 191616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94459904 # Number of bytes read from this memory +system.physmem.bytes_read::total 94651520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 191616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 191616 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2982 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1475999 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1478981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1475936 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1478930 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 296203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146611622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146907826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 296203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 296203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6645007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6645007 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6645007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 296203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146611622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 153552833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 293718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 144792467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 145086184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 293718 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 293718 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6562836 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6562836 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6562836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 293718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 144792467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 151649021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1478931 # Total number of read requests seen +system.physmem.writeReqs 66898 # Total number of write requests seen +system.physmem.cpureqs 1545829 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 94651520 # Total number of bytes read from memory +system.physmem.bytesWritten 4281472 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 94651520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4281472 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3904 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 91678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 92672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 91873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 92907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 92232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 92052 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 92519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 92192 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 92430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 91951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 91930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 92149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 91869 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 92596 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 91765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 92212 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4346 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4296 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4199 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4202 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4131 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4109 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4102 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4213 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 652381327000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 1478931 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 66898 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 1404621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2986 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 2901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 5885504293 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 50112950293 # Sum of mem lat for all requests +system.physmem.totBusLat 5900108000 # Total cycles spent in databus access +system.physmem.totBankLat 38327338000 # Total cycles spent in bank access +system.physmem.avgQLat 3990.10 # Average queueing delay per request +system.physmem.avgBankLat 25984.16 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 33974.26 # Average memory access latency +system.physmem.avgRdBW 145.09 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.56 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 145.09 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.56 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.95 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.08 # Average read queue length over time +system.physmem.avgWrQLen 10.99 # Average write queue length over time +system.physmem.readRowHits 824972 # Number of row buffer hits during reads +system.physmem.writeRowHits 37277 # Number of row buffer hits during writes +system.physmem.readRowHitRate 55.93 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 55.72 # Row buffer hit rate for writes +system.physmem.avgGap 422026.84 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 526091283 # DTB read hits -system.cpu.dtb.read_misses 609189 # DTB read misses +system.cpu.dtb.read_hits 526096858 # DTB read hits +system.cpu.dtb.read_misses 613073 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 526700472 # DTB read accesses -system.cpu.dtb.write_hits 292251681 # DTB write hits -system.cpu.dtb.write_misses 54656 # DTB write misses +system.cpu.dtb.read_accesses 526709931 # DTB read accesses +system.cpu.dtb.write_hits 292394059 # DTB write hits +system.cpu.dtb.write_misses 53899 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 292306337 # DTB write accesses -system.cpu.dtb.data_hits 818342964 # DTB hits -system.cpu.dtb.data_misses 663845 # DTB misses +system.cpu.dtb.write_accesses 292447958 # DTB write accesses +system.cpu.dtb.data_hits 818490917 # DTB hits +system.cpu.dtb.data_misses 666972 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 819006809 # DTB accesses -system.cpu.itb.fetch_hits 402493704 # ITB hits -system.cpu.itb.fetch_misses 819 # ITB misses +system.cpu.dtb.data_accesses 819157889 # DTB accesses +system.cpu.itb.fetch_hits 401734157 # ITB hits +system.cpu.itb.fetch_misses 1039 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 402494523 # ITB accesses +system.cpu.itb.fetch_accesses 401735196 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,245 +225,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1288628209 # number of cpu cycles simulated +system.cpu.numCycles 1304762689 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 393523603 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 256622136 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27591372 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 324682531 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 262034039 # Number of BTB hits +system.cpu.BPredUnit.lookups 395100113 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 257879210 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27591675 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 325941438 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 262133239 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57682078 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 6792 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421081938 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3322079900 # Number of instructions fetch has processed -system.cpu.fetch.Branches 393523603 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 319716117 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638226273 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162822813 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 94445154 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8938 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 402493704 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9540813 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1288505558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.578243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.138227 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 57700479 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 6698 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 421496575 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3322405570 # Number of instructions fetch has processed +system.cpu.fetch.Branches 395100113 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 319833718 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638480554 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 162110923 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 102053744 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9801 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 401734157 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8363180 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1296072068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.563442 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.138795 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 650279285 50.47% 50.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 59669001 4.63% 55.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43760756 3.40% 58.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72624833 5.64% 64.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127388332 9.89% 74.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46848563 3.64% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41619525 3.23% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7020509 0.54% 81.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 239294754 18.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 657591514 50.74% 50.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60871982 4.70% 55.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 44636510 3.44% 58.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71794407 5.54% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 126302912 9.75% 74.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45673565 3.52% 77.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41643401 3.21% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7024748 0.54% 81.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 240533029 18.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1288505558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305382 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.577997 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 453351036 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 77522549 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 613342023 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9559025 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134730925 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33522574 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12306 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3228150524 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46600 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134730925 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 483601779 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 32079469 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25997 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 591314469 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46752919 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3136805366 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 365 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7001 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40828800 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2086363185 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3649389993 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3531980340 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117409653 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1296072068 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.302814 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.546368 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 453815792 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 84580008 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 615145766 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8511561 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 134018941 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 34684248 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12433 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3231024090 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46816 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 134018941 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 483692761 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37815213 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 26926 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 592981976 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47536251 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3144588480 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1177 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 7026 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 41373292 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2089769744 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3655475569 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3535468644 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120006925 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 701394115 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4228 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 134 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 140886298 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 736269341 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 360318998 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68834783 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9382400 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2642228655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2193185137 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17944949 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 819070745 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 708820503 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 83 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1288505558 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.702115 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.805670 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 704800674 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4226 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 127 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 142344309 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 735042012 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 359395829 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 68166545 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9320020 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2645223582 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 121 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2193823681 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17946245 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 822107127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 708225593 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 82 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1296072068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.692671 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.804037 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 470226956 36.49% 36.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 215277039 16.71% 53.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 253569254 19.68% 72.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121312750 9.41% 82.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 106354397 8.25% 90.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 77759673 6.03% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21099202 1.64% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17230121 1.34% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5676166 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 475835975 36.71% 36.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 218666129 16.87% 53.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251350949 19.39% 72.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 122837911 9.48% 82.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 105713044 8.16% 90.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 77520434 5.98% 96.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21238629 1.64% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17216175 1.33% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5692822 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1288505558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1296072068 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1175249 3.24% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24027488 66.23% 69.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11077412 30.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1168166 3.19% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25201102 68.89% 72.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10214807 27.92% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1255595425 57.25% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16675 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29225002 1.33% 58.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204653 0.33% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589172005 26.86% 86.15% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 303713925 13.85% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1258217376 57.35% 57.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16681 0.00% 57.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29224824 1.33% 58.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254695 0.38% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 587046185 26.76% 86.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 303856512 13.85% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2193185137 # Type of FU issued -system.cpu.iq.rate 1.701953 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36280149 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016542 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5574611120 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3377500690 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2021426713 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 154489810 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 83871907 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75374894 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2150389693 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 79072841 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67211668 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2193823681 # Type of FU issued +system.cpu.iq.rate 1.681397 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36584075 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016676 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5583657415 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3378809764 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2023568909 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 154592335 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 88593840 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75404787 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2151259351 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 79145653 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62323542 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 225199315 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24267 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76315 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 149524102 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 223971986 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12645 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76017 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 148600933 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4398 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 43 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4436 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 69 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134730925 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4001327 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 199767 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3000725705 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2706866 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 736269341 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 360318998 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 195059 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4865 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76315 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27584399 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31784 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27616183 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2101081456 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 526700571 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 92103681 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 134018941 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 11876310 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 832949 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3002252422 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2341492 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 735042012 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 359395829 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 121 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 187560 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4854 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76017 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27589712 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31349 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27621061 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2103239947 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526710042 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 90583734 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 358496928 # number of nop insts executed -system.cpu.iew.exec_refs 819007361 # number of memory reference insts executed -system.cpu.iew.exec_branches 281208089 # Number of branches executed -system.cpu.iew.exec_stores 292306790 # Number of stores executed -system.cpu.iew.exec_rate 1.630479 # Inst execution rate -system.cpu.iew.wb_sent 2099578580 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2096801607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1184710151 # num instructions producing a value -system.cpu.iew.wb_consumers 1754117094 # num instructions consuming a value +system.cpu.iew.exec_nop 357028719 # number of nop insts executed +system.cpu.iew.exec_refs 819158443 # number of memory reference insts executed +system.cpu.iew.exec_branches 282386049 # Number of branches executed +system.cpu.iew.exec_stores 292448401 # Number of stores executed +system.cpu.iew.exec_rate 1.611971 # Inst execution rate +system.cpu.iew.wb_sent 2101749466 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2098973696 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1185216175 # num instructions producing a value +system.cpu.iew.wb_consumers 1752698092 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.627158 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675388 # average fanout of values written-back +system.cpu.iew.wb_rate 1.608702 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.676224 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 975019383 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 976452699 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27579200 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1153774633 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.741231 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.495587 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27579406 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1162053127 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.728826 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.486115 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 537356152 46.57% 46.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227667410 19.73% 66.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119239977 10.33% 76.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56780365 4.92% 81.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50766064 4.40% 85.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24581833 2.13% 88.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18432159 1.60% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15672614 1.36% 91.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103278059 8.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 542846661 46.71% 46.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 230306455 19.82% 66.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119679848 10.30% 76.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 57176464 4.92% 81.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50189917 4.32% 86.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25112757 2.16% 88.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 18284566 1.57% 89.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15890460 1.37% 91.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102565999 8.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1153774633 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1162053127 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +474,70 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103278059 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102565999 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4028867151 # The number of ROB reads -system.cpu.rob.rob_writes 6102747283 # The number of ROB writes -system.cpu.timesIdled 3543 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 122651 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4039291021 # The number of ROB reads +system.cpu.rob.rob_writes 6104902002 # The number of ROB writes +system.cpu.timesIdled 33492 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8690621 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.706855 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.706855 # CPI: Total CPI of All Threads -system.cpu.ipc 1.414716 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.414716 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2678227479 # number of integer regfile reads -system.cpu.int_regfile_writes 1517398403 # number of integer regfile writes -system.cpu.fp_regfile_reads 81948895 # number of floating regfile reads -system.cpu.fp_regfile_writes 54035615 # number of floating regfile writes +system.cpu.cpi 0.715706 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.715706 # CPI: Total CPI of All Threads +system.cpu.ipc 1.397222 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.397222 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2679345799 # number of integer regfile reads +system.cpu.int_regfile_writes 1518234716 # number of integer regfile writes +system.cpu.fp_regfile_reads 81979255 # number of floating regfile reads +system.cpu.fp_regfile_writes 54034777 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8420 # number of replacements -system.cpu.icache.tagsinuse 1668.242053 # Cycle average of tags in use -system.cpu.icache.total_refs 402482315 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10141 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39688.621931 # Average number of references to valid blocks. +system.cpu.icache.replacements 8417 # number of replacements +system.cpu.icache.tagsinuse 1668.126238 # Cycle average of tags in use +system.cpu.icache.total_refs 401722811 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10139 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39621.541671 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1668.242053 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.814571 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.814571 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 402482315 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 402482315 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 402482315 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 402482315 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 402482315 # number of overall hits -system.cpu.icache.overall_hits::total 402482315 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11389 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11389 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11389 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11389 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11389 # number of overall misses -system.cpu.icache.overall_misses::total 11389 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 178670000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 178670000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 178670000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 178670000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 178670000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 178670000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 402493704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 402493704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 402493704 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 402493704 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 402493704 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 402493704 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1668.126238 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.814515 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.814515 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 401722811 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 401722811 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 401722811 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 401722811 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 401722811 # number of overall hits +system.cpu.icache.overall_hits::total 401722811 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11346 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11346 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11346 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11346 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11346 # number of overall misses +system.cpu.icache.overall_misses::total 11346 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 190399000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 190399000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 190399000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 190399000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 190399000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 190399000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 401734157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 401734157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 401734157 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 401734157 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 401734157 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 401734157 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000028 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000028 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000028 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000028 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15687.944508 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15687.944508 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15687.944508 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15687.944508 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15687.944508 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15687.944508 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16781.156355 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16781.156355 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16781.156355 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16781.156355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16781.156355 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16781.156355 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,296 +546,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1247 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1247 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1247 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1247 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1247 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1247 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10142 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13295.315582 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13295.315582 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13295.315582 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13295.315582 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1528011 # number of replacements -system.cpu.dcache.tagsinuse 4095.070038 # Cycle average of tags in use -system.cpu.dcache.total_refs 666681777 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1532107 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 435.140481 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 262302000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.070038 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999773 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999773 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 456946751 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 456946751 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209734975 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209734975 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 51 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 51 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 666681726 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 666681726 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 666681726 # number of overall hits -system.cpu.dcache.overall_hits::total 666681726 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1928385 # 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Cycle average of tags in use +system.cpu.dcache.total_refs 671579546 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531737 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 438.443118 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 234314000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.118942 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999785 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999785 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 461844402 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 461844402 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209735100 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209735100 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 44 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 674563676 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 674563676 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 674563676 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 674563676 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004149 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004149 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005028 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005028 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.019231 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.019231 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004462 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33793.696324 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 43 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.004424 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004424 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004424 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004424 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40249.574148 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40249.574148 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36006.671083 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36006.671083 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38742.754607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38742.754607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38742.754607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38742.754607 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 411 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 57 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.904762 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 43 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 57 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 109393 # number of writebacks -system.cpu.dcache.writebacks::total 109393 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467889 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467889 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 988310 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 988310 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # 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number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50211071000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50211071000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3191098000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3191098000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 53402169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 53402169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 53402169000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 53402169000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003183 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003183 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 59756974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 59756974500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 59756974500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 47014623500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96989500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46917634000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 47014623500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964838 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960212 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933614 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933614 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963379 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.958977 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294025 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963379 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.958977 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32524.983233 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31227.504751 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31230.244653 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43580.260855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43580.260855 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32524.983233 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31787.036441 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31788.524329 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32524.983233 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31787.036441 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31788.524329 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2995 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409081 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1412076 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2995 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1475936 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1478931 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2995 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1475936 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1478931 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106523142 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 49028505930 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 49135029072 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3470186582 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3470186582 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106523142 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 52498692512 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 52605215654 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106523142 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52498692512 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 52605215654 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965039 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933612 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963570 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.959176 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.295365 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963570 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.959176 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.992321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34794.668248 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34796.306340 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51906.163817 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51906.163817 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35566.992321 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35569.762179 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35569.756570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35566.992321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35569.762179 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35569.756570 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index c008b73ab..1e57970d1 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,197 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.659244 # Number of seconds simulated -sim_ticks 659244465000 # Number of ticks simulated -final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.659992 # Number of seconds simulated +sim_ticks 659991928000 # Number of ticks simulated +final_tick 659991928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153116 # Simulator instruction rate (inst/s) -host_op_rate 208523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72914339 # Simulator tick rate (ticks/s) -host_mem_usage 237584 # Number of bytes of host memory used -host_seconds 9041.36 # Real time elapsed on the host -sim_insts 1384375635 # Number of instructions simulated -sim_ops 1885330387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94515200 # Number of bytes read from this memory -system.physmem.bytes_read::total 94714816 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 199616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 199616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3119 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476800 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479919 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 302795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 143368970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 143671765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302795 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6416946 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6416946 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6416946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 143368970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 150088711 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 102750 # Simulator instruction rate (inst/s) +host_op_rate 139931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48985343 # Simulator tick rate (ticks/s) +host_mem_usage 254632 # Number of bytes of host memory used +host_seconds 13473.25 # Real time elapsed on the host +sim_insts 1384374560 # Number of instructions simulated +sim_ops 1885329312 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 198528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94517696 # Number of bytes read from this memory +system.physmem.bytes_read::total 94716224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 198528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 198528 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory +system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3102 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476839 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479941 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 300804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 143210382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 143511185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 300804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 300804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6409581 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6409581 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6409581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 300804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 143210382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 149920767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1479941 # Total number of read requests seen +system.physmem.writeReqs 66098 # Total number of write requests seen +system.physmem.cpureqs 1550203 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 94716224 # Total number of bytes read from memory +system.physmem.bytesWritten 4230272 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 94716224 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 4222 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4164 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 92954 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 91941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 92050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 91689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 92209 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 92061 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 92149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 92666 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 91875 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 92213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 92439 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 92957 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 92247 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 91863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 92572 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 91834 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 659991863500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 1479941 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 66098 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4164 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 1408404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 2842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 5597502027 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 50332290027 # Sum of mem lat for all requests +system.physmem.totBusLat 5902876000 # Total cycles spent in databus access +system.physmem.totBankLat 38831912000 # Total cycles spent in bank access +system.physmem.avgQLat 3793.07 # Average queueing delay per request +system.physmem.avgBankLat 26313.89 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 34106.96 # Average memory access latency +system.physmem.avgRdBW 143.51 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.41 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 143.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.41 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 0.94 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.08 # Average read queue length over time +system.physmem.avgWrQLen 14.18 # Average write queue length over time +system.physmem.readRowHits 809039 # Number of row buffer hits during reads +system.physmem.writeRowHits 36662 # Number of row buffer hits during writes +system.physmem.readRowHitRate 54.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 55.47 # Row buffer hit rate for writes +system.physmem.avgGap 426892.12 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +235,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1318488931 # number of cpu cycles simulated +system.cpu.numCycles 1319983857 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 461326092 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 364071075 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 34100101 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 298580925 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 245422956 # Number of BTB hits +system.cpu.BPredUnit.lookups 454350981 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 358310478 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 33373061 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 312072233 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 240275028 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 54976315 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2806988 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 381926912 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2354617227 # Number of instructions fetch has processed -system.cpu.fetch.Branches 461326092 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 300399271 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 631966560 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 174781634 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 133381872 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1547 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 26290 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 359560180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11891763 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1287933807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.529860 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.156146 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 53876645 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2808673 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 374001286 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2331861224 # Number of instructions fetch has processed +system.cpu.fetch.Branches 454350981 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 294151673 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 622796021 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 170528608 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 135818762 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 24217 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 352463772 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11980006 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1269746213 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.542801 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.164977 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 656012764 50.94% 50.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47127862 3.66% 54.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105351348 8.18% 62.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 60429666 4.69% 67.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 75027065 5.83% 73.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 45419751 3.53% 76.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 32157937 2.50% 79.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 32241388 2.50% 81.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 234166026 18.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 646995456 50.95% 50.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 44687712 3.52% 54.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 102379693 8.06% 62.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 59922071 4.72% 67.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 74129472 5.84% 73.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45582835 3.59% 76.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31361893 2.47% 79.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30601811 2.41% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 234085270 18.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1287933807 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.349890 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.785845 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433461682 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105761116 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 591844441 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16248270 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 140618298 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 52072887 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12605 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3150187282 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 23939 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 140618298 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 469309271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39277977 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 483250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 570159229 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 68085782 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3069262221 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 155 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4380621 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54394099 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1922 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3038163295 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14611934802 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13977694721 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 634240081 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993148162 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1045015133 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27322 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23140 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 179514029 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 982659180 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 514844433 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35819898 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36120464 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2890303698 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 33130 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2506565055 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17234382 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 992532581 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2476785189 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10737 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1287933807 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.946191 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.883330 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1269746213 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.344209 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.766583 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 425403268 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107718588 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 581478902 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18055452 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 137090003 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 51078179 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 15137 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3127640414 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28961 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 137090003 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 461511464 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39177126 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 530700 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 561763722 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 69673198 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3042064401 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 391 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4490697 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56029467 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 2572 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2999547883 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14489457877 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13880825981 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 608631896 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993146442 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1006401441 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 29463 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25504 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 180658895 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 975543094 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 514319343 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 34765547 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 38827815 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2864053634 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 32821 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2484775177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 12535683 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 966091505 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2435627475 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 10643 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1269746213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.956907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.886378 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 425460645 33.03% 33.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 193710960 15.04% 48.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 207680071 16.13% 64.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 174651445 13.56% 77.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 137124890 10.65% 88.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 94993427 7.38% 95.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 35869114 2.79% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12687801 0.99% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5755454 0.45% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 414113290 32.61% 32.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 194811826 15.34% 47.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 206120235 16.23% 64.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 171548762 13.51% 77.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 130841431 10.30% 88.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 97116191 7.65% 95.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37554058 2.96% 98.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12317792 0.97% 99.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5322628 0.42% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1287933807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1269746213 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 692420 0.75% 0.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24115 0.03% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56113360 61.04% 61.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 35101326 38.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 947301 1.02% 1.02% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24145 0.03% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56191268 60.42% 61.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 35841535 38.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1147061112 45.76% 45.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11228333 0.45% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876483 0.27% 46.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5512765 0.22% 46.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 16 0.00% 46.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23755231 0.95% 47.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 846734490 33.78% 81.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 464021335 18.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1133457764 45.62% 45.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11237396 0.45% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876496 0.28% 46.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5506177 0.22% 46.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23536328 0.95% 47.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838863420 33.76% 81.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 463922306 18.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2506565055 # Type of FU issued -system.cpu.iq.rate 1.901089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 91931221 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036676 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6281789129 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3788847878 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2312502456 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 128440391 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 94088071 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 58648289 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2531838073 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 66658203 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 81288215 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2484775177 # Type of FU issued +system.cpu.iq.rate 1.882428 # Inst issue rate +system.cpu.iq.fu_busy_cnt 93004249 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.037430 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6215984950 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3740236476 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2293829225 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 128851549 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 90009348 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59026271 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2510712861 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 67066565 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 78532237 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 351270990 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24451 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1405210 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 237848127 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 344155119 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5694 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1300004 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 237323252 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 140618298 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16819525 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1547443 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2890351322 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8718298 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 982659180 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 514844433 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22537 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1538114 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1067 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1405210 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 36121914 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 2298987 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 38420901 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2424696979 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 800223206 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 81868076 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 137090003 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17084434 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1439762 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2864100864 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 11154453 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 975543094 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 514319343 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22441 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1430096 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1153 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1300004 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 35278606 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1697024 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 36975630 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2406030122 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 793312488 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 78745055 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14494 # number of nop insts executed -system.cpu.iew.exec_refs 1240121255 # number of memory reference insts executed -system.cpu.iew.exec_branches 334180264 # Number of branches executed -system.cpu.iew.exec_stores 439898049 # Number of stores executed -system.cpu.iew.exec_rate 1.838997 # Inst execution rate -system.cpu.iew.wb_sent 2396725321 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2371150745 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1368219909 # num instructions producing a value -system.cpu.iew.wb_consumers 2564381587 # num instructions consuming a value +system.cpu.iew.exec_nop 14409 # number of nop insts executed +system.cpu.iew.exec_refs 1235149676 # number of memory reference insts executed +system.cpu.iew.exec_branches 329779468 # Number of branches executed +system.cpu.iew.exec_stores 441837188 # Number of stores executed +system.cpu.iew.exec_rate 1.822772 # Inst execution rate +system.cpu.iew.wb_sent 2378266547 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2352855496 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1358943525 # num instructions producing a value +system.cpu.iew.wb_consumers 2560958188 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.798385 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533548 # average fanout of values written-back +system.cpu.iew.wb_rate 1.782488 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.530639 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005010225 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 22393 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 34087773 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1147315511 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.643263 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.351044 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 978761117 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 22178 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 33359188 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1132656212 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.664530 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.366367 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 497187613 43.33% 43.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 300050723 26.15% 69.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 93458742 8.15% 77.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 72384885 6.31% 83.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 45393865 3.96% 87.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22818775 1.99% 89.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15801520 1.38% 91.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11015018 0.96% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 89204370 7.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 484847147 42.81% 42.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 300235204 26.51% 69.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 89818902 7.93% 77.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 73190759 6.46% 83.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 44951546 3.97% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23093029 2.04% 89.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15848859 1.40% 91.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9835568 0.87% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90835198 8.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1147315511 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384386651 # Number of instructions committed -system.cpu.commit.committedOps 1885341403 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1132656212 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384385576 # Number of instructions committed +system.cpu.commit.committedOps 1885340328 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908384496 # Number of memory references committed -system.cpu.commit.loads 631388190 # Number of loads committed +system.cpu.commit.refs 908384066 # Number of memory references committed +system.cpu.commit.loads 631387975 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299635404 # Number of branches committed +system.cpu.commit.branches 299635189 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653702903 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653702043 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 89204370 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90835198 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3948444424 # The number of ROB reads -system.cpu.rob.rob_writes 5921335810 # The number of ROB writes -system.cpu.timesIdled 1335770 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30555124 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384375635 # Number of Instructions Simulated -system.cpu.committedOps 1885330387 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384375635 # Number of Instructions Simulated -system.cpu.cpi 0.952407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.952407 # CPI: Total CPI of All Threads -system.cpu.ipc 1.049971 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049971 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12040516185 # number of integer regfile reads -system.cpu.int_regfile_writes 2278755627 # number of integer regfile writes -system.cpu.fp_regfile_reads 70304928 # number of floating regfile reads -system.cpu.fp_regfile_writes 50983418 # number of floating regfile writes -system.cpu.misc_regfile_reads 3755360027 # number of misc regfile reads -system.cpu.misc_regfile_writes 13774920 # number of misc regfile writes -system.cpu.icache.replacements 22971 # number of replacements -system.cpu.icache.tagsinuse 1659.651348 # Cycle average of tags in use -system.cpu.icache.total_refs 359526375 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24666 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14575.787521 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3905904114 # The number of ROB reads +system.cpu.rob.rob_writes 5865307964 # The number of ROB writes +system.cpu.timesIdled 1232544 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50237644 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384374560 # Number of Instructions Simulated +system.cpu.committedOps 1885329312 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384374560 # Number of Instructions Simulated +system.cpu.cpi 0.953488 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.953488 # CPI: Total CPI of All Threads +system.cpu.ipc 1.048781 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.048781 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11951457171 # number of integer regfile reads +system.cpu.int_regfile_writes 2254061534 # number of integer regfile writes +system.cpu.fp_regfile_reads 71109797 # number of floating regfile reads +system.cpu.fp_regfile_writes 50119198 # number of floating regfile writes +system.cpu.misc_regfile_reads 3727888158 # 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number of demand (read+write) hits -system.cpu.icache.demand_hits::total 359530551 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 359530551 # number of overall hits -system.cpu.icache.overall_hits::total 359530551 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 29629 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 29629 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 29629 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 29629 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 29629 # number of overall misses -system.cpu.icache.overall_misses::total 29629 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 243264500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 243264500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 243264500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 243264500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 243264500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 243264500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 359560180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 359560180 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 359560180 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 359560180 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 359560180 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 359560180 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8210.351345 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8210.351345 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8210.351345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8210.351345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8210.351345 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1653.132974 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.807194 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.807194 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 352434103 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 352434103 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 352434103 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 352434103 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 352434103 # number of overall hits +system.cpu.icache.overall_hits::total 352434103 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 29669 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 29669 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 29669 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 29669 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 29669 # number of overall misses +system.cpu.icache.overall_misses::total 29669 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 256567500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 256567500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 256567500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 256567500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 256567500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 256567500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 352463772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 352463772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 352463772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 352463772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 352463772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 352463772 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8647.662543 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8647.662543 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8647.662543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8647.662543 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8647.662543 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +557,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 731 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 731 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 731 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 731 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 166216000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 166216000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 166216000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5751.816735 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5751.816735 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5751.816735 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5751.816735 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 738 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 738 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 738 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 738 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 738 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 738 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28931 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28931 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28931 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28931 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28931 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28931 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178433000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 178433000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178433000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 178433000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178433000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 178433000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6167.536552 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6167.536552 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6167.536552 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6167.536552 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533081 # number of replacements -system.cpu.dcache.tagsinuse 4094.855996 # Cycle average of tags in use -system.cpu.dcache.total_refs 980345028 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537177 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 637.756763 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 283497000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.855996 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999721 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999721 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27888772000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105104619500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105104619500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105104619500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105104619500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 706476047 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 706476047 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1533235 # number of replacements +system.cpu.dcache.tagsinuse 4094.869938 # Cycle average of tags in use +system.cpu.dcache.total_refs 976399177 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537331 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 635.126188 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 278705000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.869938 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999724 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999724 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 700249991 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 700249991 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276118441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276118441 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11312 # 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number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2889728 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2889728 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2889728 # number of overall misses +system.cpu.dcache.overall_misses::total 2889728 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84515499000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84515499000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31029320000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31029320000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 296000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 115544819000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 115544819000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 115544819000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 115544819000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 702322482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 702322482 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11582 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11582 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 10994 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 10994 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 983411725 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 983411725 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 983411725 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 983411725 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002952 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002952 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000259 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000259 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33822.408134 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33822.408134 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34118.712411 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34118.712411 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33900.527612 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11322 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11322 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10779 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10779 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 979258160 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 979258160 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 979258160 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 979258160 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002951 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002951 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002951 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000883 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002951 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002951 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40779.669972 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40779.669972 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37968.569705 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37968.569705 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29600 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29600 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39984.669491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39984.669491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39984.669491 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 86 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks -system.cpu.dcache.writebacks::total 108430 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 818362 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 818362 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740610 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 740610 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1558972 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1558972 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1558972 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1558972 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464617 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464617 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76794 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76794 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541411 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541411 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541411 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541411 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50261586500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50261586500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2476957500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2476957500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52738544000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52738544000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52738544000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52738544000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002073 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002073 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 108671 # number of writebacks +system.cpu.dcache.writebacks::total 108671 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 607721 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 607721 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 740509 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 740509 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 10 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 10 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1348230 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1348230 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1348230 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1348230 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464770 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464770 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76728 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76728 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541498 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541498 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541498 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541498 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 56538138500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 56538138500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2635948000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2635948000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 59174086500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 59174086500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 59174086500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 59174086500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002086 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002086 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34317.221840 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34317.221840 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32254.570670 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32254.570670 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34214.459349 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34214.459349 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001574 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001574 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001574 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001574 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38598.645862 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38598.645862 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34354.446877 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34354.446877 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38387.391031 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38387.391031 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480118 # number of replacements -system.cpu.l2cache.tagsinuse 32698.465426 # Cycle average of tags in use -system.cpu.l2cache.total_refs 83907 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512862 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.055462 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480138 # number of replacements +system.cpu.l2cache.tagsinuse 32697.181297 # Cycle average of tags in use +system.cpu.l2cache.total_refs 84298 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512881 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.055720 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3079.828905 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 55.596030 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29563.040491 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.093989 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001697 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.902192 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997878 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21536 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 53875 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 75411 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 108430 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 108430 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 3151.564148 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 56.407826 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29489.209323 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.096178 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001721 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.899939 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997839 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 21652 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 53983 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 75635 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 108671 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 108671 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6481 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6481 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21536 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 60356 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 81892 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21536 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 60356 # number of overall hits -system.cpu.l2cache.overall_hits::total 81892 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3130 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1410741 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1413871 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4230 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4230 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66081 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66081 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3130 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1476822 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1479952 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3130 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101115000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46222898000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46324013000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.126449 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963201 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.949342 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999291 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999291 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910683 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910683 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 52043294256 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 52155344165 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112049909 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 52043294256 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 52155344165 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.125257 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963129 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.949198 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999280 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999280 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35277.085069 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34480.154285 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34480.154285 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36121.827531 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35239.653243 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35241.502307 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36121.827531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35239.653243 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35241.502307 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |