diff options
Diffstat (limited to 'tests/long/se/40.perlbmk')
15 files changed, 1477 insertions, 1485 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index c3e480ad3..1dc93d52f 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -489,7 +489,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 9147626b9..fbf7fa994 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:24:16 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:12:31 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 645508416000 because target called exit() +Exiting @ tick 639588907000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index b1e9e0d80..f93e57319 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.645508 # Number of seconds simulated -sim_ticks 645508416000 # Number of ticks simulated -final_tick 645508416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.639589 # Number of seconds simulated +sim_ticks 639588907000 # Number of ticks simulated +final_tick 639588907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137005 # Simulator instruction rate (inst/s) -host_op_rate 137005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48511232 # Simulator tick rate (ticks/s) -host_mem_usage 222596 # Number of bytes of host memory used -host_seconds 13306.37 # Real time elapsed on the host +host_inst_rate 210347 # Simulator instruction rate (inst/s) +host_op_rate 210347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 73797228 # Simulator tick rate (ticks/s) +host_mem_usage 229080 # Number of bytes of host memory used +host_seconds 8666.84 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 192384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94602752 # Number of bytes read from this memory -system.physmem.bytes_read::total 94795136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 192384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 192384 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 191360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94464192 # Number of bytes read from this memory +system.physmem.bytes_read::total 94655552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 191360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 191360 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3006 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1478168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1481174 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2990 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476003 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1478993 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 298035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146555412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 146853447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 298035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 298035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6632713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6632713 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6632713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 298035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146555412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 153486160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 299192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 147695169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 147994362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 299192 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 299192 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6694100 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6694100 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6694100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 299192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 147695169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 154688461 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 526109598 # DTB read hits -system.cpu.dtb.read_misses 625347 # DTB read misses +system.cpu.dtb.read_hits 525683715 # DTB read hits +system.cpu.dtb.read_misses 628896 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 526734945 # DTB read accesses -system.cpu.dtb.write_hits 292167921 # DTB write hits -system.cpu.dtb.write_misses 53946 # DTB write misses +system.cpu.dtb.read_accesses 526312611 # DTB read accesses +system.cpu.dtb.write_hits 287304184 # DTB write hits +system.cpu.dtb.write_misses 53890 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 292221867 # DTB write accesses -system.cpu.dtb.data_hits 818277519 # DTB hits -system.cpu.dtb.data_misses 679293 # DTB misses +system.cpu.dtb.write_accesses 287358074 # DTB write accesses +system.cpu.dtb.data_hits 812987899 # DTB hits +system.cpu.dtb.data_misses 682786 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 818956812 # DTB accesses -system.cpu.itb.fetch_hits 402604817 # ITB hits -system.cpu.itb.fetch_misses 847 # ITB misses +system.cpu.dtb.data_accesses 813670685 # DTB accesses +system.cpu.itb.fetch_hits 398461552 # ITB hits +system.cpu.itb.fetch_misses 1212 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 402605664 # ITB accesses +system.cpu.itb.fetch_accesses 398462764 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,247 +67,247 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1291016833 # number of cpu cycles simulated +system.cpu.numCycles 1279177815 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 393573728 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 256530657 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 27586844 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 324820294 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 261991971 # Number of BTB hits +system.cpu.BPredUnit.lookups 391601012 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 255930815 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 27097905 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 318432805 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 256621752 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 57786471 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 8197 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 421176645 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3321335108 # Number of instructions fetch has processed -system.cpu.fetch.Branches 393573728 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 319778442 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638257970 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 162812665 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 96711303 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 59044090 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7305 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 417206849 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3304631660 # Number of instructions fetch has processed +system.cpu.fetch.Branches 391601012 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315665842 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 634205086 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 158948618 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 96266839 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 158 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8593 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 402604817 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 9565592 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1290891849 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.572900 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.136734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 11708 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 398461552 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8907646 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1279053519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.583654 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.145594 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 652633879 50.56% 50.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 59721794 4.63% 55.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 43804545 3.39% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 72624877 5.63% 64.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 127484332 9.88% 74.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46855386 3.63% 77.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41599950 3.22% 80.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7021053 0.54% 81.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 239146033 18.53% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 644848433 50.42% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 60073670 4.70% 55.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 44904383 3.51% 58.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71013010 5.55% 64.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 124436565 9.73% 73.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 45667903 3.57% 77.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41114141 3.21% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7023739 0.55% 81.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 239971675 18.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1290891849 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.304856 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.572651 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 453921580 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 79454568 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 612779431 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10011349 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 134724921 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33550717 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12520 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3227083732 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46784 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 134724921 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 483920973 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 32457268 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 25980 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 591448832 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 48313875 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3136668879 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 405 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 8064 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 42516144 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2086288186 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3648925200 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3531562512 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 117362688 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1279053519 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.306135 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.583403 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 450209575 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 79019815 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 608453320 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10020119 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131350690 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33655569 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12307 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3205531959 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46810 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131350690 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 478839352 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 32033074 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 25872 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 588505763 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 48298768 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3118953725 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 371 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 8014 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 42155636 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2071308237 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3619384197 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3501684594 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117699603 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 701319116 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4353 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 267 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 142890931 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 736649308 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 360329563 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68950696 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9282518 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2642275746 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 205 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2193056773 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17946555 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 819111732 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 708893207 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1290891849 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.698869 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.804017 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 686339167 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4232 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 137 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 140575935 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 734762265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 354500186 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67932920 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9138793 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2625466002 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2176735177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17945547 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 802302909 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 703322223 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 83 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1279053519 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.701833 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.797036 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 470876253 36.48% 36.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 218068463 16.89% 53.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 252707156 19.58% 72.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121463164 9.41% 82.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 106308054 8.24% 90.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 77452334 6.00% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 21076392 1.63% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17287996 1.34% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5652037 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 464081398 36.28% 36.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 216592353 16.93% 53.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 250622762 19.59% 72.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 121884176 9.53% 82.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104836053 8.20% 90.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 77987896 6.10% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 21570720 1.69% 98.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17288528 1.35% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4189633 0.33% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1290891849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1279053519 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1141130 3.16% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24070571 66.71% 69.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10868345 30.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1140853 3.19% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 24076891 67.30% 70.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10558644 29.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1255545244 57.25% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 16688 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 29218260 1.33% 58.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254696 0.38% 58.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 589185884 26.87% 86.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 303628594 13.84% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1247700404 57.32% 57.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 16695 0.00% 57.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 28729941 1.32% 58.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254693 0.38% 59.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204651 0.33% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 586556392 26.95% 86.30% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 298269645 13.70% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2193056773 # Type of FU issued -system.cpu.iq.rate 1.698705 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36080046 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016452 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5576578817 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3377639693 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2021595592 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 154453179 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 83821528 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 75359015 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2150081181 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 79052886 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67169273 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2176735177 # Type of FU issued +system.cpu.iq.rate 1.701667 # Inst issue rate +system.cpu.iq.fu_busy_cnt 35776388 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016436 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5534048167 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3341408955 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2010160977 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 152197641 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 86432816 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 74384435 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2134737053 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77771760 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67976479 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 225579282 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22953 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76359 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 149534667 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 223692239 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13198 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75649 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 143705290 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4418 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4417 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 29 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 134724921 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3817892 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 203271 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3000868514 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 2715875 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 736649308 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 360329563 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 205 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 131040 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4909 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76359 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 27588382 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 31906 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 27620288 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2101232365 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 526735105 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 91824408 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131350690 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3811054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 200562 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2981894857 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 2707472 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 734762265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 354500186 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 131033 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4888 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 75649 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 27118847 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 31958 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 27150805 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2088347607 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 526312810 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 88387570 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 358592563 # number of nop insts executed -system.cpu.iew.exec_refs 818957488 # number of memory reference insts executed -system.cpu.iew.exec_branches 281208298 # Number of branches executed -system.cpu.iew.exec_stores 292222383 # Number of stores executed -system.cpu.iew.exec_rate 1.627579 # Inst execution rate -system.cpu.iew.wb_sent 2099740429 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2096954607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1185148628 # num instructions producing a value -system.cpu.iew.wb_consumers 1754528061 # num instructions consuming a value +system.cpu.iew.exec_nop 356428733 # number of nop insts executed +system.cpu.iew.exec_refs 813671363 # number of memory reference insts executed +system.cpu.iew.exec_branches 280895404 # Number of branches executed +system.cpu.iew.exec_stores 287358553 # Number of stores executed +system.cpu.iew.exec_rate 1.632570 # Inst execution rate +system.cpu.iew.wb_sent 2087345359 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2084545412 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1181911333 # num instructions producing a value +system.cpu.iew.wb_consumers 1746825923 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.624266 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.675480 # average fanout of values written-back +system.cpu.iew.wb_rate 1.629598 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.676605 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 975184756 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 956239558 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 27574586 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1156166928 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.737628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.495396 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 27085717 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1147702829 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.750442 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.504523 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 540094894 46.71% 46.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 227413285 19.67% 66.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 119190896 10.31% 76.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 56737431 4.91% 81.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 50997203 4.41% 86.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24159454 2.09% 88.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18394192 1.59% 89.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 15607584 1.35% 91.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 103571989 8.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 533397723 46.48% 46.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 226612269 19.74% 66.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 118218768 10.30% 76.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 56744377 4.94% 81.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50032490 4.36% 85.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24020067 2.09% 87.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19167450 1.67% 89.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 15607807 1.36% 90.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103901878 9.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1156166928 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1147702829 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -318,70 +318,70 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 103571989 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103901878 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4031130889 # The number of ROB reads -system.cpu.rob.rob_writes 6103072592 # The number of ROB writes -system.cpu.timesIdled 3457 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 124984 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 4003391703 # The number of ROB reads +system.cpu.rob.rob_writes 6061807983 # The number of ROB writes +system.cpu.timesIdled 3462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 124296 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.708166 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.708166 # CPI: Total CPI of All Threads -system.cpu.ipc 1.412099 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.412099 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2678294251 # number of integer regfile reads -system.cpu.int_regfile_writes 1517633044 # number of integer regfile writes -system.cpu.fp_regfile_reads 81926245 # number of floating regfile reads -system.cpu.fp_regfile_writes 54028832 # number of floating regfile writes +system.cpu.cpi 0.701672 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.701672 # CPI: Total CPI of All Threads +system.cpu.ipc 1.425168 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.425168 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2657999656 # number of integer regfile reads +system.cpu.int_regfile_writes 1510398630 # number of integer regfile writes +system.cpu.fp_regfile_reads 80463471 # number of floating regfile reads +system.cpu.fp_regfile_writes 53540440 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8444 # number of replacements -system.cpu.icache.tagsinuse 1673.037469 # Cycle average of tags in use -system.cpu.icache.total_refs 402593289 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10171 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 39582.468685 # Average number of references to valid blocks. +system.cpu.icache.replacements 8417 # number of replacements +system.cpu.icache.tagsinuse 1667.677082 # Cycle average of tags in use +system.cpu.icache.total_refs 398450176 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39306.518299 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1673.037469 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.816913 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.816913 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 402593289 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 402593289 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 402593289 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 402593289 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 402593289 # number of overall hits -system.cpu.icache.overall_hits::total 402593289 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11528 # number of overall misses -system.cpu.icache.overall_misses::total 11528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 191663000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 191663000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 191663000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 191663000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 191663000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 191663000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 402604817 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 402604817 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 402604817 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 402604817 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 402604817 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 402604817 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1667.677082 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.814295 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.814295 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 398450176 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 398450176 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 398450176 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 398450176 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 398450176 # number of overall hits +system.cpu.icache.overall_hits::total 398450176 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11376 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11376 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11376 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11376 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11376 # number of overall misses +system.cpu.icache.overall_misses::total 11376 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 188382000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 188382000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 188382000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 188382000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 188382000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 188382000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 398461552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 398461552 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 398461552 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 398461552 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 398461552 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 398461552 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16625.867453 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16625.867453 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16625.867453 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16625.867453 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16625.867453 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16559.599156 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16559.599156 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16559.599156 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16559.599156 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16559.599156 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16559.599156 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,304 +390,296 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1356 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1356 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1356 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1356 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1356 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1356 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10172 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10172 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10172 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10172 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10172 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10172 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123488000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 123488000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123488000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 123488000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123488000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 123488000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1238 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1238 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1238 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1238 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1238 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1238 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10138 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10138 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10138 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10138 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10138 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10138 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 122862500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 122862500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122862500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 122862500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12139.992135 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12139.992135 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12139.992135 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12139.992135 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12119.007694 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12119.007694 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12119.007694 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12119.007694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12119.007694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12119.007694 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1528059 # number of replacements -system.cpu.dcache.tagsinuse 4095.059846 # Cycle average of tags in use -system.cpu.dcache.total_refs 667250429 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1532155 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 435.497994 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 267049000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.059846 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999770 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999770 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 457007415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 457007415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 210242966 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 210242966 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 48 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 48 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 667250381 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 667250381 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 667250381 # number of overall hits -system.cpu.dcache.overall_hits::total 667250381 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1928420 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1928420 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 551930 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 551930 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.replacements 1527982 # number of replacements +system.cpu.dcache.tagsinuse 4095.064488 # Cycle average of tags in use +system.cpu.dcache.total_refs 666017344 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1532078 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 434.715037 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 264095000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4095.064488 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999772 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999772 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 455774339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 455774339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 210242956 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 210242956 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 49 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 49 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 666017295 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 666017295 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 666017295 # number of overall hits +system.cpu.dcache.overall_hits::total 666017295 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1928410 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1928410 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 551940 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 551940 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses system.cpu.dcache.demand_misses::cpu.data 2480350 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2480350 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2480350 # number of overall misses system.cpu.dcache.overall_misses::total 2480350 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71491683500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71491683500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20877271991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20877271991 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 58500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 58500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92368955491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92368955491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92368955491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92368955491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 458935835 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 458935835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71225328000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71225328000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 20805642991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 20805642991 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 20500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 20500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92030970991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92030970991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92030970991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92030970991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 457702749 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 457702749 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 50 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 50 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 669730731 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 669730731 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 669730731 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 669730731 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004202 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 668497645 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 668497645 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 668497645 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 668497645 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004213 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004213 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002618 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002618 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.040000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.040000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003704 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003704 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003704 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003704 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37072.672706 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37072.672706 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.941679 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.941679 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 29250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 29250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37240.290883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37240.290883 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37240.290883 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 99000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 23000 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.020000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.020000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003710 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003710 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003710 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003710 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36934.743130 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36934.743130 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37695.479565 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37695.479565 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37104.026041 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37104.026041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37104.026041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37104.026041 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 98500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 22000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6187.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6156.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107245 # number of writebacks -system.cpu.dcache.writebacks::total 107245 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467870 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 467870 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 480326 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 109405 # number of writebacks +system.cpu.dcache.writebacks::total 109405 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467937 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467937 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 480335 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 480335 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 948196 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 948196 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 948196 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 948196 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460550 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460550 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71604 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71604 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1532154 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1532154 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1532154 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1532154 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49990545000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 49990545000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2492898500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2492898500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 35000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52483443500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52483443500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52483443500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52483443500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003182 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003182 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 948272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 948272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 948272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 948272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460473 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460473 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71605 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71605 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1532078 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1532078 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1532078 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1532078 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49721165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 49721165500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2483602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2483602000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52204767500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52204767500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52204767500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52204767500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003191 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003191 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.020000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.020000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002288 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002288 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34227.205505 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34227.205505 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34815.073180 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34815.073180 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 35000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34254.679034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34254.679034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34254.679034 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002292 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002292 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002292 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002292 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34044.563302 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34044.563302 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34684.756651 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34684.756651 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34074.484132 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34074.484132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34074.484132 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34074.484132 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480784 # number of replacements -system.cpu.l2cache.tagsinuse 31940.343129 # Cycle average of tags in use -system.cpu.l2cache.total_refs 64039 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513473 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.042313 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1480674 # number of replacements +system.cpu.l2cache.tagsinuse 32705.756030 # Cycle average of tags in use +system.cpu.l2cache.total_refs 66279 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1513408 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.043795 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3040.164037 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 45.228004 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28854.951088 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.092778 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001380 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.880583 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.974742 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7166 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 49233 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 56399 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107245 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107245 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7166 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 53987 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 61153 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 7166 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 53987 # number of overall hits -system.cpu.l2cache.overall_hits::total 61153 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3006 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1411318 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1414324 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66850 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66850 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3006 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1478168 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1481174 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3006 # 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mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.294930 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963399 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.959005 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.826087 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.658908 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31000.864645 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31982.865391 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31982.865391 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.826087 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31045.146250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31045.252750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.826087 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31045.146250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31045.252750 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index f9460f41a..acb7a4c77 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -158,7 +158,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing +cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index 508096573..85893d278 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:40:02 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:15:06 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2813467842000 because target called exit() +Exiting @ tick 2813377164000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index c273e38a0..9b3a7daff 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.813468 # Number of seconds simulated -sim_ticks 2813467842000 # Number of ticks simulated -final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.813377 # Number of seconds simulated +sim_ticks 2813377164000 # Number of ticks simulated +final_tick 2813377164000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1483350 # Simulator instruction rate (inst/s) -host_op_rate 1483350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2077343480 # Simulator tick rate (ticks/s) -host_mem_usage 220820 # Number of bytes of host memory used -host_seconds 1354.36 # Real time elapsed on the host +host_inst_rate 2127881 # Simulator instruction rate (inst/s) +host_op_rate 2127880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2979874149 # Simulator tick rate (ticks/s) +host_mem_usage 227924 # Number of bytes of host memory used +host_seconds 944.13 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 152128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94556032 # Number of bytes read from this memory -system.physmem.bytes_read::total 94708160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94417856 # Number of bytes read from this memory +system.physmem.bytes_read::total 94569984 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 152128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 152128 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4281472 # Number of bytes written to this memory system.physmem.bytes_written::total 4281472 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2377 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1477438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1475279 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1477656 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66898 # Number of write requests responded to by this memory system.physmem.num_writes::total 66898 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 54071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33608357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33662428 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 54071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 54071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1521777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1521777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1521777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 54071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33608357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 35184206 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 54073 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33560326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33614400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54073 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1521827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1521827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1521827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33560326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 35136226 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 5626935684 # number of cpu cycles simulated +system.cpu.numCycles 5626754328 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2008987605 # Number of instructions committed @@ -86,16 +86,16 @@ system.cpu.num_mem_refs 722298387 # nu system.cpu.num_load_insts 511488910 # Number of load instructions system.cpu.num_store_insts 210809477 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5626935684 # Number of busy cycles +system.cpu.num_busy_cycles 5626754328 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 9046 # number of replacements -system.cpu.icache.tagsinuse 1478.423269 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1478.423352 # Cycle average of tags in use system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1478.423269 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1478.423352 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.721886 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.721886 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits @@ -168,12 +168,12 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305 system.cpu.icache.overall_avg_mshr_miss_latency::total 20421.857305 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1526048 # number of replacements -system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4095.204600 # Cycle average of tags in use system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4095.204626 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4095.204600 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999806 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999806 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 1530144 # n system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses system.cpu.dcache.overall_misses::total 1530144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79658418000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79658418000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79567740000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79567740000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3815994000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3815994000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83474412000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83474412000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83474412000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83474412000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83383734000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83383734000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83383734000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83383734000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54628.209454 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54628.209454 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54566.024227 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54566.024227 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 53035.273516 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54553.304787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54553.304787 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54553.304787 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54494.043698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54494.043698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54494.043698 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107612 # number of writebacks -system.cpu.dcache.writebacks::total 107612 # number of writebacks +system.cpu.dcache.writebacks::writebacks 109771 # number of writebacks +system.cpu.dcache.writebacks::total 109771 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75283842000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75283842000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75193164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75193164000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78883980000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78883980000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78883980000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78883980000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78793302000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78793302000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78793302000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51628.209454 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51628.209454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51566.024227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51566.024227 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51553.304787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51553.304787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51553.304787 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51494.043698 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51494.043698 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1479797 # number of replacements -system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use -system.cpu.l2cache.total_refs 63431 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1512480 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.041938 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1479705 # number of replacements +system.cpu.l2cache.tagsinuse 32704.227313 # Cycle average of tags in use +system.cpu.l2cache.total_refs 65761 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1512436 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.043480 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3081.828747 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.409968 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28814.603011 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.094050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001020 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.879352 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.974421 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3254.893374 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 33.487953 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29415.845986 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.099331 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001022 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.897700 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.998054 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 47627 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 55846 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107612 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107612 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 49786 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 58005 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109771 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109771 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 8219 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 52706 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 60925 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 54865 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 63084 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 8219 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 52706 # number of overall hits -system.cpu.l2cache.overall_hits::total 60925 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 54865 # number of overall hits +system.cpu.l2cache.overall_hits::total 63084 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2377 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1410565 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1412942 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1408406 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1410783 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66873 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66873 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2377 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1477438 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1479815 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1475279 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1477656 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2377 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1477438 # number of overall misses -system.cpu.l2cache.overall_misses::total 1479815 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1475279 # number of overall misses +system.cpu.l2cache.overall_misses::total 1477656 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 123604000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73349380000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73472984000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73237112000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 73360716000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3477396000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3477396000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 123604000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 76826776000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 76950380000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 76714508000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 76838112000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 123604000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 76826776000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 76950380000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 76714508000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 76838112000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 107612 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107612 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109771 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109771 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses @@ -329,16 +329,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 10596 system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.967338 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.961978 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.965858 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.960508 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.965555 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.960457 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964144 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.959056 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.965555 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.960457 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964144 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.959056 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -361,38 +361,38 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks system.cpu.l2cache.writebacks::total 66898 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2377 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410565 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1412942 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1408406 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1410783 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2377 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1477438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1479815 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1475279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1477656 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1477438 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1479815 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1475279 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1477656 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56422600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56517680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56336240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56431320000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59097520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59192600000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59011160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59106240000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59097520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59192600000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59011160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 59106240000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.967338 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.961978 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965858 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.960508 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.929411 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.960457 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.959056 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.960457 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964144 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.959056 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index d9870188c..420e789e0 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -507,7 +507,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 0c5c10637..95a99c94b 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:06:13 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:01:11 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 735495062500 because target called exit() +Exiting @ tick 734755023500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 81f1da57a..abd280906 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.735495 # Number of seconds simulated -sim_ticks 735495062500 # Number of ticks simulated -final_tick 735495062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.734755 # Number of seconds simulated +sim_ticks 734755023500 # Number of ticks simulated +final_tick 734755023500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76677 # Simulator instruction rate (inst/s) -host_op_rate 104424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40737062 # Simulator tick rate (ticks/s) -host_mem_usage 237976 # Number of bytes of host memory used -host_seconds 18054.69 # Real time elapsed on the host -sim_insts 1384379503 # Number of instructions simulated -sim_ops 1885334256 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 213952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94625728 # Number of bytes read from this memory -system.physmem.bytes_read::total 94839680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 213952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 213952 # Number of instructions bytes read from this memory +host_inst_rate 119232 # Simulator instruction rate (inst/s) +host_op_rate 162378 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63282228 # Simulator tick rate (ticks/s) +host_mem_usage 243808 # Number of bytes of host memory used +host_seconds 11610.76 # Real time elapsed on the host +sim_insts 1384372850 # Number of instructions simulated +sim_ops 1885327602 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 205760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94510912 # Number of bytes read from this memory +system.physmem.bytes_read::total 94716672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 205760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 205760 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1478527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1481870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476733 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1479948 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 290895 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 128655830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128946726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 290895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 290895 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5751685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5751685 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5751685 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 290895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 128655830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134698411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 280039 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 128629147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 128909186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 280039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 280039 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 5757478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5757478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 5757478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 280039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 128629147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134666664 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,322 +77,322 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1470990126 # number of cpu cycles simulated +system.cpu.numCycles 1469510048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 524657246 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 401089358 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 35661760 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 339540356 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 278948773 # Number of BTB hits +system.cpu.BPredUnit.lookups 526868038 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 401113446 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 36046358 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 383398262 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 286508671 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 59722038 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2842670 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 444619593 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2613573524 # Number of instructions fetch has processed -system.cpu.fetch.Branches 524657246 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 338670811 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 712273911 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 223851331 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 98512911 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 29657 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 414743940 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11577936 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1438039773 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.556437 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.167543 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 60655682 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2811201 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 448614021 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2626557864 # Number of instructions fetch has processed +system.cpu.fetch.Branches 526868038 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 347164353 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 716084096 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 226374824 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 100079168 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 20420 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 419610687 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12785505 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1449541071 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.542405 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.156280 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 725823899 50.47% 50.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 56807029 3.95% 54.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 112550044 7.83% 62.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 69779758 4.85% 67.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 84813159 5.90% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 53785792 3.74% 76.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34099274 2.37% 79.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 30811930 2.14% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 269568888 18.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 733526710 50.60% 50.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 55834579 3.85% 54.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113825896 7.85% 62.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 72745123 5.02% 67.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 84690661 5.84% 73.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 54721422 3.78% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 33849353 2.34% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 34645380 2.39% 81.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 265701947 18.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1438039773 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.356669 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.776744 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 492128614 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 78582078 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 673411779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 11338206 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 182579096 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 79653725 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 23825 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3539524175 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 54394 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 182579096 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 529782652 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 30198632 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 660985 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 645094382 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49724026 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3431194053 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4188042 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40587721 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1707 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3342681891 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16249059655 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15604311677 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 644747978 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993154351 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1349527540 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 64268 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 59597 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138053548 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1061160981 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 575711799 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 34121400 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 39206197 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3192585936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 69047 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2718019401 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 27726721 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1306902480 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3048220381 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45882 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1438039773 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.890086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.916332 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1449541071 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.358533 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.787370 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 497288026 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 79567524 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 676485575 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 11475102 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 184724844 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 81162192 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 16785 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3548614330 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 38542 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 184724844 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 535414239 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 30600962 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 541148 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 648147088 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50112790 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3434293747 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 117 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4398993 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 40741019 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1775 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 3359442434 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 16257634697 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 15596931258 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 660703439 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993143706 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1366298728 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 50062 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 45371 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 137456980 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1058714008 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 577829073 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 31866160 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36849262 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3203795171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 52627 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2727879490 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 26513766 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1318072615 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3048733772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 30791 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1449541071 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.881892 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.914534 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 521512118 36.27% 36.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 198246164 13.79% 50.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216916723 15.08% 65.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 178677193 12.43% 77.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 155355732 10.80% 88.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 100852221 7.01% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 48369591 3.36% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10873615 0.76% 99.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7236416 0.50% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 528205619 36.44% 36.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 200385301 13.82% 50.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 218048243 15.04% 65.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 179845166 12.41% 77.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 155269867 10.71% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 101678601 7.01% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 47766137 3.30% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10944186 0.76% 99.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7397951 0.51% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1438039773 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1449541071 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1743579 1.83% 1.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23896 0.03% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56969230 59.63% 61.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36797024 38.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1786371 1.87% 1.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23899 0.03% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 56927453 59.70% 61.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36612005 38.40% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1258053988 46.29% 46.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11231448 0.41% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876560 0.25% 47.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503486 0.20% 47.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 73 0.00% 47.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23204970 0.85% 48.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 902246151 33.19% 81.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 509527435 18.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1265692730 46.40% 46.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11246210 0.41% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876504 0.25% 47.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5503517 0.20% 47.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 65 0.00% 47.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23431459 0.86% 48.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 901624360 33.05% 81.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 512129355 18.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2718019401 # Type of FU issued -system.cpu.iq.rate 1.847748 # Inst issue rate -system.cpu.iq.fu_busy_cnt 95533729 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035148 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6864166409 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4398397135 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2490268759 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 133172616 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 101224152 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59789124 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2745104459 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 68448671 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 72240187 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2727879490 # Type of FU issued +system.cpu.iq.rate 1.856319 # Inst issue rate +system.cpu.iq.fu_busy_cnt 95349728 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.034954 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6892702222 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4416661768 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2501406306 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 134461323 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 105324073 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59997583 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2754068673 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 69160545 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 71273395 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 429772018 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 278201 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1347099 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 298714721 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 427326375 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 261567 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1134338 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 300833324 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 182579096 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 16373982 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1591067 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3192732241 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 7809183 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1061160981 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 575711799 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 58058 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1589162 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 317 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1347099 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 36984086 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8972300 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 45956386 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2617990910 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 846641153 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100028491 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 184724844 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 16014821 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1979639 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3203920541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4008843 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1058714008 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 577829073 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 42582 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1976809 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 591 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1134338 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 37198169 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9007131 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 46205300 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2628771663 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 847609803 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 99107827 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 77258 # number of nop insts executed -system.cpu.iew.exec_refs 1326395495 # number of memory reference insts executed -system.cpu.iew.exec_branches 359930496 # Number of branches executed -system.cpu.iew.exec_stores 479754342 # Number of stores executed -system.cpu.iew.exec_rate 1.779747 # Inst execution rate -system.cpu.iew.wb_sent 2578580051 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2550057883 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1472840060 # num instructions producing a value -system.cpu.iew.wb_consumers 2760220207 # num instructions consuming a value +system.cpu.iew.exec_nop 72743 # number of nop insts executed +system.cpu.iew.exec_refs 1330077082 # number of memory reference insts executed +system.cpu.iew.exec_branches 361648549 # Number of branches executed +system.cpu.iew.exec_stores 482467279 # Number of stores executed +system.cpu.iew.exec_rate 1.788876 # Inst execution rate +system.cpu.iew.wb_sent 2589616129 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2561403889 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1477403496 # num instructions producing a value +system.cpu.iew.wb_consumers 2764851406 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.733566 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533595 # average fanout of values written-back +system.cpu.iew.wb_rate 1.743033 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534352 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 1384390519 # The number of committed instructions -system.cpu.commit.commitCommittedOps 1885345272 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 1307387427 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 23165 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 41179561 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1255460679 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.501716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.213055 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 1384383866 # The number of committed instructions +system.cpu.commit.commitCommittedOps 1885338618 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 1318582287 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 21836 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 41567877 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1264816229 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.490603 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.207767 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 576199063 45.90% 45.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 316668907 25.22% 71.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 101245126 8.06% 79.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79298067 6.32% 85.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 52885974 4.21% 89.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24348674 1.94% 91.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17176683 1.37% 93.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9160932 0.73% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78477253 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 584481462 46.21% 46.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 317753060 25.12% 71.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 101743247 8.04% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 79200545 6.26% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 52876697 4.18% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23864362 1.89% 91.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 17162643 1.36% 93.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9180731 0.73% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78553482 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1255460679 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384390519 # Number of instructions committed -system.cpu.commit.committedOps 1885345272 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1264816229 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384383866 # Number of instructions committed +system.cpu.commit.committedOps 1885338618 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908386041 # Number of memory references committed -system.cpu.commit.loads 631388963 # Number of loads committed +system.cpu.commit.refs 908383382 # Number of memory references committed +system.cpu.commit.loads 631387633 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350326 # Number of branches committed +system.cpu.commit.branches 291348996 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705999 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653700675 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78477253 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 78553482 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4369697780 # The number of ROB reads -system.cpu.rob.rob_writes 6568059146 # The number of ROB writes -system.cpu.timesIdled 1341236 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32950353 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384379503 # Number of Instructions Simulated -system.cpu.committedOps 1885334256 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384379503 # Number of Instructions Simulated -system.cpu.cpi 1.062563 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.062563 # CPI: Total CPI of All Threads -system.cpu.ipc 0.941121 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.941121 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12914363689 # number of integer regfile reads -system.cpu.int_regfile_writes 2421503464 # number of integer regfile writes -system.cpu.fp_regfile_reads 71102089 # number of floating regfile reads -system.cpu.fp_regfile_writes 50855882 # number of floating regfile writes -system.cpu.misc_regfile_reads 4088825153 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776464 # number of misc regfile writes -system.cpu.icache.replacements 29072 # number of replacements -system.cpu.icache.tagsinuse 1666.420003 # Cycle average of tags in use -system.cpu.icache.total_refs 414707358 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30775 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13475.462486 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 4390165307 # The number of ROB reads +system.cpu.rob.rob_writes 6592584661 # The number of ROB writes +system.cpu.timesIdled 1305443 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19968977 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384372850 # Number of Instructions Simulated +system.cpu.committedOps 1885327602 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384372850 # Number of Instructions Simulated +system.cpu.cpi 1.061499 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.061499 # CPI: Total CPI of All Threads +system.cpu.ipc 0.942064 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.942064 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12961850201 # number of integer regfile reads +system.cpu.int_regfile_writes 2434855102 # number of integer regfile writes +system.cpu.fp_regfile_reads 71417921 # number of floating regfile reads +system.cpu.fp_regfile_writes 51448336 # number of floating regfile writes +system.cpu.misc_regfile_reads 4106986212 # number of misc regfile reads +system.cpu.misc_regfile_writes 13773806 # number of misc regfile writes +system.cpu.icache.replacements 25589 # number of replacements +system.cpu.icache.tagsinuse 1654.450414 # Cycle average of tags in use +system.cpu.icache.total_refs 419572856 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 27281 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15379.672886 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1666.420003 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.813682 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.813682 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 414707364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 414707364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 414707364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 414707364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 414707364 # number of overall hits -system.cpu.icache.overall_hits::total 414707364 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 36576 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 36576 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 36576 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 36576 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 36576 # number of overall misses -system.cpu.icache.overall_misses::total 36576 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 322136500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 322136500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 322136500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 322136500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 322136500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 322136500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 414743940 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 414743940 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 414743940 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 414743940 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 414743940 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 414743940 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000088 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000088 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8807.319007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8807.319007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8807.319007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8807.319007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8807.319007 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1654.450414 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.807837 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.807837 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 419577538 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 419577538 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 419577538 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 419577538 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 419577538 # number of overall hits +system.cpu.icache.overall_hits::total 419577538 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33149 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33149 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33149 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33149 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33149 # number of overall misses +system.cpu.icache.overall_misses::total 33149 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 298308500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 298308500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 298308500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 298308500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 298308500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 298308500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 419610687 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 419610687 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 419610687 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 419610687 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 419610687 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 419610687 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000079 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000079 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000079 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000079 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000079 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000079 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8999.019578 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8999.019578 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8999.019578 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8999.019578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8999.019578 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8999.019578 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,254 +401,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 853 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 853 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 853 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 853 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 853 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 853 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 35723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 35723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 35723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 35723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 35723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192601000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 192601000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192601000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 192601000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192601000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 192601000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5391.512471 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5391.512471 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5391.512471 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5391.512471 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 781 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 781 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 781 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 781 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 781 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 781 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32368 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 32368 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 32368 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 32368 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 32368 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 32368 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 180567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 180567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 180567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 180567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 180567000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 180567000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000077 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5578.565250 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5578.565250 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5578.565250 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5578.565250 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5578.565250 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5578.565250 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1532415 # number of replacements -system.cpu.dcache.tagsinuse 4094.914319 # Cycle average of tags in use -system.cpu.dcache.total_refs 1032974400 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1536511 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 672.285717 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 290267000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.914319 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999735 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999735 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 756817928 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 756817928 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276114576 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276114576 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13150 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13150 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11766 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11766 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1032932504 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1032932504 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1032932504 # number of overall hits -system.cpu.dcache.overall_hits::total 1032932504 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2368566 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2368566 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 821102 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 821102 # number of WriteReq misses +system.cpu.dcache.replacements 1532821 # number of replacements +system.cpu.dcache.tagsinuse 4094.970368 # Cycle average of tags in use +system.cpu.dcache.total_refs 1034449788 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1536917 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 673.068089 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 277219000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.970368 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999749 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999749 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 758296274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 758296274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276114755 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276114755 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10674 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10674 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 10437 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 10437 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1034411029 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1034411029 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1034411029 # number of overall hits +system.cpu.dcache.overall_hits::total 1034411029 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2832781 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2832781 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 820923 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 820923 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3189668 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3189668 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3189668 # number of overall misses -system.cpu.dcache.overall_misses::total 3189668 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80139479500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80139479500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28569168500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28569168500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 114500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 114500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 108708648000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 108708648000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 108708648000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 108708648000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 759186494 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 759186494 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3653704 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3653704 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3653704 # number of overall misses +system.cpu.dcache.overall_misses::total 3653704 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 91513466000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 91513466000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28577501500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28577501500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 115500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 115500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 120090967500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 120090967500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 120090967500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 120090967500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 761129055 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 761129055 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13153 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13153 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11766 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11766 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1036122172 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1036122172 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1036122172 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1036122172 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003120 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003120 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002965 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002965 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000228 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000228 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003078 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003078 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003078 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003078 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33834.598445 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33834.598445 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34793.690065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34793.690065 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34081.493121 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34081.493121 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34081.493121 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10677 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10677 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 10437 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 10437 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1038064733 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1038064733 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1038064733 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1038064733 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003722 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003722 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002964 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002964 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000281 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000281 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003520 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003520 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003520 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003520 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32305.167960 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32305.167960 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34811.427503 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34811.427503 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32868.280381 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32868.280381 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32868.280381 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32868.280381 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 81500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 62000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20375 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 106560 # number of writebacks -system.cpu.dcache.writebacks::total 106560 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904767 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 904767 # 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number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029877000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029877000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2502958500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2502958500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52532835500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52532835500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52532835500 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52477921000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52477921000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52477921000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52477921000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.946153 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.117990 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.960854 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.946153 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34287.822305 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34305.994373 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34305.953001 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.653753 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34085.653753 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34287.822305 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.134831 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34296.116751 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34287.822305 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.134831 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34296.116751 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -659,67 +659,67 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks system.cpu.l2cache.writebacks::total 66099 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3343 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412447 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1415790 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4944 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 4944 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 20 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410653 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1413868 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5084 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5084 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1478527 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1481870 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3343 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1478527 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1481870 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 103877000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43883033500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43986910500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 153264000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 153264000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048525000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048525000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 103877000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931558500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46035435500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 103877000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931558500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46035435500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964919 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947286 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999394 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999394 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908791 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908791 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.945500 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108624 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962263 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.945500 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31072.988334 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.800104 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31068.809993 # average ReadReq mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3215 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1476733 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1479948 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3215 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1476733 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1479948 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 99910500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43827558000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43927468500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 157604000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 157604000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048533500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048533500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 99910500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45876091500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 45976002000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 99910500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45876091500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 45976002000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.117843 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963334 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.947870 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999410 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999410 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910531 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910531 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.117843 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960841 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.946138 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.117843 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960841 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.946138 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31076.360809 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.985782 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31069.002552 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.680993 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.680993 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31072.988334 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.755647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.771964 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.809625 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31000.809625 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31076.360809 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.935074 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31065.957723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31076.360809 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.935074 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31065.957723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 73b2ffcd2..c9a1801d2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -95,7 +95,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 1893c8b1d..d3221b5d3 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:11:11 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:03:08 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 945613131000 because target called exit() +Exiting @ tick 945613126000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 56b9fe676..088f25fd3 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.945613 # Number of seconds simulated -sim_ticks 945613131000 # Number of ticks simulated -final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 945613126000 # Number of ticks simulated +final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1814541 # Simulator instruction rate (inst/s) -host_op_rate 2471154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1239437075 # Simulator tick rate (ticks/s) -host_mem_usage 226248 # Number of bytes of host memory used -host_seconds 762.94 # Real time elapsed on the host -sim_insts 1384381614 # Number of instructions simulated -sim_ops 1885336367 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 5561086040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2464405275 # Number of bytes read from this memory -system.physmem.bytes_read::total 8025491315 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5561086040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5561086040 # Number of instructions bytes read from this memory +host_inst_rate 2568124 # Simulator instruction rate (inst/s) +host_op_rate 3497430 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1754178123 # Simulator tick rate (ticks/s) +host_mem_usage 233172 # Number of bytes of host memory used +host_seconds 539.06 # Real time elapsed on the host +sim_insts 1384381606 # Number of instructions simulated +sim_ops 1885336358 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory +system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5561086004 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1390271510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 620345399 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2010616909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 1390271501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 620345398 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2010616899 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5880931491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2606145361 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8487076852 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5880931491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5880931491 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188602780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1188602780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5880931491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3794748141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9675679632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 5880931484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2606145374 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8487076858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5880931484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5880931484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188602786 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1891226263 # number of cpu cycles simulated +system.cpu.numCycles 1891226253 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1384381614 # Number of instructions committed -system.cpu.committedOps 1885336367 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.committedInsts 1384381606 # Number of instructions committed +system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_func_calls 80372855 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 223735905 # number of instructions that are conditional controls +system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 8601515950 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written +system.cpu.num_int_register_reads 8601515912 # number of times the integer registers were read +system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382480 # number of memory refs -system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_mem_refs 908382479 # number of memory refs +system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1891226263 # Number of busy cycles +system.cpu.num_busy_cycles 1891226253 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 1dd9a3ff2..a14c026cf 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -176,7 +176,7 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 579afd945..e82eb191d 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 18:24:05 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 01:12:18 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 2369901960000 because target called exit() +Exiting @ tick 2369826854000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 4610b3f7b..a105f9616 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.369902 # Number of seconds simulated -sim_ticks 2369901960000 # Number of ticks simulated -final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.369827 # Number of seconds simulated +sim_ticks 2369826854000 # Number of ticks simulated +final_tick 2369826854000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 768078 # Simulator instruction rate (inst/s) -host_op_rate 1041952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1317503901 # Simulator tick rate (ticks/s) -host_mem_usage 235416 # Number of bytes of host memory used -host_seconds 1798.78 # Real time elapsed on the host -sim_insts 1381604347 # Number of instructions simulated -sim_ops 1874244950 # Number of ops (including micro ops) simulated +host_inst_rate 1185646 # Simulator instruction rate (inst/s) +host_op_rate 1608413 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2033704433 # Simulator tick rate (ticks/s) +host_mem_usage 241756 # Number of bytes of host memory used +host_seconds 1165.28 # Real time elapsed on the host +sim_insts 1381604339 # Number of instructions simulated +sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94551872 # Number of bytes read from this memory -system.physmem.bytes_read::total 94696320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94437440 # Number of bytes read from this memory +system.physmem.bytes_read::total 94581888 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 144448 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 144448 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 2257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1477373 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1479630 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1475585 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1477842 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 60951 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39896955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 39957906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 60951 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1785026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1785026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 60951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39896955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41742932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 60953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39849932 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 39910885 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 60953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 60953 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1785082 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1785082 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1785082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 60953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39849932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41695968 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,43 +77,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 4739803920 # number of cpu cycles simulated +system.cpu.numCycles 4739653708 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1381604347 # Number of instructions committed -system.cpu.committedOps 1874244950 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses +system.cpu.committedInsts 1381604339 # Number of instructions committed +system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses -system.cpu.num_func_calls 80344203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223735906 # number of instructions that are conditional controls -system.cpu.num_int_insts 1653698876 # number of integer instructions +system.cpu.num_func_calls 80372855 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 223735905 # number of instructions that are conditional controls +system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions -system.cpu.num_int_register_reads 10466679954 # number of times the integer registers were read -system.cpu.num_int_register_writes 1874331406 # number of times the integer registers were written +system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read +system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written -system.cpu.num_mem_refs 908382480 # number of memory refs -system.cpu.num_load_insts 631387182 # Number of load instructions +system.cpu.num_mem_refs 908382479 # number of memory refs +system.cpu.num_load_insts 631387181 # Number of load instructions system.cpu.num_store_insts 276995298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 4739803920 # Number of busy cycles +system.cpu.num_busy_cycles 4739653708 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 18364 # number of replacements -system.cpu.icache.tagsinuse 1392.324437 # Cycle average of tags in use -system.cpu.icache.total_refs 1390251708 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1392.324421 # Cycle average of tags in use +system.cpu.icache.total_refs 1390251699 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 70204.095289 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1392.324437 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1392.324421 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1390251708 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1390251708 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1390251708 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1390251708 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1390251708 # number of overall hits -system.cpu.icache.overall_hits::total 1390251708 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits +system.cpu.icache.overall_hits::total 1390251699 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses @@ -126,12 +126,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 372036000 system.cpu.icache.demand_miss_latency::total 372036000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 372036000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 372036000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1390271511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1390271511 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1390271511 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1390271511 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1390271511 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1390271511 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses @@ -178,26 +178,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 system.cpu.icache.overall_avg_mshr_miss_latency::total 15786.850477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1529557 # number of replacements -system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use -system.cpu.dcache.total_refs 895757409 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4094.960317 # Cycle average of tags in use +system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.960333 # Average occupied blocks per requestor +system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 997872000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.960317 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999746 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999746 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 618874541 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 618874541 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 895737439 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 895737439 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 895737439 # number of overall hits -system.cpu.dcache.overall_hits::total 895737439 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits +system.cpu.dcache.overall_hits::total 895737438 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 1533653 # n system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses system.cpu.dcache.overall_misses::total 1533653 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79725982000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79725982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79650886000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79650886000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 3794826000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 3794826000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83520808000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83520808000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83520808000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 620335414 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 620335414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 83445712000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83445712000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83445712000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83445712000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 897271092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 897271092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 897271092 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 897271092 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54574.204602 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54522.799723 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54522.799723 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52141.055235 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54458.738711 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54409.773267 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54409.773267 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54409.773267 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107259 # number of writebacks -system.cpu.dcache.writebacks::total 107259 # number of writebacks +system.cpu.dcache.writebacks::writebacks 109047 # number of writebacks +system.cpu.dcache.writebacks::total 109047 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75343363000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75343363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75268267000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75268267000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 78919849000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78919849000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 78919849000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 78844753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 78844753000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 78844753000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51574.204602 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51522.799723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51522.799723 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51458.738711 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51409.773267 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51409.773267 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1478755 # number of replacements -system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use -system.cpu.l2cache.total_refs 75453 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1478696 # number of replacements +system.cpu.l2cache.tagsinuse 32689.777876 # Cycle average of tags in use +system.cpu.l2cache.total_refs 77413 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 1511439 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.051218 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 3041.423322 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 32.598415 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28860.822381 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.092817 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000995 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.880762 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.974574 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 3194.588699 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 32.929350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 29462.259827 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.097491 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001005 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.899117 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997613 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 17546 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 49593 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 67139 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 107259 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 107259 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 51381 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 68927 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109047 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109047 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 6687 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 6687 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 17546 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 56280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 73826 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 58068 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 75614 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 17546 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 56280 # number of overall hits -system.cpu.l2cache.overall_hits::total 73826 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 58068 # number of overall hits +system.cpu.l2cache.overall_hits::total 75614 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2257 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1411280 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1413537 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1409492 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1411749 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66093 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 2257 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1477373 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1479630 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1475585 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1477842 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 2257 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1477373 # number of overall misses -system.cpu.l2cache.overall_misses::total 1479630 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1475585 # number of overall misses +system.cpu.l2cache.overall_misses::total 1477842 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 117364000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73386560000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 73503924000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73293584000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 73410948000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436836000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 117364000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 76823396000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 76940760000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 76730420000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 76847784000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 117364000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 76823396000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 76940760000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 76730420000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 76847784000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1460873 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1480676 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 107259 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 107259 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109047 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109047 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72780 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72780 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 19803 # number of demand (read+write) accesses @@ -347,16 +347,16 @@ system.cpu.l2cache.overall_accesses::cpu.inst 19803 system.cpu.l2cache.overall_accesses::cpu.data 1533653 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 1553456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113973 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966052 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.954657 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964829 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.953449 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113973 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963303 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.952476 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.962137 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.951325 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113973 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963303 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.952476 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.962137 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.951325 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -379,38 +379,38 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks system.cpu.l2cache.writebacks::total 66099 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2257 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411280 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1413537 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1409492 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1411749 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66093 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 2257 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1477373 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1479630 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1475585 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1477842 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 2257 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1477373 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1479630 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1475585 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1477842 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56451200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56541480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56379680000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56469960000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59094920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 59185200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59023400000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 59113680000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59094920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 59185200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59023400000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 59113680000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.954657 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964829 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.953449 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908120 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.952476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.951325 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963303 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.952476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962137 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.951325 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |