diff options
Diffstat (limited to 'tests/long/se/40.perlbmk')
8 files changed, 0 insertions, 5595 deletions
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 7428b23f1..e69de29bb 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,800 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.504258 # Number of seconds simulated -sim_ticks 504258263000 # Number of ticks simulated -final_tick 504258263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 386643 # Simulator instruction rate (inst/s) -host_op_rate 386643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209915985 # Simulator tick rate (ticks/s) -host_mem_usage 262852 # Number of bytes of host memory used -host_seconds 2402.19 # Real time elapsed on the host -sim_insts 928789150 # Number of instructions simulated -sim_ops 928789150 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 185088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520000 # Number of bytes read from this memory -system.physmem.bytes_read::total 18705088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2892 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289375 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292267 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 367050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36727212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37094262 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 367050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 367050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8463346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8463346 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8463346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 367050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36727212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 45557607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292267 # Number of read requests accepted -system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292267 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18685248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266176 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18705088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18033 # Per bank write bursts -system.physmem.perBankRdBursts::1 18363 # Per bank write bursts -system.physmem.perBankRdBursts::2 18394 # Per bank write bursts -system.physmem.perBankRdBursts::3 18341 # Per bank write bursts -system.physmem.perBankRdBursts::4 18245 # Per bank write bursts -system.physmem.perBankRdBursts::5 18249 # Per bank write bursts -system.physmem.perBankRdBursts::6 18313 # Per bank write bursts -system.physmem.perBankRdBursts::7 18290 # Per bank write bursts -system.physmem.perBankRdBursts::8 18231 # Per bank write bursts -system.physmem.perBankRdBursts::9 18232 # Per bank write bursts -system.physmem.perBankRdBursts::10 18229 # Per bank write bursts -system.physmem.perBankRdBursts::11 18376 # Per bank write bursts -system.physmem.perBankRdBursts::12 18272 # Per bank write bursts -system.physmem.perBankRdBursts::13 18137 # Per bank write bursts -system.physmem.perBankRdBursts::14 18064 # Per bank write bursts -system.physmem.perBankRdBursts::15 18188 # Per bank write bursts -system.physmem.perBankWrBursts::0 4125 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4223 # Per bank write bursts -system.physmem.perBankWrBursts::3 4160 # Per bank write bursts -system.physmem.perBankWrBursts::4 4142 # Per bank write bursts -system.physmem.perBankWrBursts::5 4099 # Per bank write bursts -system.physmem.perBankWrBursts::6 4262 # Per bank write bursts -system.physmem.perBankWrBursts::7 4226 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4183 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 504258181000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292267 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 222.473443 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.311324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 268.647767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 37345 36.20% 36.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43741 42.40% 78.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9241 8.96% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 735 0.71% 88.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1396 1.35% 89.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1157 1.12% 90.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 662 0.64% 91.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 564 0.55% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8314 8.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103155 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.893801 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.549322 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 747.524050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.463077 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.442287 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.845052 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3113 76.88% 76.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 933 23.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads -system.physmem.totQLat 3567632750 # Total ticks spent queuing -system.physmem.totMemAccLat 9041826500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12219.72 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30969.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 37.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 37.09 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.46 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.36 # Data bus utilization in percentage -system.physmem.busUtilRead 0.29 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing -system.physmem.readRowHits 203404 # Number of row buffer hits during reads -system.physmem.writeRowHits 52048 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes -system.physmem.avgGap 1404814.55 # Average gap between requests -system.physmem.pageHitRate 71.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 388939320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 212218875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140243000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 104730111945 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 210683510250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 350306824590 # Total energy per rank (pJ) -system.physmem_0.averagePower 694.703966 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 349825620000 # Time in different power states -system.physmem_0.memoryStateTime::REF 16838120000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 137589656250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 390829320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 213250125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136538000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215511840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 32935362720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 105447215835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 210054471750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 350393179590 # Total energy per rank (pJ) -system.physmem_1.averagePower 694.875219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 348773258750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16838120000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 138643034750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 123840342 # Number of BP lookups -system.cpu.branchPred.condPredicted 79869322 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 685088 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102061444 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68186680 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.809441 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691358 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9446 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14052117 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14048642 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3475 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11780 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237538322 # DTB read hits -system.cpu.dtb.read_misses 198467 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736789 # DTB read accesses -system.cpu.dtb.write_hits 98305180 # DTB write hits -system.cpu.dtb.write_misses 7178 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312358 # DTB write accesses -system.cpu.dtb.data_hits 335843502 # DTB hits -system.cpu.dtb.data_misses 205645 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336049147 # DTB accesses -system.cpu.itb.fetch_hits 285763790 # ITB hits -system.cpu.itb.fetch_misses 119 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 285763909 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1008516526 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928789150 # Number of instructions committed -system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 316849 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.085840 # CPI: cycles per instruction -system.cpu.ipc 0.920946 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction -system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::MemRead 237705247 25.59% 89.42% # Class of committed instruction -system.cpu.op_class_0::MemWrite 98308071 10.58% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 957154131 # Number of cycles that the object actually ticked -system.cpu.idleCycles 51362395 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 776530 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.342308 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 321596153 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 411.972126 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 901583500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.342308 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999107 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999107 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 956 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1398 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1472 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 645671096 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 645671096 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 223432106 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 223432106 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 321596153 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 321596153 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 321596153 # number of overall hits -system.cpu.dcache.overall_hits::total 321596153 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses -system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25457059500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25457059500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10110916000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10110916000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35567975500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35567975500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35567975500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35567975500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 224144035 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 224144035 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 322445235 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 322445235 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 322445235 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 322445235 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003176 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41889.918170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41889.918170 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88489 # number of writebacks -system.cpu.dcache.writebacks::total 88489 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68456 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68456 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68456 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68456 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711615 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711615 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780626 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24738054000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24738054000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5071007000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5071007000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29809061000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29809061000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29809061000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29809061000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003175 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003175 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002421 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002421 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002421 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34763.255412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34763.255412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73481.140688 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080 # average overall mshr miss latency -system.cpu.icache.tags.replacements 10567 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.158478 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 285751480 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12309 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23214.841173 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.158478 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823320 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823320 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 571539889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 571539889 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 285751480 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285751480 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285751480 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285751480 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285751480 # number of overall hits -system.cpu.icache.overall_hits::total 285751480 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12310 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12310 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12310 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12310 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12310 # number of overall misses -system.cpu.icache.overall_misses::total 12310 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 352350500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 352350500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 352350500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 352350500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 352350500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 352350500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285763790 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285763790 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285763790 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285763790 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285763790 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285763790 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28623.111292 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28623.111292 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28623.111292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28623.111292 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10567 # number of writebacks -system.cpu.icache.writebacks::total 10567 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12310 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12310 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12310 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12310 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12310 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12310 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 340041500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 340041500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 340041500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 340041500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 340041500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 340041500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27623.192526 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27623.192526 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 259940 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32579.649991 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218214 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292676 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.162330 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2630.640415 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.297977 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29869.711599 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.080281 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002420 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.911551 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994252 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 305 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2976 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29021 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13001951 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13001951 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 88489 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88489 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10567 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10567 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9417 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 9417 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488885 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488885 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9417 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491251 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 500668 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9417 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491251 # number of overall hits -system.cpu.l2cache.overall_hits::total 500668 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2893 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2893 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222730 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222730 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2893 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289375 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292268 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2893 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289375 # number of overall misses -system.cpu.l2cache.overall_misses::total 292268 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942620000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4942620000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 222699500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 222699500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18537323500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18537323500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 222699500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23479943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23702643000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 222699500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23479943500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23702643000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88489 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88489 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10567 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10567 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12310 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12310 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711615 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711615 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12310 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780626 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792936 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12310 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780626 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792936 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235012 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235012 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312992 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312992 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235012 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370696 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.368590 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235012 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370696 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.368590 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74163.403106 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74163.403106 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76978.741791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76978.741791 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83227.780272 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83227.780272 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76978.741791 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81140.193521 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81099.001601 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76978.741791 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81140.193521 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81099.001601 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2893 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2893 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222730 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222730 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2893 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289375 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292268 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2893 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289375 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292268 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4276170000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4276170000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193779500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193779500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16310023500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16310023500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193779500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20586193500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20779973000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193779500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20586193500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20779973000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235012 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312992 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312992 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368590 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235012 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370696 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368590 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64163.403106 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580033 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787097 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2081 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2081 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 723924 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155172 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881298 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12310 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35186 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2372968 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1464064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55623360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57087424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259940 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1052876 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001976 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044414 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050795 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2081 0.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052876 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889072500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18463500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170939499 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225622 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191176 # Transaction distribution -system.membus.trans_dist::ReadExReq 66645 # Transaction distribution -system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225622 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842393 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842393 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22972800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22972800 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 550126 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 550126 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 550126 # Request fanout histogram -system.membus.reqLayer0.occupancy 918516000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556053500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 80519f72d..e69de29bb 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,1055 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.174766 # Number of seconds simulated -sim_ticks 174766258500 # Number of ticks simulated -final_tick 174766258500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 294264 # Simulator instruction rate (inst/s) -host_op_rate 294264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61050004 # Simulator tick rate (ticks/s) -host_mem_usage 263360 # Number of bytes of host memory used -host_seconds 2862.67 # Real time elapsed on the host -sim_insts 842382029 # Number of instructions simulated -sim_ops 842382029 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 174016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18524608 # Number of bytes read from this memory -system.physmem.bytes_read::total 18698624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 174016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 174016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2719 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292166 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 995707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 105996479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 106992186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 995707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 995707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24419176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24419176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24419176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 995707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 105996479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 131411362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292166 # Number of read requests accepted -system.physmem.writeReqs 66682 # Number of write requests accepted -system.physmem.readBursts 292166 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18677824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20800 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265792 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18698624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 325 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18006 # Per bank write bursts -system.physmem.perBankRdBursts::1 18334 # Per bank write bursts -system.physmem.perBankRdBursts::2 18382 # Per bank write bursts -system.physmem.perBankRdBursts::3 18340 # Per bank write bursts -system.physmem.perBankRdBursts::4 18235 # Per bank write bursts -system.physmem.perBankRdBursts::5 18233 # Per bank write bursts -system.physmem.perBankRdBursts::6 18311 # Per bank write bursts -system.physmem.perBankRdBursts::7 18302 # Per bank write bursts -system.physmem.perBankRdBursts::8 18233 # Per bank write bursts -system.physmem.perBankRdBursts::9 18227 # Per bank write bursts -system.physmem.perBankRdBursts::10 18220 # Per bank write bursts -system.physmem.perBankRdBursts::11 18388 # Per bank write bursts -system.physmem.perBankRdBursts::12 18256 # Per bank write bursts -system.physmem.perBankRdBursts::13 18125 # Per bank write bursts -system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18192 # Per bank write bursts -system.physmem.perBankWrBursts::0 4125 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4223 # Per bank write bursts -system.physmem.perBankWrBursts::3 4160 # Per bank write bursts -system.physmem.perBankWrBursts::4 4142 # Per bank write bursts -system.physmem.perBankWrBursts::5 4099 # Per bank write bursts -system.physmem.perBankWrBursts::6 4261 # Per bank write bursts -system.physmem.perBankWrBursts::7 4226 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts -system.physmem.perBankWrBursts::10 4148 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 174766169000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292166 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46521 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.414911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 153.615169 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 282.362382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 31544 32.64% 32.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41851 43.31% 75.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11279 11.67% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 407 0.42% 88.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 349 0.36% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 422 0.44% 88.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 656 0.68% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1511 1.56% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8609 8.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96628 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.731557 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.520071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 729.773377 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4045 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.445349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.425120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.833815 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3151 77.74% 77.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 77.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 896 22.11% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads -system.physmem.totQLat 3659606000 # Total ticks spent queuing -system.physmem.totMemAccLat 9131624750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12539.73 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31289.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 106.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 24.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 106.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 24.42 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.83 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.19 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 209802 # Number of row buffer hits during reads -system.physmem.writeRowHits 52054 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes -system.physmem.avgGap 487020.04 # Average gap between requests -system.physmem.pageHitRate 73.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 364626360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 198952875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139346000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216432000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63677219400 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 49000374750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 126011580585 # Total energy per rank (pJ) -system.physmem_0.averagePower 721.044153 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81102514500 # Time in different power states -system.physmem_0.memoryStateTime::REF 5835700000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 87824440500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 365752800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 199567500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136265000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215479440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 11414629200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 63630052470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 49041749250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 126003495660 # Total energy per rank (pJ) -system.physmem_1.averagePower 720.997890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81165303250 # Time in different power states -system.physmem_1.memoryStateTime::REF 5835700000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 87762226750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 129267026 # Number of BP lookups -system.cpu.branchPred.condPredicted 83048450 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 145225 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93510959 # Number of BTB lookups -system.cpu.branchPred.BTBHits 70602364 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 75.501700 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19428078 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1137 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14846480 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14819636 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 26844 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 243602185 # DTB read hits -system.cpu.dtb.read_misses 267667 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 243869852 # DTB read accesses -system.cpu.dtb.write_hits 101634527 # DTB write hits -system.cpu.dtb.write_misses 39608 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 101674135 # DTB write accesses -system.cpu.dtb.data_hits 345236712 # DTB hits -system.cpu.dtb.data_misses 307275 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 345543987 # DTB accesses -system.cpu.itb.fetch_hits 116217608 # ITB hits -system.cpu.itb.fetch_misses 1594 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 116219202 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 349532518 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 116536228 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973715519 # Number of instructions fetch has processed -system.cpu.fetch.Branches 129267026 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 104850078 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 232359516 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 756618 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13025 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 116217608 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 170932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 349287938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.787716 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.090069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 152570668 43.68% 43.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 21852908 6.26% 49.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15618674 4.47% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24569577 7.03% 61.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 38589117 11.05% 72.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15690770 4.49% 76.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 12536709 3.59% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3990160 1.14% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63869355 18.29% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 349287938 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369828 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.785765 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85729217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 85771889 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158922951 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18492364 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371517 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11932000 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7014 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 968678626 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25475 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371517 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93246352 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12124008 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14162 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 169252951 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 74278948 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 966798475 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 812 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25198716 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40147884 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7202949 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 666569389 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1151537527 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114498375 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 37039151 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27602231 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 86 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 87958062 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 245057270 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 102624029 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35348443 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4751860 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 877942600 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 76 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 871652294 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 10599 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35560646 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10943510 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 349287938 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.495512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.135180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 75519507 21.62% 21.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 61352705 17.57% 39.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 57497159 16.46% 55.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51075272 14.62% 70.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45041028 12.90% 83.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20641156 5.91% 89.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18147367 5.20% 94.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10284591 2.94% 97.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9729153 2.79% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 349287938 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3589516 19.40% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11788826 63.72% 83.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3123532 16.88% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 505111201 57.95% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7850 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13300877 1.53% 59.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826560 0.44% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339807 0.38% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 244259904 28.02% 88.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 101804815 11.68% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 871652294 # Type of FU issued -system.cpu.iq.rate 2.493766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18501874 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021226 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2041816444 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 876761594 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 835992532 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69288555 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36778587 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34169821 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855051836 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35101056 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65597329 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7546673 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37094 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4322829 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2714 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4439 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371517 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4003286 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 617757 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 966013425 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16652 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 245057270 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 102624029 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 76 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 538427 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 92920 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37094 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128203 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 15937 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 144140 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 871030251 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 243869972 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 622043 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88070749 # number of nop insts executed -system.cpu.iew.exec_refs 345544428 # number of memory reference insts executed -system.cpu.iew.exec_branches 127159642 # Number of branches executed -system.cpu.iew.exec_stores 101674456 # Number of stores executed -system.cpu.iew.exec_rate 2.491986 # Inst execution rate -system.cpu.iew.wb_sent 870623887 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 870162353 # cumulative count of insts written-back -system.cpu.iew.wb_producers 525000957 # num instructions producing a value -system.cpu.iew.wb_consumers 821946847 # num instructions consuming a value -system.cpu.iew.wb_rate 2.489503 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.638729 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 31811556 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 138434 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 345159794 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.690312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.060061 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 109423104 31.70% 31.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 81928646 23.74% 55.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 29947333 8.68% 64.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19779535 5.73% 69.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17819278 5.16% 75.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7961935 2.31% 77.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3040960 0.88% 78.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3978860 1.15% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71280143 20.65% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 345159794 # Number of insts commited each cycle -system.cpu.commit.committedInsts 928587628 # Number of instructions committed -system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 335811797 # Number of memory references committed -system.cpu.commit.loads 237510597 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 123111018 # Number of branches committed -system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions. -system.cpu.commit.int_insts 821934723 # Number of committed integer instructions. -system.cpu.commit.function_calls 18524163 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 237510597 25.58% 89.41% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 71280143 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1231657697 # The number of ROB reads -system.cpu.rob.rob_writes 1924928764 # The number of ROB writes -system.cpu.timesIdled 3152 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 244580 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 842382029 # Number of Instructions Simulated -system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.414933 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.414933 # CPI: Total CPI of All Threads -system.cpu.ipc 2.410025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.410025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1104176449 # number of integer regfile reads -system.cpu.int_regfile_writes 635594518 # number of integer regfile writes -system.cpu.fp_regfile_reads 36406853 # number of floating regfile reads -system.cpu.fp_regfile_writes 24680531 # number of floating regfile writes -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 776668 # number of replacements -system.cpu.dcache.tags.tagsinuse 4091.068449 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 273851879 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780764 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 350.748599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 371412500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4091.068449 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998796 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 421 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 553379090 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 553379090 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 176443243 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 176443243 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408623 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408623 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 273851866 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 273851866 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 273851866 # number of overall hits -system.cpu.dcache.overall_hits::total 273851866 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1554707 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1554707 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 892577 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 892577 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2447284 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2447284 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2447284 # number of overall misses -system.cpu.dcache.overall_misses::total 2447284 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83708553000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83708553000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61914869831 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61914869831 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145623422831 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145623422831 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145623422831 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145623422831 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177997950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177997950 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 276299150 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 276299150 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 276299150 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 276299150 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008734 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009080 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009080 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59504.096309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59504.096309 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22333 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 68716 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.360231 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 132.400771 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88604 # number of writebacks -system.cpu.dcache.writebacks::total 88604 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842561 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 842561 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 823959 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 823959 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1666520 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1666520 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1666520 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1666520 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712146 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712146 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68618 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68618 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780764 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780764 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780764 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780764 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24226479500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24226479500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5661245497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5661245497 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29887724997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29887724997 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29887724997 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29887724997 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282 # average overall mshr miss latency -system.cpu.icache.tags.replacements 4617 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.904441 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 116209358 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18381.739639 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.904441 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1541 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 232441538 # Number of tag accesses -system.cpu.icache.tags.data_accesses 232441538 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 116209358 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 116209358 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 116209358 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 116209358 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 116209358 # number of overall hits -system.cpu.icache.overall_hits::total 116209358 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8250 # number of overall misses -system.cpu.icache.overall_misses::total 8250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 354158499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 354158499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 354158499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 354158499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 354158499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 354158499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 116217608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 116217608 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 116217608 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 116217608 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 116217608 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 116217608 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42928.302909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42928.302909 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42928.302909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42928.302909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42928.302909 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 738 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 61.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4617 # number of writebacks -system.cpu.icache.writebacks::total 4617 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1927 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1927 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1927 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1927 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1927 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1927 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6323 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6323 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6323 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6323 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6323 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6323 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 263974500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 263974500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 263974500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 263974500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 263974500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 263974500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41748.299858 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41748.299858 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 259794 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32576.626048 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207042 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292532 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.126188 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2634.083249 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.428877 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29874.113923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.080386 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002088 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.911686 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994160 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32738 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 211 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 859 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8617 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 22757 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12908126 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12908126 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 88604 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88604 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4617 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4617 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3603 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3603 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489324 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 489324 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3603 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491317 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 494920 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3603 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491317 # number of overall hits -system.cpu.l2cache.overall_hits::total 494920 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66625 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66625 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2720 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2720 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222822 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222822 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2720 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289447 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292167 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2720 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289447 # number of overall misses -system.cpu.l2cache.overall_misses::total 292167 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5537092500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5537092500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 216561000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 216561000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18014278000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18014278000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 216561000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23551370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23767931500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 216561000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23551370500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23767931500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88604 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88604 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4617 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4617 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68618 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68618 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6323 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712146 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712146 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6323 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780764 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 787087 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6323 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780764 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 787087 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.970955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.970955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.430176 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.430176 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312888 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312888 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430176 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370723 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.371200 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430176 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370723 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.371200 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83108.330206 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83108.330206 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79618.014706 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79618.014706 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80846.047518 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80846.047518 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79618.014706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81366.780447 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81350.499885 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79618.014706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81366.780447 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81350.499885 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66682 # number of writebacks -system.cpu.l2cache.writebacks::total 66682 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66625 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66625 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2720 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2720 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222822 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2720 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292167 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2720 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289447 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292167 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4870842500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4870842500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 189371000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 189371000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15786058000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15786058000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 189371000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20656900500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20846271500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 189371000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20656900500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20846271500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970955 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.430176 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312888 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312888 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.371200 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430176 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370723 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.371200 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73108.330206 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73108.330206 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69621.691176 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69621.691176 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70846.047518 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70846.047518 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1568372 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781285 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2003 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2003 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 718468 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712146 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17262 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338196 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2355458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56339648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259794 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1046881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001913 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043699 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1044878 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2003 0.19% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1046881 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877407000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9483000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171146499 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225541 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution -system.membus.trans_dist::CleanEvict 191110 # Transaction distribution -system.membus.trans_dist::ReadExReq 66625 # Transaction distribution -system.membus.trans_dist::ReadExResp 66625 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225541 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842124 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842124 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22966272 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 549958 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549958 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549958 # Request fanout histogram -system.membus.reqLayer0.occupancy 877671500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551270000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index f8aa50083..e69de29bb 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.464395 # Number of seconds simulated -sim_ticks 464394627000 # Number of ticks simulated -final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2843750 # Simulator instruction rate (inst/s) -host_op_rate 2843750 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1422183537 # Simulator tick rate (ticks/s) -host_mem_usage 289848 # Number of bytes of host memory used -host_seconds 326.54 # Real time elapsed on the host -sim_insts 928587629 # Number of instructions simulated -sim_ops 928587629 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory -system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory -system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution -system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution -system.membus.trans_dist::WriteReq 98301200 # Transaction distribution -system.membus.trans_dist::WriteResp 98301200 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734452 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441624 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 335811797 26.55% 26.55% # Request fanout histogram -system.membus.snoop_fanout::1 928789150 73.45% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1264600947 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237510597 # DTB read hits -system.cpu.dtb.read_misses 194650 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237705247 # DTB read accesses -system.cpu.dtb.write_hits 98301200 # DTB write hits -system.cpu.dtb.write_misses 6871 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98308071 # DTB write accesses -system.cpu.dtb.data_hits 335811797 # DTB hits -system.cpu.dtb.data_misses 201521 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336013318 # DTB accesses -system.cpu.itb.fetch_hits 928789150 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 928789255 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 928789255 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928587629 # Number of instructions committed -system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses -system.cpu.num_func_calls 37048314 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls -system.cpu.num_int_insts 822136244 # number of integer instructions -system.cpu.num_fp_insts 33439365 # number of float instructions -system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read -system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read -system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written -system.cpu.num_mem_refs 336013318 # number of memory refs -system.cpu.num_load_insts 237705247 # Number of load instructions -system.cpu.num_store_insts 98308071 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 928789255 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 123111018 # Number of branches fetched -system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction -system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction -system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction -system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 928789150 # Class of executed instruction - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index fa790fe39..e69de29bb 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,548 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.288319 # Number of seconds simulated -sim_ticks 1288319411500 # Number of ticks simulated -final_tick 1288319411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1388114 # Simulator instruction rate (inst/s) -host_op_rate 1388114 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1925865262 # Simulator tick rate (ticks/s) -host_mem_usage 260804 # Number of bytes of host memory used -host_seconds 668.96 # Real time elapsed on the host -sim_insts 928587629 # Number of instructions simulated -sim_ops 928587629 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18511872 # Number of bytes read from this memory -system.physmem.bytes_read::total 18648896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289248 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291389 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14369008 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14475367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3312619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3312619 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3312619 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14369008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787986 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237510597 # DTB read hits -system.cpu.dtb.read_misses 194650 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237705247 # DTB read accesses -system.cpu.dtb.write_hits 98301200 # DTB write hits -system.cpu.dtb.write_misses 6871 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98308071 # DTB write accesses -system.cpu.dtb.data_hits 335811797 # DTB hits -system.cpu.dtb.data_misses 201521 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336013318 # DTB accesses -system.cpu.itb.fetch_hits 928789151 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 928789256 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2576638823 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928587629 # Number of instructions committed -system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses -system.cpu.num_func_calls 37048314 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls -system.cpu.num_int_insts 822136244 # number of integer instructions -system.cpu.num_fp_insts 33439365 # number of float instructions -system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read -system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read -system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written -system.cpu.num_mem_refs 336013318 # number of memory refs -system.cpu.num_load_insts 237705247 # Number of load instructions -system.cpu.num_store_insts 98308071 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2576638823 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 123111018 # Number of branches fetched -system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction -system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction -system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction -system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 928789150 # Class of executed instruction -system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.180330 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1104319500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.180330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999556 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999556 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits -system.cpu.dcache.overall_hits::total 335031269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses -system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20157098000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20157098000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4162936000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4162936000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24320034000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24320034000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24320034000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24320034000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28329.868421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28329.868421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60320.166923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60320.166923 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31158.438903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31158.438903 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31158.438903 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88866 # number of writebacks -system.cpu.dcache.writebacks::total 88866 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19445584000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19445584000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4093922000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4093922000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23539506000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23539506000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23539506000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23539506000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27329.868421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27329.868421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59320.166923 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59320.166923 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30158.438903 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30158.438903 # average overall mshr miss latency -system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.418872 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.418872 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719931 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits -system.cpu.icache.overall_hits::total 928782983 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses -system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 185126500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 185126500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 185126500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 185126500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 185126500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 185126500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30014.023995 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30014.023995 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30014.023995 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30014.023995 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30014.023995 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4618 # number of writebacks -system.cpu.icache.writebacks::total 4618 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 178958500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 178958500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 178958500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 178958500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 178958500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 178958500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29014.023995 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29014.023995 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29014.023995 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29014.023995 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 258847 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32654.651136 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1207020 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291581 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.139570 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2500.518191 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.895472 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30106.237473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076310 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001462 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.918769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32734 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31154 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998962 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12902563 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12902563 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 88866 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88866 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488914 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488914 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491280 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495307 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491280 # number of overall hits -system.cpu.l2cache.overall_hits::total 495307 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222600 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222600 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289248 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291389 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289248 # number of overall misses -system.cpu.l2cache.overall_misses::total 291389 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3965557000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3965557000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 127415500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 127415500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13244711500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13244711500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 127415500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17210268500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17337684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 127415500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17210268500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17337684000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88866 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88866 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312854 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312854 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370580 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370396 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370580 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370396 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.051662 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.051662 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59500.132126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59512.143858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.043216 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59500.132126 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222600 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222600 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289248 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289248 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3299077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3299077000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 106005500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 106005500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11018711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11018711500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106005500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14317788500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14423794000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106005500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14317788500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14423794000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312854 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312854 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370396 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370396 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.051662 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.051662 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49512.143858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.043216 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.132126 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1718 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1718 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155549 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55641216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56331520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258847 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1045543 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001643 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.040503 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1043825 99.84% 99.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1718 0.16% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1045543 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877357000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 224741 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190447 # Transaction distribution -system.membus.trans_dist::ReadExReq 66648 # Transaction distribution -system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224741 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839908 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22916608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22916608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 548519 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 548519 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 548519 # Request fanout histogram -system.membus.reqLayer0.occupancy 815264000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456945000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index b04619cac..e69de29bb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,906 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.489946 # Number of seconds simulated -sim_ticks 489945697500 # Number of ticks simulated -final_tick 489945697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235921 # Simulator instruction rate (inst/s) -host_op_rate 290449 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 180421993 # Simulator tick rate (ticks/s) -host_mem_usage 280028 # Number of bytes of host memory used -host_seconds 2715.55 # Real time elapsed on the host -sim_insts 640655085 # Number of instructions simulated -sim_ops 788730744 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 163712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18473856 # Number of bytes read from this memory -system.physmem.bytes_read::total 18637568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 163712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 163712 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2558 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288654 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291212 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 334143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 37705926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 38040069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 334143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 334143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8634165 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8634165 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8634165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 334143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 37705926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 46674234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291212 # Number of read requests accepted -system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291212 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18637568 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18282 # Per bank write bursts -system.physmem.perBankRdBursts::1 18130 # Per bank write bursts -system.physmem.perBankRdBursts::2 18217 # Per bank write bursts -system.physmem.perBankRdBursts::3 18178 # Per bank write bursts -system.physmem.perBankRdBursts::4 18288 # Per bank write bursts -system.physmem.perBankRdBursts::5 18411 # Per bank write bursts -system.physmem.perBankRdBursts::6 18177 # Per bank write bursts -system.physmem.perBankRdBursts::7 17990 # Per bank write bursts -system.physmem.perBankRdBursts::8 18028 # Per bank write bursts -system.physmem.perBankRdBursts::9 18056 # Per bank write bursts -system.physmem.perBankRdBursts::10 18107 # Per bank write bursts -system.physmem.perBankRdBursts::11 18202 # Per bank write bursts -system.physmem.perBankRdBursts::12 18216 # Per bank write bursts -system.physmem.perBankRdBursts::13 18274 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18258 # Per bank write bursts -system.physmem.perBankWrBursts::0 4171 # Per bank write bursts -system.physmem.perBankWrBursts::1 4099 # Per bank write bursts -system.physmem.perBankWrBursts::2 4134 # Per bank write bursts -system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4225 # Per bank write bursts -system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4173 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4095 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4138 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 489945603000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291212 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 110179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 207.337369 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 135.107709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.005441 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 44928 40.78% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43473 39.46% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9308 8.45% 88.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1919 1.74% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 694 0.63% 91.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 753 0.68% 91.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 467 0.42% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 575 0.52% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8062 7.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 110179 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.520538 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.272045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.481387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.449091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.428808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.834669 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3115 77.55% 77.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 902 22.45% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 3297540750 # Total ticks spent queuing -system.physmem.totMemAccLat 8751747000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11336.00 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30086.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 38.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 38.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.63 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.36 # Data bus utilization in percentage -system.physmem.busUtilRead 0.30 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.85 # Average write queue length when enqueuing -system.physmem.readRowHits 195161 # Number of row buffer hits during reads -system.physmem.writeRowHits 51618 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.09 # Row buffer hit rate for writes -system.physmem.avgGap 1371205.96 # Average gap between requests -system.physmem.pageHitRate 69.13 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 417417840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 227757750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136210400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215563680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 104435392590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 202355359500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 340788331200 # Total energy per rank (pJ) -system.physmem_0.averagePower 695.568361 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 335944764000 # Time in different power states -system.physmem_0.memoryStateTime::REF 16360240000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 137638069000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 415474920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 226697625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132396200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212608800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 32000629440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 104010891930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 202727728500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 340726427415 # Total energy per rank (pJ) -system.physmem_1.averagePower 695.442012 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 336564996750 # Time in different power states -system.physmem_1.memoryStateTime::REF 16360240000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 137017032000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 144591747 # Number of BP lookups -system.cpu.branchPred.condPredicted 96197702 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 97552 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 81370677 # Number of BTB lookups -system.cpu.branchPred.BTBHits 61978792 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 76.168461 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19276085 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1317 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 15994685 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 15989167 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5518 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 8032 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 979891395 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 640655085 # Number of instructions committed -system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 6653282 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529515 # CPI: cycles per instruction -system.cpu.ipc 0.653802 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction -system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction -system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction -system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 924243701 # Number of cycles that the object actually ticked -system.cpu.idleCycles 55647694 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778302 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.104499 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378448234 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782398 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.702967 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 792959500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.104499 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999049 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999049 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 971 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1499 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1413 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759382252 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759382252 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249619506 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249619506 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128813766 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813766 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378433272 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378433272 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378436756 # number of overall hits -system.cpu.dcache.overall_hits::total 378436756 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713841 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713841 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137711 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137711 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 851552 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851552 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851693 # number of overall misses -system.cpu.dcache.overall_misses::total 851693 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25188260500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25188260500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10109820000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10109820000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35298080500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35298080500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35298080500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35298080500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250333347 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250333347 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379284824 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379284824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379288449 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379288449 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41451.468025 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41444.605627 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88712 # number of writebacks -system.cpu.dcache.writebacks::total 88712 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 904 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 904 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68389 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68389 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69293 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69293 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69293 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69293 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712937 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712937 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782259 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782259 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782398 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782398 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24459771500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24459771500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5070040000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5070040000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29529811500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29529811500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29531599500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29531599500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372 # average overall mshr miss latency -system.cpu.icache.tags.replacements 24859 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.892625 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 252585994 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 26612 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9491.432211 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.892625 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836373 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836373 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1753 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1599 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.855957 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 505251826 # Number of tag accesses -system.cpu.icache.tags.data_accesses 505251826 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 252585994 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 252585994 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 252585994 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 252585994 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 252585994 # number of overall hits -system.cpu.icache.overall_hits::total 252585994 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 26613 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 26613 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 26613 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 26613 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 26613 # number of overall misses -system.cpu.icache.overall_misses::total 26613 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 516729500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 516729500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 516729500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 516729500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 516729500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 516729500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 252612607 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 252612607 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 252612607 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 252612607 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 252612607 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 252612607 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000105 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000105 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000105 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000105 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000105 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19416.431819 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19416.431819 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19416.431819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19416.431819 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 24859 # number of writebacks -system.cpu.icache.writebacks::total 24859 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26613 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 26613 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 26613 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 26613 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 26613 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 26613 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 490117500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 490117500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 490117500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 490117500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 490117500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 490117500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000105 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000105 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000105 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 258808 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32560.749490 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1247790 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291552 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.279820 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2632.544658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 88.421700 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.783132 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.080339 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002698 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.910638 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.993675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 326 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 28951 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 13231738 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 13231738 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 88712 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88712 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 23528 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 23528 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24049 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 24049 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490486 # 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number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2564 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288681 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291245 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2564 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288681 # number of overall misses -system.cpu.l2cache.overall_misses::total 291245 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4932129000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4932129000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 196405000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 196405000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18239788500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 18239788500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 196405000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23171917500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23368322500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 196405000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23171917500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23368322500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88712 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88712 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 23528 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 23528 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26613 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 26613 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 713076 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 713076 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 26613 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 782398 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 809011 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 26613 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 782398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 809011 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096344 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096344 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312155 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312155 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096344 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368970 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.360001 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096344 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368970 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.360001 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.333389 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.333389 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81943.431870 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81943.431870 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80235.961132 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks -system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 27 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 27 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2559 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2559 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222563 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222563 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2559 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288654 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291213 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2559 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288654 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291213 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4271219000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4271219000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 170500500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 170500500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16012410500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16012410500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170500500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20283629500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20454130000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170500500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20283629500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20454130000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096156 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312117 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312117 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359962 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096156 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368935 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359962 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1612172 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 803221 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3314 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 739688 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 154810 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24859 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 882300 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 26613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 713076 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78084 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343098 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2421182 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3294144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55751040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 59045184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258808 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1067819 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005072 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.071235 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1062418 99.49% 99.49% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5386 0.50% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1067819 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 919657000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 39920495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173610473 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225121 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190682 # Transaction distribution -system.membus.trans_dist::ReadExReq 66091 # Transaction distribution -system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225121 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839204 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839204 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22867840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22867840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 547992 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 547992 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 547992 # Request fanout histogram -system.membus.reqLayer0.occupancy 916865000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554037500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 2624c980a..e69de29bb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,1232 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.326731 # Number of seconds simulated -sim_ticks 326731324000 # Number of ticks simulated -final_tick 326731324000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 138534 # Simulator instruction rate (inst/s) -host_op_rate 170554 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70652444 # Simulator tick rate (ticks/s) -host_mem_usage 277336 # Number of bytes of host memory used -host_seconds 4624.49 # Real time elapsed on the host -sim_insts 640649299 # Number of instructions simulated -sim_ops 788724958 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 227072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47957824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12822400 # Number of bytes read from this memory -system.physmem.bytes_read::total 61007296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227072 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4245376 # Number of bytes written to this memory -system.physmem.bytes_written::total 4245376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3548 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 749341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 953239 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66334 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66334 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 694981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 146780613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 39244477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186720071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 694981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 694981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12993477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12993477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12993477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 694981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 146780613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 39244477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 199713548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 953240 # Number of read requests accepted -system.physmem.writeReqs 66334 # Number of write requests accepted -system.physmem.readBursts 953240 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66334 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 60987072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61007360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4245376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 64 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19685 # Per bank write bursts -system.physmem.perBankRdBursts::1 19287 # Per bank write bursts -system.physmem.perBankRdBursts::2 657567 # Per bank write bursts -system.physmem.perBankRdBursts::3 20052 # Per bank write bursts -system.physmem.perBankRdBursts::4 19480 # Per bank write bursts -system.physmem.perBankRdBursts::5 20770 # Per bank write bursts -system.physmem.perBankRdBursts::6 19386 # Per bank write bursts -system.physmem.perBankRdBursts::7 19760 # Per bank write bursts -system.physmem.perBankRdBursts::8 19321 # Per bank write bursts -system.physmem.perBankRdBursts::9 19768 # Per bank write bursts -system.physmem.perBankRdBursts::10 19303 # Per bank write bursts -system.physmem.perBankRdBursts::11 19444 # Per bank write bursts -system.physmem.perBankRdBursts::12 19433 # Per bank write bursts -system.physmem.perBankRdBursts::13 20871 # Per bank write bursts -system.physmem.perBankRdBursts::14 19269 # Per bank write bursts -system.physmem.perBankRdBursts::15 19527 # Per bank write bursts -system.physmem.perBankWrBursts::0 4288 # Per bank write bursts -system.physmem.perBankWrBursts::1 4110 # Per bank write bursts -system.physmem.perBankWrBursts::2 4140 # Per bank write bursts -system.physmem.perBankWrBursts::3 4154 # Per bank write bursts -system.physmem.perBankWrBursts::4 4242 # Per bank write bursts -system.physmem.perBankWrBursts::5 4232 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4095 # Per bank write bursts -system.physmem.perBankWrBursts::9 4095 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts -system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4146 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 326731313500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 953240 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66334 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 759877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 8005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3769 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1473 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 882 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3862 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 187141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.533437 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.264052 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 368.938471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 57976 30.98% 30.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60329 32.24% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15964 8.53% 71.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2811 1.50% 73.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2834 1.51% 74.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2850 1.52% 76.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2680 1.43% 77.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 20043 10.71% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21654 11.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 187141 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4039 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 232.424858 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.579593 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3031.486386 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 4013 99.36% 99.36% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.65% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 1 0.02% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 4 0.10% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.02% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::53248-57343 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::106496-110591 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::118784-122879 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4039 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4039 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.403318 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.369585 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.145225 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3419 84.65% 84.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.37% 85.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 455 11.27% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 68 1.68% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.64% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 15 0.37% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.37% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 7 0.17% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.22% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4039 # Writes before turning the bus around for reads -system.physmem.totQLat 12733277648 # Total ticks spent queuing -system.physmem.totMemAccLat 30600583898 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4764615000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13362.34 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32112.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 186.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 12.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 186.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 12.99 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.56 # Data bus utilization in percentage -system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.20 # Average write queue length when enqueuing -system.physmem.readRowHits 805882 # Number of row buffer hits during reads -system.physmem.writeRowHits 26140 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.44 # Row buffer hit rate for writes -system.physmem.avgGap 320458.66 # Average gap between requests -system.physmem.pageHitRate 81.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 905544360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 494096625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6208534800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216665280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 220053154905 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3007065000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 252225255690 # Total energy per rank (pJ) -system.physmem_0.averagePower 771.975754 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3732596290 # Time in different power states -system.physmem_0.memoryStateTime::REF 10910120000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 312084210210 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 509143320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 277806375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1223765400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212654160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 21340194720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86358123315 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 120283389750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 230205077040 # Total energy per rank (pJ) -system.physmem_1.averagePower 704.579541 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 199538723813 # Time in different power states -system.physmem_1.memoryStateTime::REF 10910120000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 116279470187 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 174663372 # Number of BP lookups -system.cpu.branchPred.condPredicted 119116658 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015834 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720842 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67756635 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.053810 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18785000 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716087 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16701520 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14567 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279491 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 653462649 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 34330546 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824287133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174663372 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103243155 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 614749504 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068361 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2074 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3172 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247743048 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 12728 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 653119493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.556506 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.252668 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 191049151 29.25% 29.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148339787 22.71% 51.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72947000 11.17% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240783555 36.87% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 653119493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.267289 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.261414 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75090408 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 234264663 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277765642 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61977614 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021166 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20809487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13114 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924578192 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11804661 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021166 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118033326 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 133536652 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207511 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 294559211 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102761627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906540244 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891569 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27986936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218724 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49336465 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 494906 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980929615 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4376071754 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001832293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457071 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106151385 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6850 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138811891 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271881167 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160584857 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6164108 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12154940 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899826382 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12579 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860025252 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216952 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111114003 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 248251839 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 653119493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.316796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093773 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 190460700 29.16% 29.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182404327 27.93% 57.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 175564310 26.88% 83.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 92270630 14.13% 98.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12417215 1.90% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2311 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 653119493 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66606660 24.62% 24.62% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18142 0.01% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.24% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.87% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 134118538 49.58% 74.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69109914 25.55% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413086253 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187655 0.60% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550149 0.30% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478193 1.33% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 266665790 31.01% 81.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 157232010 18.28% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860025252 # Type of FU issued -system.cpu.iq.rate 1.316105 # Inst issue rate -system.cpu.iq.fu_busy_cnt 270490143 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2595335329 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980330228 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820077465 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 57541763 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641547 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878664 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1098495276 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 32020119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13987051 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19640229 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 121 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18814 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31604361 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918936 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18556 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021166 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10589336 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 14351 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899849213 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271881167 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160584857 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6839 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 943 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11501 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18814 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295227 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290376 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850170088 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263374256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855164 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10252 # number of nop insts executed -system.cpu.iew.exec_refs 416063199 # number of memory reference insts executed -system.cpu.iew.exec_branches 143379422 # Number of branches executed -system.cpu.iew.exec_stores 152688943 # Number of stores executed -system.cpu.iew.exec_rate 1.301023 # Inst execution rate -system.cpu.iew.wb_sent 846292107 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844956129 # cumulative count of insts written-back -system.cpu.iew.wb_producers 487338276 # num instructions producing a value -system.cpu.iew.wb_consumers 808096579 # num instructions consuming a value -system.cpu.iew.wb_rate 1.293044 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.603069 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103168329 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002820 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 638538795 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.235211 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.072799 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 348204518 54.53% 54.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137237104 21.49% 76.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51340026 8.04% 84.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28219441 4.42% 88.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14379877 2.25% 90.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774087 2.31% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871873 1.23% 94.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561542 1.03% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29950327 4.69% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 638538795 # Number of insts commited each cycle -system.cpu.commit.committedInsts 640654411 # Number of instructions committed -system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 381221434 # Number of memory references committed -system.cpu.commit.loads 252240938 # Number of loads committed -system.cpu.commit.membars 5740 # Number of memory barriers committed -system.cpu.commit.branches 137364860 # Number of branches committed -system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions. -system.cpu.commit.int_insts 682251399 # Number of committed integer instructions. -system.cpu.commit.function_calls 19275340 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 385756794 48.91% 48.91% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29950327 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1500478116 # The number of ROB reads -system.cpu.rob.rob_writes 1798380886 # The number of ROB writes -system.cpu.timesIdled 9234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 343156 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 640649299 # Number of Instructions Simulated -system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.020001 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.020001 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980392 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980392 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868460109 # number of integer regfile reads -system.cpu.int_regfile_writes 500697086 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616061 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959483 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322370942 # number of cc regfile reads -system.cpu.cc_regfile_writes 369203387 # number of cc regfile writes -system.cpu.misc_regfile_reads 632347857 # number of misc regfile reads -system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756452 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.912722 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371048240 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756964 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.585813 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 268220000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.912722 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999830 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999830 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751744798 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751744798 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 243125245 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243125245 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906950 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906950 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5738 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5738 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371032195 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371032195 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371035352 # number of overall hits -system.cpu.dcache.overall_hits::total 371035352 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401911 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401911 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044527 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044527 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3446438 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3446438 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3447085 # number of overall misses -system.cpu.dcache.overall_misses::total 3447085 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 68215511500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 68215511500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10001211350 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10001211350 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 165500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 165500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 78216722850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 78216722850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 78216722850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 78216722850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245527156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245527156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3804 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374478633 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374478633 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374482437 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374482437 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008100 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008100 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009205 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009205 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.871066 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.871066 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22694.945579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22690.685855 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 351776 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4812 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 73.103907 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756452 # number of writebacks -system.cpu.dcache.writebacks::total 2756452 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 366436 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 366436 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323495 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323495 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 689931 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 689931 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 689931 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 689931 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 721032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 642 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756507 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2757149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2757149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 63009195000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 63009195000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5955069850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5955069850 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5660000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5660000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 68964264850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 68964264850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 68969924850 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 68969924850 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.008290 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005591 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168770 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168770 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007361 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007361 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007363 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8259.092315 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8259.092315 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8816.199377 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8816.199377 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917 # average overall mshr miss latency -system.cpu.icache.tags.replacements 1979880 # number of replacements -system.cpu.icache.tags.tagsinuse 510.626245 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 245759391 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1980390 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 124.096461 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 258109500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.626245 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497466609 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497466609 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 245759426 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 245759426 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 245759426 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 245759426 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 245759426 # number of overall hits -system.cpu.icache.overall_hits::total 245759426 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1983591 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1983591 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1983591 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1983591 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1983591 # number of overall misses -system.cpu.icache.overall_misses::total 1983591 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16128682925 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16128682925 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16128682925 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16128682925 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16128682925 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16128682925 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 247743017 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 247743017 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 247743017 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 247743017 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 247743017 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 247743017 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8131.052684 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8131.052684 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8131.052684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8131.052684 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8131.052684 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 75472 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2912 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.917582 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 15 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1979880 # number of writebacks -system.cpu.icache.writebacks::total 1979880 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1980577 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1980577 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1980577 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1980577 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1980577 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1980577 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15098139938 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15098139938 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15098139938 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15098139938 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15098139938 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15098139938 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007994 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007994 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007994 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007994 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7623.101721 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7623.101721 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7623.101721 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7623.101721 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350865 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355053 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 3664 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790051 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 301370 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16350.432681 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7222107 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 317734 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.730041 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 44242160500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9843.702780 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6506.729901 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.600812 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997951 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6334 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 10030 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1704 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4420 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2583 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6932 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.386597 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.612183 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 142338236 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 142338236 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 736314 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 736314 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3356496 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3356496 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 718501 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 718501 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1976843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1976843 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1287256 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1287256 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1976843 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2005757 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3982600 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1976843 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2005757 # number of overall hits -system.cpu.l2cache.overall_hits::total 3982600 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 185 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 185 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2346 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2346 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3550 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3550 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 748861 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 748861 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3550 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 751207 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 754757 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3550 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 751207 # number of overall misses -system.cpu.l2cache.overall_misses::total 754757 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 195074000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 195074000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 261372000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 261372000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 51585571000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 51585571000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 261372000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 51780645000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 52042017000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 261372000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 51780645000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 52042017000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 736314 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 736314 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3356496 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3356496 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 185 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 185 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1980393 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1980393 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2036117 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 2036117 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1980393 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756964 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 4737357 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1980393 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756964 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 4737357 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003255 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003255 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.001793 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.001793 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.367789 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.367789 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.001793 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.272476 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159320 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.001793 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.272476 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159320 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83151.747656 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83151.747656 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73625.915493 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73625.915493 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68885.375257 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68885.375257 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68952.016344 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73625.915493 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 2695 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 66334 # number of writebacks -system.cpu.l2cache.writebacks::total 66334 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 963 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 963 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 903 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 903 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 1866 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1867 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 1866 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1867 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 200438 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 200438 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 185 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 185 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1383 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1383 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3549 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3549 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 747958 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 747958 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3549 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 749341 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 752890 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3549 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 749341 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 200438 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 953328 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 16667426112 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2605000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2605000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 137246500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 137246500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 240029500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 240029500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 47054888500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 47054888500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 240029500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47192135000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 47432164500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 240029500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47192135000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16667426112 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 64099590612 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001919 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.001792 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367345 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367345 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.158926 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.001792 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.271799 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.201236 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9474058 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736544 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643707 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 759527 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116739 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 642788 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 4016692 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000018 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 986541 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036117 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5940848 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270750 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14211598 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253457344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352858624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606315968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1296784 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6034326 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.339099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.661177 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4630880 76.74% 76.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 760658 12.61% 89.35% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 642788 10.65% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6034326 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9473361000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2970865494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135548979 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 951856 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66334 # Transaction distribution -system.membus.trans_dist::CleanEvict 227102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 185 # Transaction distribution -system.membus.trans_dist::ReadExReq 1383 # Transaction distribution -system.membus.trans_dist::ReadExResp 1383 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 951857 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2200100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2200100 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65252672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65252672 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1246861 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1246861 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1246861 # Request fanout histogram -system.membus.reqLayer0.occupancy 1754485252 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5014122383 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index f8c904908..e69de29bb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -1,243 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.395727 # Number of seconds simulated -sim_ticks 395726778500 # Number of ticks simulated -final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1575908 # Simulator instruction rate (inst/s) -host_op_rate 1940150 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 973424664 # Simulator tick rate (ticks/s) -host_mem_usage 311080 # Number of bytes of host memory used -host_seconds 406.53 # Real time elapsed on the host -sim_insts 640654411 # Number of instructions simulated -sim_ops 788730070 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory -system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory -system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory -system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 791453558 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 640654411 # Number of instructions committed -system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses -system.cpu.num_func_calls 37261296 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls -system.cpu.num_int_insts 682251400 # number of integer instructions -system.cpu.num_fp_insts 24239771 # number of float instructions -system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read -system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written -system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read -system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read -system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written -system.cpu.num_mem_refs 381221435 # number of memory refs -system.cpu.num_load_insts 252240938 # Number of load instructions -system.cpu.num_store_insts 128980497 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364860 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction -system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction -system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730744 # Class of executed instruction -system.membus.trans_dist::ReadReq 893703778 # Transaction distribution -system.membus.trans_dist::ReadResp 893709517 # Transaction distribution -system.membus.trans_dist::WriteReq 128951477 # Transaction distribution -system.membus.trans_dist::WriteResp 128951477 # Transaction distribution -system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution -system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution -system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1022670353 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index c2f10176e..e69de29bb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,659 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.045756 # Number of seconds simulated -sim_ticks 1045756396500 # Number of ticks simulated -final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 744148 # Simulator instruction rate (inst/s) -host_op_rate 914231 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1217137628 # Simulator tick rate (ticks/s) -host_mem_usage 277972 # Number of bytes of host memory used -host_seconds 859.19 # Real time elapsed on the host -sim_insts 639366787 # Number of instructions simulated -sim_ops 785501035 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470976 # Number of bytes read from this memory -system.physmem.bytes_read::total 18583552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory -system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288609 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290368 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 107650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17662790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17770441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4045179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045179 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4045179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17662790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21815620 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2091512793 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 639366787 # Number of instructions committed -system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses -system.cpu.num_func_calls 37261296 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls -system.cpu.num_int_insts 682251400 # number of integer instructions -system.cpu.num_fp_insts 24239771 # number of float instructions -system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read -system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written -system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read -system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written -system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read -system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written -system.cpu.num_mem_refs 381221435 # number of memory refs -system.cpu.num_load_insts 252240938 # Number of load instructions -system.cpu.num_store_insts 128980497 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2091512792.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 137364860 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction -system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction -system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction -system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 788730744 # Class of executed instruction -system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.549761 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1041808500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.549761 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999402 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1037 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits -system.cpu.dcache.overall_hits::total 378498833 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses -system.cpu.dcache.overall_misses::total 782143 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20169396000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20169396000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4139811500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4139811500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24309207500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24309207500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24309207500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24309207500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28300.734831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28300.734831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59717.719949 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59717.719949 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31085.784088 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31085.784088 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31080.259620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31080.259620 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88995 # number of writebacks -system.cpu.dcache.writebacks::total 88995 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19456669000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19456669000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4070488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4070488500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1766000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1766000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23527157500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23527157500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23528923500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23528923500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # 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average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30085.763737 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30085.763737 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30082.674885 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30082.674885 # average overall mshr miss latency -system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.385132 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 643367692 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 63025.831897 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.385132 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.679387 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.679387 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1286766008 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1286766008 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 643367692 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 643367692 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 643367692 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 219076500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 219076500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 643377900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 643377900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 643377900 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 643377900 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 643377900 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 643377900 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21461.255878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21461.255878 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21461.255878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21461.255878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21461.255878 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 8769 # number of writebacks -system.cpu.icache.writebacks::total 8769 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 208868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 208868500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 208868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 208868500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 208868500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 208868500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20461.255878 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20461.255878 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20461.255878 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20461.255878 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 257772 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32622.591915 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218050 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290515 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.192727 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2525.639317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 45.833351 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30051.119247 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.077076 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001399 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.917087 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30923 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12984278 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12984278 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 88995 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88995 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 8752 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 8752 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3230 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8449 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490303 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 490303 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8449 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 493533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501982 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8449 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 493533 # number of overall hits -system.cpu.l2cache.overall_hits::total 501982 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66093 # 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number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3932586500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104759500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 104759500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13239976500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13239976500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 104759500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17172563000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17277322500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 104759500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17172563000 # 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number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712819 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 10208 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 782142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792350 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10208 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 782142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.172316 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312163 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312163 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.172316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368998 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.366464 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.172316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368998 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.366464 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.801900 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59556.281978 # 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number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1759 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288609 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290368 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1759 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288609 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290368 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3271656500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3271656500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87169500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87169500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11014816500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11014816500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87169500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14286473000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14373642500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87169500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14286473000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14373642500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.172316 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312163 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312163 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.366464 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368998 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.366464 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.801900 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49556.281978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49556.281978 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49501.233619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49501.233619 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49556.281978 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.134753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.468826 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1579165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1580 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 257772 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.051024 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1047402 99.74% 99.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2713 0.26% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1050122 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 887346500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 224275 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190094 # Transaction distribution -system.membus.trans_dist::ReadExReq 66093 # Transaction distribution -system.membus.trans_dist::ReadExResp 66093 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224275 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836928 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 836928 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22813824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22813824 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 546561 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 546561 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 546561 # Request fanout histogram -system.membus.reqLayer0.occupancy 811325000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1451840000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |