diff options
Diffstat (limited to 'tests/long/se/40.perlbmk')
4 files changed, 430 insertions, 436 deletions
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 5cc3f8bc2..f250ad066 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.545048 # Nu sim_ticks 545048444500 # Number of ticks simulated final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131789 # Simulator instruction rate (inst/s) -host_op_rate 162250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112122004 # Simulator tick rate (ticks/s) -host_mem_usage 314432 # Number of bytes of host memory used -host_seconds 4861.21 # Real time elapsed on the host +host_inst_rate 177094 # Simulator instruction rate (inst/s) +host_op_rate 218026 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 150665678 # Simulator tick rate (ticks/s) +host_mem_usage 323140 # Number of bytes of host memory used +host_seconds 3617.60 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -808,17 +808,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 899017 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 899017 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index d04be0b82..bdaafd38c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.409388 # Number of seconds simulated -sim_ticks 409388341000 # Number of ticks simulated -final_tick 409388341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 409388416000 # Number of ticks simulated +final_tick 409388416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75979 # Simulator instruction rate (inst/s) -host_op_rate 93540 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48552243 # Simulator tick rate (ticks/s) -host_mem_usage 312124 # Number of bytes of host memory used -host_seconds 8431.91 # Real time elapsed on the host +host_inst_rate 93306 # Simulator instruction rate (inst/s) +host_op_rate 114872 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59624294 # Simulator tick rate (ticks/s) +host_mem_usage 320320 # Number of bytes of host memory used +host_seconds 6866.13 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 226496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 226560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7024000 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 12938624 # Number of bytes read from this memory -system.physmem.bytes_read::total 20189120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 20189184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 226560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 226560 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4245888 # Number of bytes written to this memory system.physmem.bytes_written::total 4245888 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3540 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 109750 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 202166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315456 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66342 # Number of write requests responded to by this memory system.physmem.num_writes::total 66342 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 553255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17157303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31604769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49315327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 553255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 553255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10371297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10371297 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10371297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 553255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17157303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31604769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59686624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315455 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 553411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17157300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31604763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49315475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 553411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 553411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10371295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10371295 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10371295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 553411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17157300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31604763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59686769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315456 # Number of read requests accepted system.physmem.writeReqs 66342 # Number of write requests accepted -system.physmem.readBursts 315455 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 315456 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66342 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20169536 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 20169600 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue system.physmem.bytesWritten 4238784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20189120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 20189184 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4245888 # Total written bytes from the system interface side system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 19899 # Per bank write bursts system.physmem.perBankRdBursts::1 19575 # Per bank write bursts system.physmem.perBankRdBursts::2 19715 # Per bank write bursts @@ -67,7 +67,7 @@ system.physmem.perBankRdBursts::11 19765 # Pe system.physmem.perBankRdBursts::12 19604 # Per bank write bursts system.physmem.perBankRdBursts::13 19959 # Per bank write bursts system.physmem.perBankRdBursts::14 19457 # Per bank write bursts -system.physmem.perBankRdBursts::15 19977 # Per bank write bursts +system.physmem.perBankRdBursts::15 19978 # Per bank write bursts system.physmem.perBankWrBursts::0 4260 # Per bank write bursts system.physmem.perBankWrBursts::1 4107 # Per bank write bursts system.physmem.perBankWrBursts::2 4142 # Per bank write bursts @@ -86,14 +86,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4150 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 409388286500 # Total gap between requests +system.physmem.totGap 409388361500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315455 # Read request sizes (log2) +system.physmem.readPktSize::6 315456 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -101,7 +101,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66342 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 122393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 122394 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 117234 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14139 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6795 # What read queue length does an incoming req see @@ -197,20 +197,20 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136711 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.525503 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.653130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.190580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 136710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.527277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.653997 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.191580 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 54126 39.59% 39.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57416 42.00% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14736 10.78% 92.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57414 42.00% 81.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14737 10.78% 92.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 1353 0.99% 93.36% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 1490 1.09% 94.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1455 1.06% 95.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1216 0.89% 96.40% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1169 0.86% 97.26% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3750 2.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136711 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136710 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4038 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 65.701585 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::gmean 34.708310 # Reads before turning the bus around for writes @@ -248,12 +248,12 @@ system.physmem.wrPerTurnAround::27 2 0.05% 99.93% # Wr system.physmem.wrPerTurnAround::28 2 0.05% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4038 # Writes before turning the bus around for reads -system.physmem.totQLat 9474891317 # Total ticks spent queuing -system.physmem.totMemAccLat 15383935067 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1575745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30064.80 # Average queueing delay per DRAM burst +system.physmem.totQLat 9474850817 # Total ticks spent queuing +system.physmem.totMemAccLat 15383913317 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1575750000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30064.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48814.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 48814.58 # Average memory access latency per DRAM burst system.physmem.avgRdBW 49.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 49.32 # Average system read bandwidth in MiByte/s @@ -264,11 +264,11 @@ system.physmem.busUtilRead 0.38 # Da system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing -system.physmem.readRowHits 218193 # Number of row buffer hits during reads +system.physmem.readRowHits 218195 # Number of row buffer hits during reads system.physmem.writeRowHits 26465 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.23 # Row buffer hit rate for reads +system.physmem.readRowHitRate 69.24 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.94 # Row buffer hit rate for writes -system.physmem.avgGap 1072266.90 # Average gap between requests +system.physmem.avgGap 1072264.29 # Average gap between requests system.physmem.pageHitRate 64.15 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 518729400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 283036875 # Energy for precharge commands per rank (pJ) @@ -279,32 +279,32 @@ system.physmem_0.actBackEnergy 96374211480 # En system.physmem_0.preBackEnergy 161092645500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 286455220215 # Total energy per rank (pJ) system.physmem_0.averagePower 699.719632 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 267357168520 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 267357262270 # Time in different power states system.physmem_0.memoryStateTime::REF 13670280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 128358277730 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 514715040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 280846500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 514722600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280850625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1226721600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ) system.physmem_1.actBackEnergy 96210213075 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 161236503750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 286420773645 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.635490 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 267598080337 # Time in different power states +system.physmem_1.totalEnergy 286420785330 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.635519 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 267597865087 # Time in different power states system.physmem_1.memoryStateTime::REF 13670280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 128117581163 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233960254 # Number of BP lookups -system.cpu.branchPred.condPredicted 161822373 # Number of conditional branches predicted +system.cpu.branchPred.lookups 233960267 # Number of BP lookups +system.cpu.branchPred.condPredicted 161822378 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15514618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121575796 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108259792 # Number of BTB hits +system.cpu.branchPred.BTBLookups 121575807 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108259798 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.047159 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 89.047156 # BTB Hit Percentage system.cpu.branchPred.usedRAS 25036830 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1300193 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -425,84 +425,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 818776683 # number of cpu cycles simulated +system.cpu.numCycles 818776833 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84080283 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200690611 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233960254 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133296622 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 718833631 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 84080281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200690651 # Number of instructions fetch has processed +system.cpu.fetch.Branches 233960267 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133296628 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718834157 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 31063665 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 2157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3279 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370702181 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652815 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 818451212 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.833527 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370702196 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652814 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 818451752 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.833525 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.163546 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 136785734 16.71% 16.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 223134622 27.26% 43.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98075130 11.98% 55.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360455726 44.04% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136786252 16.71% 16.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223134631 27.26% 43.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98075133 11.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360455736 44.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 818451212 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 818451752 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.285744 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.466445 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119992571 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 159648210 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662538 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38629741 # Number of cycles decode is unblocking +system.cpu.fetch.rate 1.466444 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119992574 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159648734 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662553 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38629739 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 15518152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25181026 # Number of times decode resolved a branch +system.cpu.decode.BranchResolved 25181029 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248127712 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39967189 # Number of squashed instructions handled by decode +system.cpu.decode.DecodedInsts 1248127732 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39967182 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 15518152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 177000170 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78888622 # Number of cycles rename is blocking +system.cpu.rename.IdleCycles 177000175 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78889127 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 210704 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464955823 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81877741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190635480 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25549977 # Number of squashed instructions processed by rename +system.cpu.rename.RunCycles 464955834 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81877760 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190635501 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25549976 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 24948594 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2267380 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 41534187 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1694220 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225376851 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812387634 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358166964 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1694237 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225376861 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812387733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358166990 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 40876517 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350598621 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 350598631 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108139964 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366113107 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236095924 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 108139973 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366113111 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236095933 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1592417 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 5322589 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168545112 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 1168545131 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12357 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017136895 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18518107 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379832511 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032101117 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017136914 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18518110 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379832530 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032101126 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 203 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 818451212 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.242758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 818451752 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.242757 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 260801504 31.87% 31.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227738074 27.83% 59.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 216482418 26.45% 86.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97282888 11.89% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16146319 1.97% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 260802028 31.87% 31.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227738086 27.83% 59.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216482422 26.45% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97282889 11.89% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16146318 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -510,7 +510,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 818451212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 818451752 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 64511713 19.12% 19.12% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18146 0.01% 19.13% # attempts to use FU when none available @@ -541,12 +541,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155540663 46.10% 65.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116678902 34.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155540667 46.10% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116678907 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456370981 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456370990 44.87% 44.87% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued @@ -575,40 +575,40 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 11478993 1.13% 47.13% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322128329 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215587412 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322128333 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215587418 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017136895 # Type of FU issued +system.cpu.iq.FU_type_0::total 1017136914 # Type of FU issued system.cpu.iq.rate 1.242264 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337386313 # FU busy when requested +system.cpu.iq.fu_busy_cnt 337386322 # FU busy when requested system.cpu.iq.fu_busy_rate 0.331702 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3146752380 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504842501 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934271178 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_reads 3146752970 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504842539 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934271199 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 61877042 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 43565869 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320712858 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1320712886 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33810350 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 9960171 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113872169 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 113872173 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18393 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107115428 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 107115437 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2065797 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 22350 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 15518152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35325435 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 35325436 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 42128 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168563023 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 1168563042 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366113107 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236095924 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366113111 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236095933 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6617 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 102 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 45749 # Number of times the LSQ has become full, causing a stall @@ -616,43 +616,43 @@ system.cpu.iew.memOrderViolationEvents 18393 # Nu system.cpu.iew.predictedTakenIncorrect 15437385 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 3784510 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974751162 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303297617 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42385733 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 974751184 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297622 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42385730 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 5554 # number of nop insts executed -system.cpu.iew.exec_refs 497765227 # number of memory reference insts executed -system.cpu.iew.exec_branches 150613464 # Number of branches executed -system.cpu.iew.exec_stores 194467610 # Number of stores executed +system.cpu.iew.exec_refs 497765238 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613469 # Number of branches executed +system.cpu.iew.exec_stores 194467616 # Number of stores executed system.cpu.iew.exec_rate 1.190497 # Inst execution rate -system.cpu.iew.wb_sent 963723916 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960423621 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536680580 # num instructions producing a value -system.cpu.iew.wb_consumers 893282190 # num instructions consuming a value +system.cpu.iew.wb_sent 963723937 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960423642 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536680583 # num instructions producing a value +system.cpu.iew.wb_consumers 893282195 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 1.172998 # insts written-back per cycle system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357407190 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357407209 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 15500938 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 767630958 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.027486 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.786865 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 767631497 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.027485 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.786864 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 430922921 56.14% 56.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172477665 22.47% 78.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 430923455 56.14% 56.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172477669 22.47% 78.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 73566542 9.58% 88.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31624091 4.12% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31624094 4.12% 92.31% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 8540357 1.11% 93.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14250533 1.86% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14250532 1.86% 95.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 7269334 0.95% 96.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 6619169 0.86% 97.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360346 2.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360345 2.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 767630958 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 767631497 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -698,30 +698,30 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360346 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1891399121 # The number of ROB reads -system.cpu.rob.rob_writes 2343098694 # The number of ROB writes -system.cpu.timesIdled 647342 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 325471 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22360345 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1891399680 # The number of ROB reads +system.cpu.rob.rob_writes 2343098733 # The number of ROB writes +system.cpu.timesIdled 647345 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 325081 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated system.cpu.cpi 1.278042 # CPI: Cycles Per Instruction system.cpu.cpi_total 1.278042 # CPI: Total CPI of All Threads system.cpu.ipc 0.782447 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.782447 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995806500 # number of integer regfile reads -system.cpu.int_regfile_writes 567906149 # number of integer regfile writes +system.cpu.int_regfile_reads 995806519 # number of integer regfile reads +system.cpu.int_regfile_writes 567906159 # number of integer regfile writes system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794435390 # number of cc regfile reads -system.cpu.cc_regfile_writes 384898944 # number of cc regfile writes -system.cpu.misc_regfile_reads 715817585 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794435468 # number of cc regfile reads +system.cpu.cc_regfile_writes 384898950 # number of cc regfile writes +system.cpu.misc_regfile_reads 715817595 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes system.cpu.dcache.tags.replacements 2756184 # number of replacements system.cpu.dcache.tags.tagsinuse 511.932971 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414226707 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 414226712 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2756696 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.262019 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.262021 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.932971 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy @@ -732,10 +732,10 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 224 system.cpu.dcache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839343974 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839343974 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286295255 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286295255 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 839343984 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839343984 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286295259 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286295259 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 127916705 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 127916705 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3174 # number of SoftPFReq hits @@ -744,34 +744,34 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414211960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414211960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414215134 # number of overall hits -system.cpu.dcache.overall_hits::total 414215134 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3031607 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3031607 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 414211964 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414211964 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414215138 # number of overall hits +system.cpu.dcache.overall_hits::total 414215138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031608 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031608 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1034772 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1034772 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4066379 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4066379 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4067026 # number of overall misses -system.cpu.dcache.overall_misses::total 4067026 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 35304231919 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 35304231919 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981686625 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9981686625 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4066380 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4066380 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4067027 # number of overall misses +system.cpu.dcache.overall_misses::total 4067027 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35305181420 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35305181420 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9981703626 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9981703626 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45285918544 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45285918544 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45285918544 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45285918544 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289326862 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289326862 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 45286885046 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45286885046 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45286885046 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45286885046 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289326867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289326867 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3821 # number of SoftPFReq accesses(hits+misses) @@ -780,10 +780,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418278339 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418278339 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418282160 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418282160 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 418278344 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418278344 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418282165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418282165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses @@ -796,16 +796,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.385407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.385407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.266641 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.266641 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11645.694767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11645.694767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9646.283071 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9646.283071 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63166.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.669392 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11136.669392 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11134.897722 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11134.897722 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11136.904334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11136.904334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11135.132628 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11135.132628 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 343566 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -816,16 +816,16 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 735673 # number of writebacks system.cpu.dcache.writebacks::total 735673 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996398 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 996398 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996399 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 996399 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313907 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 313907 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1310305 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1310305 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1310305 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1310305 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1310306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1310306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1310306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1310306 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720865 # number of WriteReq MSHR misses @@ -836,16 +836,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2756074 system.cpu.dcache.demand_mshr_misses::total 2756074 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2756715 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2756715 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23117834450 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23117834450 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596502782 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596502782 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23118028700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23118028700 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5596519781 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5596519781 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5770003 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5770003 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714337232 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28714337232 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720107235 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28720107235 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28714548481 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28714548481 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28720318484 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28720318484 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses @@ -856,108 +856,108 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11358.948614 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11358.948614 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.593436 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.593436 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11359.044059 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11359.044059 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7763.617017 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7763.617017 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 9001.564743 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 9001.564743 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.565406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.565406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.235920 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.235920 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10418.642054 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10418.642054 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10418.312551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10418.312551 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169973 # number of replacements +system.cpu.icache.tags.replacements 5169974 # number of replacements system.cpu.icache.tags.tagsinuse 511.005918 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 365527993 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5170483 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.695135 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 365528009 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5170484 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.695124 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 247768250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.005918 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 746574800 # Number of tag accesses -system.cpu.icache.tags.data_accesses 746574800 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 365528016 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 365528016 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 365528016 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 365528016 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 365528016 # number of overall hits -system.cpu.icache.overall_hits::total 365528016 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5174133 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5174133 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5174133 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174133 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174133 # number of overall misses -system.cpu.icache.overall_misses::total 5174133 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647669446 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41647669446 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41647669446 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41647669446 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41647669446 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41647669446 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370702149 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370702149 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370702149 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370702149 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370702149 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370702149 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 746574831 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746574831 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365528032 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365528032 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365528032 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 365528032 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 365528032 # number of overall hits +system.cpu.icache.overall_hits::total 365528032 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174132 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174132 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174132 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174132 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174132 # number of overall misses +system.cpu.icache.overall_misses::total 5174132 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41647443196 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41647443196 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41647443196 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41647443196 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41647443196 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41647443196 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370702164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370702164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370702164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370702164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370702164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370702164 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013958 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013958 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013958 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013958 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013958 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013958 # 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number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 19 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 720846 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 720846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5170485 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 5170486 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 2756696 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7927181 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5170485 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7927182 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5170486 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 2756696 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7927181 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7927182 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000687 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053854 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.015707 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003965 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.003965 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000687 # miss rate for demand accesses @@ -1062,17 +1062,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.014640 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000687 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.040809 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014640 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73505.759640 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78090.323069 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77946.417547 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73435.485087 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.090232 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77945.883535 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1236.789474 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1236.789474 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71806.752624 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71806.752624 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77795.214080 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73505.759640 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77930.688196 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77795.214080 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77794.694522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73435.485087 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77932.410464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77794.694522 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1094,130 +1096,128 @@ system.cpu.l2cache.demand_mshr_hits::total 2761 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 2747 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 2761 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3539 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3540 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108352 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 111891 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 111892 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202242 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 202242 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 19 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 19 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1398 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1398 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3539 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3540 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 109750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 113289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3539 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113290 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3540 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 109750 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202242 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 315531 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 230067036 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7609571000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839638036 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 315532 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 229882786 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7609765250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7839648036 # number of ReadReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17078829649 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 248018 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 248018 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 262019 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 262019 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114010508 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114010508 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 230067036 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723581508 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7953648544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 230067036 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723581508 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229882786 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7723775758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7953658544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229882786 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7723775758 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25032478193 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_miss_latency::total 25032488193 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053222 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015527 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001939 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001939 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.014291 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.039804 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65009.052275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70230.092661 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.956395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64938.640113 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.419583 # average ReadReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average HardPFReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13778.777778 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13778.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13790.473684 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.715074 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70206.183635 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64938.640113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70376.088911 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.449525 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7206353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7206352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7206354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7206353 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 735673 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 248887 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340989 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6249103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16590090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330910976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16590092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330911040 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223511616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554422592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554422656 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 248905 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8911778 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.027928 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8911779 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.027928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.164766 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 8662891 97.21% 97.21% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 248887 2.79% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8662892 97.21% 97.21% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 248887 2.79% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8911778 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5067118500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8911779 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5067119000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7756291499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7756292749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4138722865 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4138723116 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 314057 # Transaction distribution -system.membus.trans_dist::ReadResp 314057 # Transaction distribution +system.membus.trans_dist::ReadReq 314058 # Transaction distribution +system.membus.trans_dist::ReadResp 314058 # Transaction distribution system.membus.trans_dist::Writeback 66342 # Transaction distribution -system.membus.trans_dist::UpgradeReq 18 # Transaction distribution -system.membus.trans_dist::UpgradeResp 18 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19 # Transaction distribution +system.membus.trans_dist::UpgradeResp 19 # Transaction distribution system.membus.trans_dist::ReadExReq 1398 # Transaction distribution system.membus.trans_dist::ReadExResp 1398 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 697288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24435008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697292 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697292 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24435072 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381815 # Request fanout histogram +system.membus.snoop_fanout::samples 381817 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381815 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381817 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381815 # Request fanout histogram -system.membus.reqLayer0.occupancy 746604866 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381817 # Request fanout histogram +system.membus.reqLayer0.occupancy 746606366 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648190996 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1648197495 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 790f4a782..f8c904908 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778500 # Number of ticks simulated final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1109777 # Simulator instruction rate (inst/s) -host_op_rate 1366282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 685499869 # Simulator tick rate (ticks/s) -host_mem_usage 303676 # Number of bytes of host memory used -host_seconds 577.28 # Real time elapsed on the host +host_inst_rate 1575908 # Simulator instruction rate (inst/s) +host_op_rate 1940150 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 973424664 # Simulator tick rate (ticks/s) +host_mem_usage 311080 # Number of bytes of host memory used +host_seconds 406.53 # Real time elapsed on the host sim_insts 640654411 # Number of instructions simulated sim_ops 788730070 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,16 +230,14 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram -system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram +system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::3 643377899 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 1022670353 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index e0c0a3846..4a7e6f230 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -598,17 +598,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 883911 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |