diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 858 |
1 files changed, 508 insertions, 350 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 7d4bfa05d..14d4b21df 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,217 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046793 # Number of seconds simulated -sim_ticks 46793182500 # Number of ticks simulated -final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.046394 # Number of seconds simulated +sim_ticks 46393648500 # Number of ticks simulated +final_tick 46393648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131801 # Simulator instruction rate (inst/s) -host_op_rate 131801 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69813482 # Simulator tick rate (ticks/s) -host_mem_usage 220956 # Number of bytes of host memory used -host_seconds 670.26 # Real time elapsed on the host +host_inst_rate 96549 # Simulator instruction rate (inst/s) +host_op_rate 96549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50704548 # Simulator tick rate (ticks/s) +host_mem_usage 252684 # Number of bytes of host memory used +host_seconds 914.98 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10272832 # Number of bytes read from this memory -system.physmem.bytes_read::total 10787712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 514880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 514880 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 514944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10272704 # Number of bytes read from this memory +system.physmem.bytes_read::total 10787648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 514944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 514944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8045 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160513 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 8046 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160511 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168557 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11003312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 219536938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 230540250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11003312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11003312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 158621397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 158621397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 158621397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11003312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 219536938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 389161648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 11099450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 221424793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 232524243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11099450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11099450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 159987417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 159987417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 159987417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11099450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 221424793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 392511660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168557 # Total number of read requests seen +system.physmem.writeReqs 115975 # Total number of write requests seen +system.physmem.cpureqs 284532 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10787648 # Total number of bytes read from memory +system.physmem.bytesWritten 7422400 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10787648 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7422400 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 10983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10544 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10882 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10471 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10499 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10074 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10523 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10531 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10827 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10322 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7019 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7391 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7077 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7201 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7177 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7052 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7484 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7300 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 46393600000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 168557 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 115975 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 162958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 4989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1271098054 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4666794054 # Sum of mem lat for all requests +system.physmem.totBusLat 674180000 # Total cycles spent in databus access +system.physmem.totBankLat 2721516000 # Total cycles spent in bank access +system.physmem.avgQLat 7541.59 # Average queueing delay per request +system.physmem.avgBankLat 16147.12 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27688.71 # Average memory access latency +system.physmem.avgRdBW 232.52 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 159.99 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 232.52 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 159.99 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.45 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.10 # Average read queue length over time +system.physmem.avgWrQLen 10.39 # Average write queue length over time +system.physmem.readRowHits 152922 # Number of row buffer hits during reads +system.physmem.writeRowHits 84722 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.05 # Row buffer hit rate for writes +system.physmem.avgGap 163052.31 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277225 # DTB read hits +system.cpu.dtb.read_hits 20277224 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367373 # DTB read accesses -system.cpu.dtb.write_hits 14736820 # DTB write hits +system.cpu.dtb.read_accesses 20367372 # DTB read accesses +system.cpu.dtb.write_hits 14736801 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744072 # DTB write accesses -system.cpu.dtb.data_hits 35014045 # DTB hits +system.cpu.dtb.write_accesses 14744053 # DTB write accesses +system.cpu.dtb.data_hits 35014025 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111445 # DTB accesses -system.cpu.itb.fetch_hits 12477645 # ITB hits -system.cpu.itb.fetch_misses 12958 # ITB misses +system.cpu.dtb.data_accesses 35111425 # DTB accesses +system.cpu.itb.fetch_hits 12475425 # ITB hits +system.cpu.itb.fetch_misses 12954 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12490603 # ITB accesses +system.cpu.itb.fetch_accesses 12488379 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 93586366 # number of cpu cycles simulated +system.cpu.numCycles 92787298 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18829185 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12442057 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5026145 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16204746 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5047870 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18828887 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12440846 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5023695 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16217673 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5047073 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660946 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.150565 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8475762 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10353423 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74332851 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.120821 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8474385 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10354502 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74331965 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126652101 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65265 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126651215 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65206 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292895 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14120054 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064610 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4681911 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 233734 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4915645 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8856618 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.692355 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44775927 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292836 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14119774 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064022 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4679410 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233785 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4913195 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8859107 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.674465 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44776036 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78075293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78069956 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 311800 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23300937 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70285429 # Number of cycles cpu stages are processed. -system.cpu.activity 75.102210 # Percentage of cycles cpu is active +system.cpu.timesIdled 311324 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 22508104 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70279194 # Number of cycles cpu stages are processed. +system.cpu.activity 75.742257 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,144 +272,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.059380 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.050335 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.059380 # CPI: Total CPI of All Threads -system.cpu.ipc 0.943948 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.050335 # CPI: Total CPI of All Threads +system.cpu.ipc 0.952077 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.943948 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 40161098 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53425268 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 57.086593 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 50931554 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42654812 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.578019 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50461046 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43125320 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 46.080772 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71466223 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120143 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.636074 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47482076 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46104290 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.263896 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85221 # number of replacements -system.cpu.icache.tagsinuse 1887.407088 # Cycle average of tags in use -system.cpu.icache.total_refs 12359392 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87267 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.627328 # Average number of references to valid blocks. +system.cpu.ipc_total 0.952077 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 39364116 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53423182 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 57.575965 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 50132225 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42655073 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.970811 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 49662532 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43124766 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 46.477015 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 70666607 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120691 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.840215 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46683402 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46103896 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 49.687723 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85246 # number of replacements +system.cpu.icache.tagsinuse 1892.367381 # Cycle average of tags in use +system.cpu.icache.total_refs 12357191 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87292 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.561552 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1887.407088 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.921585 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.921585 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12359392 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12359392 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12359392 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12359392 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12359392 # number of overall hits -system.cpu.icache.overall_hits::total 12359392 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118206 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118206 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118206 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118206 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118206 # number of overall misses -system.cpu.icache.overall_misses::total 118206 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1871587000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1871587000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1871587000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1871587000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1871587000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1871587000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12477598 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12477598 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12477598 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12477598 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12477598 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12477598 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15833.265655 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15833.265655 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15833.265655 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1892.367381 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.924008 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.924008 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12357191 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12357191 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12357191 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12357191 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12357191 # number of overall hits +system.cpu.icache.overall_hits::total 12357191 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118187 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118187 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118187 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118187 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118187 # number of overall misses +system.cpu.icache.overall_misses::total 118187 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1883931500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1883931500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1883931500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1883931500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1883931500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1883931500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12475378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12475378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12475378 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12475378 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12475378 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12475378 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15940.259927 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15940.259927 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15940.259927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15940.259927 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 2050 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1882 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 108 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21.808511 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 17.425926 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30939 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30939 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30939 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30939 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30939 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87267 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87267 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87267 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87267 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87267 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87267 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1309592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1309592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1309592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1309592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1309592500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1309592500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006994 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006994 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006994 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15006.732213 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15006.732213 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30895 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30895 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30895 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30895 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30895 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30895 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87292 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87292 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87292 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87292 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87292 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87292 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1323717000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1323717000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1323717000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1323717000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1323717000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1323717000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006997 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006997 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006997 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15164.241855 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15164.241855 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15164.241855 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15164.241855 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15164.241855 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15164.241855 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4072.865489 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126021 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4074.773035 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126001 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000352 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 486992000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.865489 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994352 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994352 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180532 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180532 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945489 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945489 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126021 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126021 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34126021 # number of overall hits -system.cpu.dcache.overall_hits::total 34126021 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96106 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96106 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667888 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667888 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 763994 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 763994 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 763994 # number of overall misses -system.cpu.dcache.overall_misses::total 763994 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3881207000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3881207000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 34562623000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 34562623000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38443830000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38443830000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38443830000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38443830000 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000254 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 420616000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4074.773035 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994818 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994818 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180529 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180529 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945472 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945472 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34126001 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34126001 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34126001 # number of overall hits +system.cpu.dcache.overall_hits::total 34126001 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96109 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96109 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667905 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667905 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764014 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764014 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764014 # number of overall misses +system.cpu.dcache.overall_misses::total 764014 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3658302500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3658302500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32880134000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32880134000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36538436500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36538436500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36538436500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36538436500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -262,38 +420,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045704 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045704 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40384.648201 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40384.648201 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51749.130094 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51749.130094 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50319.544394 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 12521367 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 100.881952 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045705 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045705 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38064.099096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38064.099096 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49228.758581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49228.758581 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47824.302303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47824.302303 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11803841 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124100 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 271 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95.115560 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks -system.cpu.dcache.writebacks::total 165811 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35339 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35339 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524308 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524308 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559647 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559647 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559647 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559647 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 165814 # number of writebacks +system.cpu.dcache.writebacks::total 165814 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35342 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35342 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524325 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524325 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559667 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559667 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559667 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559667 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -302,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1916080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1916080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7177771000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7177771000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9093851000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9093851000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9093851000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9093851000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1847026500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1847026500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6899064500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6899064500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8746091000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8746091000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8746091000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8746091000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -318,152 +476,152 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31531.587868 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31531.587868 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49991.440312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49991.440312 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30395.222736 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30395.222736 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48050.316897 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48050.316897 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 87267 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 87292 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 291614 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 87267 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 291639 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 87292 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 291614 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092188 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486414 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52642.849939 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092173 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.785483 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.577965 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092173 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.785483 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.577965 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54854.523987 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49937.805458 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50992.455345 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50569.448366 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50569.448366 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54854.523987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50453.501629 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50663.582646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54854.523987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50453.501629 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50663.582646 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1238 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 309.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 115975 # number of writebacks system.cpu.l2cache.writebacks::total 115975 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8045 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29466 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37511 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8046 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29464 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37510 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131047 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 131047 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8045 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 160513 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168558 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8045 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160513 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168558 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329317000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181708500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1511025500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5272374500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5272374500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6454083000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6783400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329317000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6454083000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6783400000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486414 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253718 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160511 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168557 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160511 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168557 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339209803 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1094048732 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1433258535 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4985919806 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4985919806 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339209803 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6079968538 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6419178341 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339209803 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6079968538 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6419178341 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253669 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.578018 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.578018 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40934.369173 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40104.136971 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40282.197222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40232.698955 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40232.698955 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.577965 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.577965 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42158.812205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37131.710969 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38210.038256 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38046.806154 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38046.806154 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |