diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 692 |
1 files changed, 346 insertions, 346 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 0041bdcc8..52b1e9eb7 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.047017 # Number of seconds simulated -sim_ticks 47017029500 # Number of ticks simulated -final_tick 47017029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.047910 # Number of seconds simulated +sim_ticks 47910283500 # Number of ticks simulated +final_tick 47910283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156470 # Simulator instruction rate (inst/s) -host_op_rate 156470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 83276889 # Simulator tick rate (ticks/s) -host_mem_usage 227180 # Number of bytes of host memory used -host_seconds 564.59 # Real time elapsed on the host +host_inst_rate 137428 # Simulator instruction rate (inst/s) +host_op_rate 137428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74532010 # Simulator tick rate (ticks/s) +host_mem_usage 227148 # Number of bytes of host memory used +host_seconds 642.82 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 515072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10272768 # Number of bytes read from this memory -system.physmem.bytes_read::total 10787840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 515072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 515072 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 515328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10272960 # Number of bytes read from this memory +system.physmem.bytes_read::total 10788288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 515328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 515328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8048 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160512 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 8052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160515 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168567 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10955009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 218490366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 229445376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10955009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10955009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 157866205 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 157866205 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 157866205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10955009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 218490366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 387311580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10756104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 214420773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 225176877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10756104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10756104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 154922899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 154922899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 154922899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10756104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 214420773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 380099775 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277221 # DTB read hits +system.cpu.dtb.read_hits 20277225 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367369 # DTB read accesses -system.cpu.dtb.write_hits 14736814 # DTB write hits +system.cpu.dtb.read_accesses 20367373 # DTB read accesses +system.cpu.dtb.write_hits 14736863 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744066 # DTB write accesses -system.cpu.dtb.data_hits 35014035 # DTB hits +system.cpu.dtb.write_accesses 14744115 # DTB write accesses +system.cpu.dtb.data_hits 35014088 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111435 # DTB accesses -system.cpu.itb.fetch_hits 12478267 # ITB hits -system.cpu.itb.fetch_misses 13087 # ITB misses +system.cpu.dtb.data_accesses 35111488 # DTB accesses +system.cpu.itb.fetch_hits 12475946 # ITB hits +system.cpu.itb.fetch_misses 12952 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12491354 # ITB accesses +system.cpu.itb.fetch_accesses 12488898 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 94034060 # number of cpu cycles simulated +system.cpu.numCycles 95820568 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18830633 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12442208 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5026177 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16228748 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5052031 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660951 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18829757 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12442338 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5025331 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16200752 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5042995 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1029 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.130134 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8480322 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10350311 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74324480 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.128154 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8471214 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10358543 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74332888 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126643730 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65335 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126652138 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65238 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292965 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14127744 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064158 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4682153 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 233524 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4915677 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8856497 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.692818 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44775466 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292868 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14120784 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064786 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4680831 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 234000 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4914831 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8857404 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.686517 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44775821 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78068863 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78582823 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 305152 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23747130 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70286930 # Number of cycles cpu stages are processed. -system.cpu.activity 74.746246 # Percentage of cycles cpu is active +system.cpu.timesIdled 467369 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25529650 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70290918 # Number of cycles cpu stages are processed. +system.cpu.activity 73.356816 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.064448 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.084671 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.064448 # CPI: Total CPI of All Threads -system.cpu.ipc 0.939454 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.084671 # CPI: Total CPI of All Threads +system.cpu.ipc 0.921939 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.939454 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 40602486 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53431574 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 56.821511 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 51377982 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42656078 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.362370 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50907944 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43126116 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 45.862229 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71905105 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22128955 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.532915 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47936936 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46097124 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.021731 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85298 # number of replacements -system.cpu.icache.tagsinuse 1887.307132 # Cycle average of tags in use -system.cpu.icache.total_refs 12360070 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87344 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.510235 # Average number of references to valid blocks. +system.cpu.ipc_total 0.921939 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 42393437 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53427131 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 55.757477 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 53162471 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42658097 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 44.518727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 52693934 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43126634 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 45.007700 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 73699390 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22121178 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.086043 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 49718373 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46102195 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 48.113047 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85335 # number of replacements +system.cpu.icache.tagsinuse 1885.674809 # Cycle average of tags in use +system.cpu.icache.total_refs 12357256 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87381 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.418111 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1887.307132 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.921537 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.921537 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12360070 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12360070 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12360070 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12360070 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12360070 # number of overall hits -system.cpu.icache.overall_hits::total 12360070 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118149 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118149 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118149 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118149 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118149 # number of overall misses -system.cpu.icache.overall_misses::total 118149 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2012242500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2012242500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2012242500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2012242500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2012242500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2012242500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12478219 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12478219 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12478219 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12478219 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12478219 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12478219 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009468 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17031.396796 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17031.396796 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17031.396796 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17031.396796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17031.396796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17031.396796 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1885.674809 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.920740 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.920740 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12357256 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12357256 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12357256 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12357256 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12357256 # number of overall hits +system.cpu.icache.overall_hits::total 12357256 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118639 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118639 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118639 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118639 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118639 # number of overall misses +system.cpu.icache.overall_misses::total 118639 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2081821000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2081821000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2081821000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2081821000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2081821000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2081821000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12475895 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12475895 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12475895 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12475895 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12475895 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12475895 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009509 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009509 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009509 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009509 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009509 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009509 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17547.526530 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17547.526530 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17547.526530 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17547.526530 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17547.526530 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1223500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1176500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 109 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 105 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 11224.770642 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 11204.761905 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30805 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30805 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30805 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30805 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30805 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30805 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87344 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87344 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87344 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87344 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87344 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1308493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1308493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1308493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1308493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1308493500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1308493500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.007000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.007000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14980.920269 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14980.920269 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14980.920269 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14980.920269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14980.920269 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14980.920269 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31258 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 31258 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 31258 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 31258 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 31258 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 31258 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87381 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87381 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87381 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87381 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87381 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87381 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1364843500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1364843500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1364843500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1364843500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1364843500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1364843500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007004 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15619.453886 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15619.453886 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15619.453886 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15619.453886 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4073.021699 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126085 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4073.238674 # Cycle average of tags in use +system.cpu.dcache.total_refs 34125947 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000666 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 487962000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4073.021699 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994390 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994390 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180546 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180546 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945539 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945539 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126085 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126085 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34126085 # number of overall hits -system.cpu.dcache.overall_hits::total 34126085 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96092 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96092 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667838 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667838 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 763930 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 763930 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 763930 # number of overall misses -system.cpu.dcache.overall_misses::total 763930 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3967104000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3967104000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35310638000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35310638000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39277742000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39277742000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39277742000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39277742000 # number of overall miss cycles +system.cpu.dcache.avg_refs 166.999990 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 499859000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4073.238674 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994443 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994443 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180530 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180530 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945417 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945417 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34125947 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34125947 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34125947 # number of overall hits +system.cpu.dcache.overall_hits::total 34125947 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96108 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96108 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667960 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667960 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764068 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764068 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764068 # number of overall misses +system.cpu.dcache.overall_misses::total 764068 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4228645500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4228645500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 42086848500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 42086848500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 46315494000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 46315494000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 46315494000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 46315494000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -260,40 +260,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004739 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004739 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045700 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021895 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021895 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021895 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021895 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41284.435749 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41284.435749 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52873.059035 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52873.059035 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51415.367900 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51415.367900 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51415.367900 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51415.367900 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045709 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045709 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021899 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021899 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43998.891872 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43998.891872 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63008.037158 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63008.037158 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60616.979117 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60616.979117 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60616.979117 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 6330819000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 6945858000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124116 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124169 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51007.275452 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 55938.744775 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165812 # number of writebacks -system.cpu.dcache.writebacks::total 165812 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35325 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35325 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524258 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524258 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559583 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559583 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559583 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559583 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 165805 # number of writebacks +system.cpu.dcache.writebacks::total 165805 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35341 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35341 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524380 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524380 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559721 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559721 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559721 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559721 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -302,14 +302,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1914810500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1914810500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7237342000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7237342000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9152152500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9152152500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9152152500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9152152500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1936845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1936845000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7868977000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7868977000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9805822000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9805822000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9805822000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9805822000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -318,98 +318,98 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31510.696595 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31510.696595 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50406.337930 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50406.337930 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44787.310310 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44787.310310 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44787.310310 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44787.310310 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31873.302944 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31873.302944 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54805.523053 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54805.523053 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 47986.131433 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 47986.131433 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 136133 # number of replacements -system.cpu.l2cache.tagsinuse 28807.621629 # Cycle average of tags in use -system.cpu.l2cache.total_refs 146477 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 166996 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.877129 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 136141 # number of replacements +system.cpu.l2cache.tagsinuse 28773.047265 # Cycle average of tags in use +system.cpu.l2cache.total_refs 146499 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 167004 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.877219 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25341.359652 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1731.515405 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1734.746571 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.773357 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.052842 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.052940 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.879139 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 79296 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31113 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 110409 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 165812 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 165812 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 25287.688081 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1723.908362 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1761.450821 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.771719 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.052610 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.053755 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.878084 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 79329 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31110 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 110439 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 165805 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 165805 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12722 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12722 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 79296 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 43835 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 123131 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 79296 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 43835 # number of overall hits -system.cpu.l2cache.overall_hits::total 123131 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8048 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 29464 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 37512 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 79329 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 43832 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 123161 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 79329 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 43832 # number of overall hits +system.cpu.l2cache.overall_hits::total 123161 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 8052 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 29467 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37519 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 131048 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 131048 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8048 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 160512 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 168560 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8048 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 160512 # number of overall misses -system.cpu.l2cache.overall_misses::total 168560 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 420766000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1537793000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1958559000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6828933500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6828933500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 420766000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8366726500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8787492500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 420766000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8366726500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8787492500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 87344 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 8052 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 160515 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168567 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8052 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 160515 # number of overall misses +system.cpu.l2cache.overall_misses::total 168567 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 427362500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1541002500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1968365000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6838998500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6838998500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 427362500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8380001000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8807363500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 427362500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8380001000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8807363500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 87381 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 147921 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 165812 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 165812 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 147958 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 165805 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 165805 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 87344 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 87381 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 291691 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 87344 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 291728 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 87381 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 291691 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092141 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486389 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.253595 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 291728 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092148 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486439 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.253579 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911511 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.911511 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092141 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.785487 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.577872 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092141 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.785487 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.577872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52282.057654 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52192.268531 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52211.532310 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52110.169556 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52110.169556 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52282.057654 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52125.239857 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52132.727219 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52282.057654 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52125.239857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52132.727219 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092148 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.785502 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.577822 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092148 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.785502 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.577822 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53075.322901 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52295.873350 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52463.152003 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52186.973475 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52186.973475 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52248.444239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53075.322901 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52206.965081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52248.444239 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,50 +420,50 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 115975 # number of writebacks system.cpu.l2cache.writebacks::total 115975 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8048 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29464 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37512 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8052 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29467 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37519 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131048 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 131048 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8048 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 160512 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168560 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8048 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160512 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168560 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 322504500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1178813500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1501318000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5243991500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5243991500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 322504500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6422805000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6745309500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 322504500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6422805000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6745309500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486389 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253595 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8052 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160515 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168567 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8052 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160515 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168567 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329154000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181438500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1510592500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5254733000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5254733000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329154000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6436171500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6765325500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329154000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6436171500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6765325500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486439 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253579 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785487 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.577872 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092141 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785487 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.577872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40072.626740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40008.603720 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40022.339518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40015.807185 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40015.807185 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40072.626740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40014.484898 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40017.260916 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40072.626740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40014.484898 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40017.260916 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.577822 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092148 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785502 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.577822 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40878.539493 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40093.613194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40262.067219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40097.773335 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40097.773335 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40878.539493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40097.009625 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40134.341241 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |