diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/minor-timing')
3 files changed, 579 insertions, 560 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini index 4117f093b..46094eb94 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout index dcc24233a..a86af0918 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4306 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28063 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 60000593000 because target called exit() +Exiting @ tick 61709224000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 58628a22b..4a990b700 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060094 # Number of seconds simulated -sim_ticks 60093931000 # Number of ticks simulated -final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061709 # Number of seconds simulated +sim_ticks 61709224000 # Number of ticks simulated +final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 276952 # Simulator instruction rate (inst/s) -host_op_rate 276952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188189933 # Simulator tick rate (ticks/s) -host_mem_usage 264524 # Number of bytes of host memory used -host_seconds 319.33 # Real time elapsed on the host +host_inst_rate 242211 # Simulator instruction rate (inst/s) +host_op_rate 242211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 169006859 # Simulator tick rate (ticks/s) +host_mem_usage 262168 # Number of bytes of host memory used +host_seconds 365.13 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory -system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory -system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165736 # Number of read requests accepted -system.physmem.writeReqs 115250 # Number of write requests accepted -system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory +system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory +system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165740 # Number of read requests accepted +system.physmem.writeReqs 115251 # Number of write requests accepted +system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue +system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10345 # Per bank write bursts -system.physmem.perBankRdBursts::1 10388 # Per bank write bursts +system.physmem.perBankRdBursts::1 10387 # Per bank write bursts system.physmem.perBankRdBursts::2 10224 # Per bank write bursts -system.physmem.perBankRdBursts::3 10067 # Per bank write bursts +system.physmem.perBankRdBursts::3 10068 # Per bank write bursts system.physmem.perBankRdBursts::4 10353 # Per bank write bursts system.physmem.perBankRdBursts::5 10360 # Per bank write bursts system.physmem.perBankRdBursts::6 9794 # Per bank write bursts -system.physmem.perBankRdBursts::7 10229 # Per bank write bursts +system.physmem.perBankRdBursts::7 10230 # Per bank write bursts system.physmem.perBankRdBursts::8 10568 # Per bank write bursts system.physmem.perBankRdBursts::9 10626 # Per bank write bursts -system.physmem.perBankRdBursts::10 10567 # Per bank write bursts +system.physmem.perBankRdBursts::10 10568 # Per bank write bursts system.physmem.perBankRdBursts::11 10241 # Per bank write bursts -system.physmem.perBankRdBursts::12 10307 # Per bank write bursts -system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::12 10306 # Per bank write bursts +system.physmem.perBankRdBursts::13 10592 # Per bank write bursts system.physmem.perBankRdBursts::14 10494 # Per bank write bursts system.physmem.perBankRdBursts::15 10573 # Per bank write bursts system.physmem.perBankWrBursts::0 7166 # Per bank write bursts -system.physmem.perBankWrBursts::1 7280 # Per bank write bursts +system.physmem.perBankWrBursts::1 7281 # Per bank write bursts system.physmem.perBankWrBursts::2 7303 # Per bank write bursts -system.physmem.perBankWrBursts::3 7011 # Per bank write bursts -system.physmem.perBankWrBursts::4 7144 # Per bank write bursts -system.physmem.perBankWrBursts::5 7304 # Per bank write bursts +system.physmem.perBankWrBursts::3 7012 # Per bank write bursts +system.physmem.perBankWrBursts::4 7145 # Per bank write bursts +system.physmem.perBankWrBursts::5 7305 # Per bank write bursts system.physmem.perBankWrBursts::6 6890 # Per bank write bursts -system.physmem.perBankWrBursts::7 7170 # Per bank write bursts -system.physmem.perBankWrBursts::8 7244 # Per bank write bursts -system.physmem.perBankWrBursts::9 7072 # Per bank write bursts -system.physmem.perBankWrBursts::10 7215 # Per bank write bursts +system.physmem.perBankWrBursts::7 7164 # Per bank write bursts +system.physmem.perBankWrBursts::8 7246 # Per bank write bursts +system.physmem.perBankWrBursts::9 7071 # Per bank write bursts +system.physmem.perBankWrBursts::10 7213 # Per bank write bursts system.physmem.perBankWrBursts::11 7126 # Per bank write bursts system.physmem.perBankWrBursts::12 7072 # Per bank write bursts system.physmem.perBankWrBursts::13 7397 # Per bank write bursts -system.physmem.perBankWrBursts::14 7353 # Per bank write bursts +system.physmem.perBankWrBursts::14 7351 # Per bank write bursts system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60093907500 # Total gap between requests +system.physmem.totGap 61709200500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165736 # Read request sizes (log2) +system.physmem.readPktSize::6 165740 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115250 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115251 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6962 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,124 +194,134 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads -system.physmem.totQLat 1892978500 # Total ticks spent queuing -system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads +system.physmem.totQLat 3617300750 # Total ticks spent queuing +system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.34 # Data bus utilization in percentage -system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing -system.physmem.readRowHits 144145 # Number of row buffer hits during reads -system.physmem.writeRowHits 89685 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes -system.physmem.avgGap 213867.98 # Average gap between requests -system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ) -system.physmem_0.averagePower 711.117850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ) -system.physmem_1.averagePower 713.246634 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14696108 # Number of BP lookups -system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits +system.physmem.busUtil 2.28 # Data bus utilization in percentage +system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing +system.physmem.readRowHits 144262 # Number of row buffer hits during reads +system.physmem.writeRowHits 89468 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes +system.physmem.avgGap 219612.73 # Average gap between requests +system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ) +system.physmem_0.averagePower 393.299410 # Core power per rank (mW) +system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states +system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ) +system.physmem_1.averagePower 400.858918 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14696527 # Number of BP lookups +system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20579333 # DTB read hits -system.cpu.dtb.read_misses 95423 # DTB read misses +system.cpu.dtb.read_hits 20579387 # DTB read hits +system.cpu.dtb.read_misses 95377 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674756 # DTB read accesses -system.cpu.dtb.write_hits 14666035 # DTB write hits +system.cpu.dtb.read_accesses 20674764 # DTB read accesses +system.cpu.dtb.write_hits 14666029 # DTB write hits system.cpu.dtb.write_misses 8840 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674875 # DTB write accesses -system.cpu.dtb.data_hits 35245368 # DTB hits -system.cpu.dtb.data_misses 104263 # DTB misses +system.cpu.dtb.write_accesses 14674869 # DTB write accesses +system.cpu.dtb.data_hits 35245416 # DTB hits +system.cpu.dtb.data_misses 104217 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35349631 # DTB accesses -system.cpu.itb.fetch_hits 25649355 # ITB hits -system.cpu.itb.fetch_misses 5175 # ITB misses +system.cpu.dtb.data_accesses 35349633 # DTB accesses +system.cpu.itb.fetch_hits 25650137 # ITB hits +system.cpu.itb.fetch_misses 5179 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25654530 # ITB accesses +system.cpu.itb.fetch_accesses 25655316 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,16 +335,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120187862 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 123418448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359006 # CPI: cycles per instruction -system.cpu.ipc 0.735832 # IPC: instructions per cycle +system.cpu.cpi 1.395535 # CPI: cycles per instruction +system.cpu.ipc 0.716571 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -370,106 +380,106 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked -system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200806 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy +system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked +system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200809 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits -system.cpu.dcache.overall_hits::total 34648172 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses -system.cpu.dcache.overall_misses::total 341638 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits +system.cpu.dcache.overall_hits::total 34647996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses +system.cpu.dcache.overall_misses::total 341611 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168116 # number of writebacks -system.cpu.dcache.writebacks::total 168116 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 194 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136542 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136736 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136736 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136736 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -478,338 +488,338 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44391.652401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44391.652401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76579.203438 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76579.203438 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66944.239197 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1033 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 801 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90398.558530 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107171.897810 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107171.897810 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94563.145481 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94563.145481 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 91794.924008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 91794.924008 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115251 # number of writebacks -system.cpu.l2cache.writebacks::total 115251 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 115252 # number of writebacks +system.cpu.l2cache.writebacks::total 115252 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6849 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6849 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27980 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27980 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6849 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158888 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165737 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6849 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158888 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165737 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9336833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9336833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 494657000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 494657000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2000469500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2000469500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 494657000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11337303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11831960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 494657000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11337303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11831960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6850 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6850 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27983 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27983 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6850 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158891 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165741 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6850 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158891 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165741 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10524814500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10524814500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 665637500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 665637500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2366330500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2366330500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 665637500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12891145000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13556782500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 665637500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12891145000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13556782500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043914 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459274 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459274 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135276 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135280 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34828 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution -system.membus.trans_dist::CleanEvict 15883 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34832 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution +system.membus.trans_dist::CleanEvict 15886 # Transaction distribution system.membus.trans_dist::ReadExReq 130908 # Transaction distribution system.membus.trans_dist::ReadExResp 130908 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165736 # Request fanout histogram +system.membus.snoop_fanout::samples 165740 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165736 # Request fanout histogram -system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +system.membus.snoop_fanout::total 165740 # Request fanout histogram +system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |