diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 1581 |
1 files changed, 793 insertions, 788 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index f889e2dcc..5daeaeb73 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,104 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024977 # Number of seconds simulated -sim_ticks 24977022500 # Number of ticks simulated -final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024874 # Number of seconds simulated +sim_ticks 24873813500 # Number of ticks simulated +final_tick 24873813500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179872 # Simulator instruction rate (inst/s) -host_op_rate 179872 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56446381 # Simulator tick rate (ticks/s) -host_mem_usage 238148 # Number of bytes of host memory used -host_seconds 442.49 # Real time elapsed on the host +host_inst_rate 165069 # Simulator instruction rate (inst/s) +host_op_rate 165069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51586823 # Simulator tick rate (ticks/s) +host_mem_usage 265596 # Number of bytes of host memory used +host_seconds 482.17 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 489600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10643136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7650 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166305 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19617390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 406515068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 426132458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19617390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19617390 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 292149475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 292149475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 292149475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166305 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 114016 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 166305 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 114016 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 10643520 # Total number of bytes read from memory -system.physmem.bytesWritten 7297024 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10060 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10548 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10226 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10277 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10618 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10625 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24976988500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 0 # Categorize read packet sizes -system.physmem.readPktSize::3 0 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166305 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 0 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114016 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.num_reads::total 166299 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19683351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 408201822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 427885173 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19683351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19683351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 293364264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 293364264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 293364264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19683351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 408201822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 721249438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166299 # Number of read requests accepted +system.physmem.writeReqs 114017 # Number of write requests accepted +system.physmem.readBursts 166299 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10643008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7296896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10643136 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10432 # Per bank write bursts +system.physmem.perBankRdBursts::1 10453 # Per bank write bursts +system.physmem.perBankRdBursts::2 10310 # Per bank write bursts +system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::4 10431 # Per bank write bursts +system.physmem.perBankRdBursts::5 10400 # Per bank write bursts +system.physmem.perBankRdBursts::6 9846 # Per bank write bursts +system.physmem.perBankRdBursts::7 10320 # Per bank write bursts +system.physmem.perBankRdBursts::8 10615 # Per bank write bursts +system.physmem.perBankRdBursts::9 10642 # Per bank write bursts +system.physmem.perBankRdBursts::10 10549 # Per bank write bursts +system.physmem.perBankRdBursts::11 10234 # Per bank write bursts +system.physmem.perBankRdBursts::12 10280 # Per bank write bursts +system.physmem.perBankRdBursts::13 10614 # Per bank write bursts +system.physmem.perBankRdBursts::14 10489 # Per bank write bursts +system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankWrBursts::0 7083 # Per bank write bursts +system.physmem.perBankWrBursts::1 7257 # Per bank write bursts +system.physmem.perBankWrBursts::2 7256 # Per bank write bursts +system.physmem.perBankWrBursts::3 6997 # Per bank write bursts +system.physmem.perBankWrBursts::4 7126 # Per bank write bursts +system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 7093 # Per bank write bursts +system.physmem.perBankWrBursts::8 7227 # Per bank write bursts +system.physmem.perBankWrBursts::9 6941 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::13 7287 # Per bank write bursts +system.physmem.perBankWrBursts::14 7286 # Per bank write bursts +system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 24873779500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 166299 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 114017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71536 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 31949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -125,230 +127,233 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49952 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.130045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.640646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 741.801736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 20814 41.67% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7820 15.66% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4185 8.38% 65.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3013 6.03% 71.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2148 4.30% 76.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1700 3.40% 79.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1301 2.60% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1098 2.20% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 776 1.55% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 657 1.32% 87.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 496 0.99% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 568 1.14% 89.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 406 0.81% 90.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 302 0.60% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 268 0.54% 91.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 357 0.71% 91.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 241 0.48% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 170 0.34% 92.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 145 0.29% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 323 0.65% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 351 0.70% 94.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 146 0.29% 94.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 301 0.60% 95.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 689 1.38% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 236 0.47% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 76 0.15% 97.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 36 0.07% 97.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 184 0.37% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 89 0.18% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 34 0.07% 97.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 40 0.08% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 93 0.19% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 64 0.13% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 19 0.04% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 44 0.09% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 19 0.04% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 19 0.04% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 36 0.07% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 21 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 12 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 20 0.04% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 10 0.02% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 10 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 15 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 9 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 8 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 8 0.02% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 9 0.02% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 10 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 5 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 11 0.02% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 7 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 169 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49952 # Bytes accessed per row activation -system.physmem.totQLat 6557959000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8953517750 # Sum of mem lat for all requests -system.physmem.totBusLat 831510000 # Total cycles spent in databus access -system.physmem.totBankLat 1564048750 # Total cycles spent in bank access -system.physmem.avgQLat 39434.04 # Average queueing delay per request -system.physmem.avgBankLat 9404.87 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53838.91 # Average memory access latency -system.physmem.avgRdBW 426.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 292.15 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 426.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 292.15 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.61 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.36 # Average read queue length over time -system.physmem.avgWrQLen 9.86 # Average write queue length over time -system.physmem.readRowHits 154145 # Number of row buffer hits during reads -system.physmem.writeRowHits 76216 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.85 # Row buffer hit rate for writes -system.physmem.avgGap 89101.38 # Average gap between requests -system.membus.throughput 718281933 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35508 # Transaction distribution -system.membus.trans_dist::ReadResp 35508 # Transaction distribution -system.membus.trans_dist::Writeback 114016 # Transaction distribution -system.membus.trans_dist::ReadExReq 130797 # Transaction distribution -system.membus.trans_dist::ReadExResp 130797 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446626 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446626 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940544 # Total data (bytes) +system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.243169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.634788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 670.449971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 22509 43.19% 43.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7813 14.99% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4251 8.16% 66.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3108 5.96% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2227 4.27% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1678 3.22% 79.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1376 2.64% 82.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1167 2.24% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 816 1.57% 86.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 658 1.26% 87.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 508 0.97% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 506 0.97% 89.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 390 0.75% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 297 0.57% 90.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 306 0.59% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 440 0.84% 92.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 200 0.38% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 185 0.36% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 164 0.31% 93.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 351 0.67% 93.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 222 0.43% 94.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 266 0.51% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 128 0.25% 95.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 805 1.54% 96.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 220 0.42% 97.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 67 0.13% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 43 0.08% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 225 0.43% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 103 0.20% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.10% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 84 0.16% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 57 0.11% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 36 0.07% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 55 0.11% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 21 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 12 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 17 0.03% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 18 0.03% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 24 0.05% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 13 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 9 0.02% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 11 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 6 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 7 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 11 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 9 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 13 0.02% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 6 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 8 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 10 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 6 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 8 0.02% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 7 0.01% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 5 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 3 0.01% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 8 0.02% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation +system.physmem.totQLat 6321612000 # Total ticks spent queuing +system.physmem.totMemAccLat 8667027000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831485000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1513930000 # Total ticks spent accessing banks +system.physmem.avgQLat 38013.99 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9103.77 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 52117.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 427.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 293.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 427.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 293.36 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.63 # Data bus utilization in percentage +system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.68 # Average write queue length when enqueuing +system.physmem.readRowHits 152202 # Number of row buffer hits during reads +system.physmem.writeRowHits 75997 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.65 # Row buffer hit rate for writes +system.physmem.avgGap 88734.78 # Average gap between requests +system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.04 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 721249438 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35493 # Transaction distribution +system.membus.trans_dist::ReadResp 35493 # Transaction distribution +system.membus.trans_dist::Writeback 114017 # Transaction distribution +system.membus.trans_dist::ReadExReq 130806 # Transaction distribution +system.membus.trans_dist::ReadExResp 130806 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446615 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446615 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17940224 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940224 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242127000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1541382250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1539178500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) -system.cpu.branchPred.lookups 16531947 # Number of BP lookups -system.cpu.branchPred.condPredicted 10672978 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 414050 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11481292 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7335496 # Number of BTB hits +system.cpu.branchPred.lookups 16532535 # Number of BP lookups +system.cpu.branchPred.condPredicted 10677865 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 412540 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11187771 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7331268 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.890858 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1991572 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 40927 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.529300 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1986493 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41581 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22403443 # DTB read hits -system.cpu.dtb.read_misses 219972 # DTB read misses -system.cpu.dtb.read_acv 45 # DTB read access violations -system.cpu.dtb.read_accesses 22623415 # DTB read accesses -system.cpu.dtb.write_hits 15699616 # DTB write hits -system.cpu.dtb.write_misses 41064 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15740680 # DTB write accesses -system.cpu.dtb.data_hits 38103059 # DTB hits -system.cpu.dtb.data_misses 261036 # DTB misses -system.cpu.dtb.data_acv 46 # DTB access violations -system.cpu.dtb.data_accesses 38364095 # DTB accesses -system.cpu.itb.fetch_hits 13905618 # ITB hits -system.cpu.itb.fetch_misses 35229 # ITB misses +system.cpu.dtb.read_hits 22399036 # DTB read hits +system.cpu.dtb.read_misses 220951 # DTB read misses +system.cpu.dtb.read_acv 40 # DTB read access violations +system.cpu.dtb.read_accesses 22619987 # DTB read accesses +system.cpu.dtb.write_hits 15703469 # DTB write hits +system.cpu.dtb.write_misses 40937 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 15744406 # DTB write accesses +system.cpu.dtb.data_hits 38102505 # DTB hits +system.cpu.dtb.data_misses 261888 # DTB misses +system.cpu.dtb.data_acv 45 # DTB access violations +system.cpu.dtb.data_accesses 38364393 # DTB accesses +system.cpu.itb.fetch_hits 13899355 # ITB hits +system.cpu.itb.fetch_misses 34906 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13940847 # ITB accesses +system.cpu.itb.fetch_accesses 13934261 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -362,98 +367,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49954048 # number of cpu cycles simulated +system.cpu.numCycles 49747630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15782352 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105305571 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16531947 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9327068 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19535430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1996105 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7525610 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314470 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13905618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 207845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44615196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.360307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15785028 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105317585 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16532535 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9317761 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19533050 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1994568 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7608263 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7898 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 310217 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13899355 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 208294 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44693564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.356437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120216 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25079766 56.21% 56.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1526701 3.42% 59.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1368492 3.07% 62.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1511592 3.39% 66.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4137930 9.27% 75.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1849422 4.15% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 676249 1.52% 81.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069566 2.40% 83.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7395478 16.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25160514 56.30% 56.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1525973 3.41% 59.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1366086 3.06% 62.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510374 3.38% 66.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4139884 9.26% 75.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1847459 4.13% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 671184 1.50% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1072337 2.40% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7399753 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44615196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.330943 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.108049 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16870832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7056928 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18547803 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 794977 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743758 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107019 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103586885 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 307942 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17339272 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4755583 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85639 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18836599 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2253447 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102335224 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2492 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122982558 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319719 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44693564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.332328 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.117037 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16872770 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7137515 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18556178 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 782832 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344269 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743968 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106931 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103592319 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 303311 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344269 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17342531 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4850765 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84983 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18829662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2241354 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102344042 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 512 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2574 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2122740 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61629886 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123330813 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123015128 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 315684 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5530 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4823408 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23239875 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16264209 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1185310 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 465013 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90722071 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5344 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88415019 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95015 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10694229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4666218 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 761 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44615196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981724 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109954 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9083005 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5524 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5522 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4827061 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23228738 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16269123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1186061 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 452179 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90719899 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5267 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88414674 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10680066 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4660295 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 684 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44693564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.978242 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.110252 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16409410 36.78% 36.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6866152 15.39% 52.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5567351 12.48% 64.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4772569 10.70% 75.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4725060 10.59% 85.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2625070 5.88% 91.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1917083 4.30% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1291638 2.90% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 440863 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16504766 36.93% 36.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6842289 15.31% 52.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5576642 12.48% 64.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4760179 10.65% 75.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4735432 10.60% 85.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2623142 5.87% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1921443 4.30% 96.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1284900 2.87% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 444771 1.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44615196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44693564 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126842 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126888 6.81% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available @@ -482,19 +487,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 784071 42.12% 48.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 950643 51.07% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 786366 42.17% 48.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 951332 51.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49344695 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43834 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49347874 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43826 0.05% 55.86% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121349 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121152 0.14% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38963 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 120827 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120926 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 58 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38966 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -516,84 +521,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22855764 25.85% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15889119 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848043 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15894065 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88415019 # Type of FU issued -system.cpu.iq.rate 1.769927 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1861556 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021055 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222796879 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101023469 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86533748 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 604926 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415943 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294379 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89974024 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302551 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1471412 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88414674 # Type of FU issued +system.cpu.iq.rate 1.777264 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1864586 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021089 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222880329 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101013312 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86537625 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 602080 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 409925 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89978136 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301124 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1470512 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2963237 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4955 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18224 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1650832 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2952100 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4699 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18249 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655746 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2867 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 96301 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2987 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 95590 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344656 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3651094 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 72855 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100203758 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 216158 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23239875 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16264209 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5344 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49772 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6561 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18224 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192723 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161669 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 354392 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87578159 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22626447 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 836860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344269 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3728175 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74875 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100203568 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23228738 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16269123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5267 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49826 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6538 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18249 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 191969 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160202 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 352171 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87579420 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22623199 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 835254 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9476343 # number of nop insts executed -system.cpu.iew.exec_refs 38367436 # number of memory reference insts executed -system.cpu.iew.exec_branches 15087087 # Number of branches executed -system.cpu.iew.exec_stores 15740989 # Number of stores executed -system.cpu.iew.exec_rate 1.753174 # Inst execution rate -system.cpu.iew.wb_sent 87216851 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86828127 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33345535 # num instructions producing a value -system.cpu.iew.wb_consumers 43468305 # num instructions consuming a value +system.cpu.iew.exec_nop 9478402 # number of nop insts executed +system.cpu.iew.exec_refs 38367932 # number of memory reference insts executed +system.cpu.iew.exec_branches 15082234 # Number of branches executed +system.cpu.iew.exec_stores 15744733 # Number of stores executed +system.cpu.iew.exec_rate 1.760474 # Inst execution rate +system.cpu.iew.wb_sent 87221630 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86831789 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33348400 # num instructions producing a value +system.cpu.iew.wb_consumers 43473071 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.738160 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767123 # average fanout of values written-back +system.cpu.iew.wb_rate 1.745446 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767105 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8869178 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8866636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 309326 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43270540 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.041589 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791914 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 307777 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43349295 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.037880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791190 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20425554 47.20% 47.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7044262 16.28% 63.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3374707 7.80% 71.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2054728 4.75% 76.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2036437 4.71% 80.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1166697 2.70% 83.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108378 2.56% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 724905 1.68% 87.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5334872 12.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20524240 47.35% 47.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7032147 16.22% 63.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3350548 7.73% 71.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2057076 4.75% 76.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2049777 4.73% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1169910 2.70% 83.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1109421 2.56% 86.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718391 1.66% 87.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5337785 12.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43270540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43349295 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,212 +609,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5334872 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5337785 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133828176 # The number of ROB reads -system.cpu.rob.rob_writes 195767077 # The number of ROB writes -system.cpu.timesIdled 83938 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5338852 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133901476 # The number of ROB reads +system.cpu.rob.rob_writes 195761663 # The number of ROB writes +system.cpu.timesIdled 83653 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5054066 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.627628 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.627628 # CPI: Total CPI of All Threads -system.cpu.ipc 1.593299 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.593299 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115893073 # number of integer regfile reads -system.cpu.int_regfile_writes 57500612 # number of integer regfile writes -system.cpu.fp_regfile_reads 249654 # number of floating regfile reads -system.cpu.fp_regfile_writes 240130 # number of floating regfile writes -system.cpu.misc_regfile_reads 38049 # number of misc regfile reads +system.cpu.cpi 0.625035 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.625035 # CPI: Total CPI of All Threads +system.cpu.ipc 1.599911 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.599911 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115904116 # number of integer regfile reads +system.cpu.int_regfile_writes 57506232 # number of integer regfile writes +system.cpu.fp_regfile_reads 249599 # number of floating regfile reads +system.cpu.fp_regfile_writes 239957 # number of floating regfile writes +system.cpu.misc_regfile_reads 38110 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1198592827 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580061 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 766612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5969600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29937280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes) +system.cpu.toL2Bus.throughput 1204474416 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155768 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168935 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143420 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143420 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187275 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 767312 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5992768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29959872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29959872 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402997000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141571734 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141831227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326236500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91227 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13799737 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13799737 # number of overall hits -system.cpu.icache.overall_hits::total 13799737 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105880 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105880 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105880 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105880 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105880 # number of overall misses -system.cpu.icache.overall_misses::total 105880 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2067336982 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2067336982 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2067336982 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2067336982 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2067336982 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2067336982 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13905617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13905617 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13905617 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13905617 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13905617 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13905617 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007614 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007614 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78465.690759 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100362.857629 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 99355.429946 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -818,164 +823,164 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114016 # number of writebacks -system.cpu.l2cache.writebacks::total 114016 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65817.932296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88004.844027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86984.085989 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201470 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105301044001 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105301044001 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105301044001 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20878626 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20878626 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35496749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35496749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35496749 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35496749 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036813 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036813 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036813 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036813 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59595.145382 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59595.145382 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87144.823113 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 87144.823113 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81505.864935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81505.864935 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5253118 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 160 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112229 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 55 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35492003 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35492003 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35492003 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35492003 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036820 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036820 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036820 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036820 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60927.246150 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60927.246150 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85635.179837 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85635.179837 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80577.769786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80577.769786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80577.769786 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5154697 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.807135 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.949822 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks -system.cpu.dcache.writebacks::total 168929 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205307 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205307 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895863 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101170 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101170 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101170 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101170 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62160 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62160 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205566 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205566 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2516687000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2516687000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14340164994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14340164994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16856851994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16856851994 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16856851994 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16856851994 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002977 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.writebacks::writebacks 168935 # number of writebacks +system.cpu.dcache.writebacks::total 168935 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205357 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205357 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895917 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895917 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101274 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101274 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101274 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101274 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62134 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62134 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205551 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205551 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205551 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205551 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2523454750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2523454750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14076498244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14076498244 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16599952994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16599952994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16599952994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.242600 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.242600 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99996.966612 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99996.966612 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40613.106351 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40613.106351 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98150.834587 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98150.834587 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80758.317858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80758.317858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |