diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt | 388 |
1 files changed, 194 insertions, 194 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 026fc581b..9facba206 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.134277 # Number of seconds simulated -sim_ticks 134276988000 # Number of ticks simulated -final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.134037 # Number of seconds simulated +sim_ticks 134036748000 # Number of ticks simulated +final_tick 134036748000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1431789 # Simulator instruction rate (inst/s) -host_op_rate 1431788 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2176303972 # Simulator tick rate (ticks/s) -host_mem_usage 222880 # Number of bytes of host memory used -host_seconds 61.70 # Real time elapsed on the host +host_inst_rate 2004374 # Simulator instruction rate (inst/s) +host_op_rate 2004373 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3041175629 # Simulator tick rate (ticks/s) +host_mem_usage 226164 # Number of bytes of host memory used +host_seconds 44.07 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 558272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10563648 # Number of bytes read from this memory -system.physmem.bytes_read::total 11121920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 558272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 558272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7712384 # Number of bytes written to this memory -system.physmem.bytes_written::total 7712384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8723 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 165057 # Number of read requests responded to by this memory -system.physmem.num_reads::total 173780 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120506 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120506 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4157615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 78670576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 82828191 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4157615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4157615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 57436379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 57436379 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 57436379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4157615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 78670576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140264570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10270528 # Number of bytes read from this memory +system.physmem.bytes_read::total 10755840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 485312 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 485312 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7421120 # Number of bytes written to this memory +system.physmem.bytes_written::total 7421120 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160477 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3620738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76624718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 80245456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3620738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3620738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 55366309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 55366309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 55366309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3620738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76624718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 135611765 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 268553976 # number of cpu cycles simulated +system.cpu.numCycles 268073496 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 268553976 # Number of busy cycles +system.cpu.num_busy_cycles 268073496 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.404551 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.539157 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.404551 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913772 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913772 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1871.539157 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913837 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913837 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1436470000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1436470000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1436470000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1436470000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1436470000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1436470000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1388590000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1388590000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1388590000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1388590000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1388590000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1388590000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18793.107960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18793.107960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18793.107960 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18166.701554 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18166.701554 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18166.701554 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18166.701554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18166.701554 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18166.701554 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1207162000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1207162000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1207162000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1207162000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1207162000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1207162000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159282000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1159282000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159282000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1159282000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159282000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1159282000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15793.107960 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15793.107960 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15166.701554 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15166.701554 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15166.701554 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15166.701554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15166.701554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15166.701554 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.827650 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.858373 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995815 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995815 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4078.827650 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995808 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995808 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2261000000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2261000000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7532210000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7532210000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9793210000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9793210000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9793210000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9793210000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2087582000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2087582000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7513268000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7513268000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9600850000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9600850000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9600850000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9600850000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 37208.307277 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 52460.753040 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47925.116470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47925.116470 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34354.441629 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34354.441629 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52328.824750 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 52328.824750 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46983.762675 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46983.762675 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46983.762675 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46983.762675 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 161222 # number of writebacks -system.cpu.dcache.writebacks::total 161222 # number of writebacks +system.cpu.dcache.writebacks::writebacks 165828 # number of writebacks +system.cpu.dcache.writebacks::total 165828 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078702000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7101476000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7101476000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9180178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9180178000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9180178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9180178000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905284000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905284000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082534000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082534000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987818000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8987818000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987818000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8987818000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34208.307277 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49460.753040 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44925.116470 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.441629 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31354.441629 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.824750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.824750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43983.762675 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43983.762675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43983.762675 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43983.762675 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 147405 # number of replacements -system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use -system.cpu.l2cache.total_refs 122958 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 135625 # number of replacements +system.cpu.l2cache.tagsinuse 29002.202656 # Cycle average of tags in use +system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15808.263557 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1305.254425 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1501.295351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.482430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.039833 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.568079 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 67713 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 27188 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 94901 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 161222 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 161222 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12099 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12099 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 67713 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 39287 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 107000 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 67713 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 39287 # number of overall hits -system.cpu.l2cache.overall_hits::total 107000 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8723 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 42301 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131479 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131479 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8723 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 165057 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 173780 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8723 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 165057 # number of overall misses -system.cpu.l2cache.overall_misses::total 173780 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 453596000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1746056000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2199652000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6836908000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6836908000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 453596000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8582964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9036560000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 453596000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8582964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9036560000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 25777.846112 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1647.476120 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1576.880424 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.786677 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.050277 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.048123 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.885077 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 68853 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31317 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 100170 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 165828 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 165828 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12550 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12550 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 68853 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 43867 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 112720 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 68853 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 43867 # number of overall hits +system.cpu.l2cache.overall_hits::total 112720 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7583 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 29449 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37032 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131028 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131028 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7583 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 160477 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168060 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7583 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 160477 # number of overall misses +system.cpu.l2cache.overall_misses::total 168060 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 394316000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1531348000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1925664000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6813456000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6813456000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 394316000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8344804000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8739120000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 394316000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8344804000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8739120000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 161222 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 161222 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 165828 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 165828 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses @@ -328,17 +328,17 @@ system.cpu.l2cache.demand_accesses::total 280780 # n system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.308312 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.915732 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.618919 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.618919 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099207 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.484630 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.269909 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912591 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912591 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099207 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.785328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.598547 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099207 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.785328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.598547 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -358,41 +358,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 120506 # number of writebacks -system.cpu.l2cache.writebacks::total 120506 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8723 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 42301 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131479 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5259160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 348920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6602280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6951200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 348920000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308312 # 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