diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha')
4 files changed, 1231 insertions, 1153 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index f3edc5948..ca907eb24 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043459 # Number of seconds simulated -sim_ticks 43458818000 # Number of ticks simulated -final_tick 43458818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043473 # Number of seconds simulated +sim_ticks 43472869000 # Number of ticks simulated +final_tick 43472869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114678 # Simulator instruction rate (inst/s) -host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56415550 # Simulator tick rate (ticks/s) -host_mem_usage 273516 # Number of bytes of host memory used -host_seconds 770.33 # Real time elapsed on the host +host_inst_rate 112027 # Simulator instruction rate (inst/s) +host_op_rate 112027 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55129043 # Simulator tick rate (ticks/s) +host_mem_usage 274568 # Number of bytes of host memory used +host_seconds 788.57 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,31 +25,31 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10460294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 233286787 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 243747080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10460294 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10460294 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 167878657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 167878657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 167878657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10460294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 233286787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 411625737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10456913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 233211385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 243668298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10456913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10456913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 167824396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 167824396 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 167824396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10456913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 233211385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 411492694 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165515 # Number of read requests accepted system.physmem.writeReqs 113997 # Number of write requests accepted system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10592576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294400 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 10592320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue +system.physmem.bytesWritten 7293824 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10379 # Per bank write bursts -system.physmem.perBankRdBursts::1 10437 # Per bank write bursts +system.physmem.perBankRdBursts::1 10436 # Per bank write bursts system.physmem.perBankRdBursts::2 10256 # Per bank write bursts system.physmem.perBankRdBursts::3 10015 # Per bank write bursts system.physmem.perBankRdBursts::4 10350 # Per bank write bursts @@ -58,9 +58,9 @@ system.physmem.perBankRdBursts::6 9796 # Pe system.physmem.perBankRdBursts::7 10273 # Per bank write bursts system.physmem.perBankRdBursts::8 10509 # Per bank write bursts system.physmem.perBankRdBursts::9 10590 # Per bank write bursts -system.physmem.perBankRdBursts::10 10477 # Per bank write bursts +system.physmem.perBankRdBursts::10 10475 # Per bank write bursts system.physmem.perBankRdBursts::11 10188 # Per bank write bursts -system.physmem.perBankRdBursts::12 10236 # Per bank write bursts +system.physmem.perBankRdBursts::12 10235 # Per bank write bursts system.physmem.perBankRdBursts::13 10580 # Per bank write bursts system.physmem.perBankRdBursts::14 10468 # Per bank write bursts system.physmem.perBankRdBursts::15 10593 # Per bank write bursts @@ -71,18 +71,18 @@ system.physmem.perBankWrBursts::3 6998 # Pe system.physmem.perBankWrBursts::4 7125 # Per bank write bursts system.physmem.perBankWrBursts::5 7170 # Per bank write bursts system.physmem.perBankWrBursts::6 6769 # Per bank write bursts -system.physmem.perBankWrBursts::7 7092 # Per bank write bursts -system.physmem.perBankWrBursts::8 7216 # Per bank write bursts +system.physmem.perBankWrBursts::7 7083 # Per bank write bursts +system.physmem.perBankWrBursts::8 7217 # Per bank write bursts system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7083 # Per bank write bursts +system.physmem.perBankWrBursts::10 7081 # Per bank write bursts system.physmem.perBankWrBursts::11 6989 # Per bank write bursts system.physmem.perBankWrBursts::12 6963 # Per bank write bursts system.physmem.perBankWrBursts::13 7284 # Per bank write bursts -system.physmem.perBankWrBursts::14 7281 # Per bank write bursts +system.physmem.perBankWrBursts::14 7282 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 43458797000 # Total gap between requests +system.physmem.totGap 43472848000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 113997 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 69517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,45 +144,45 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -193,83 +193,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.014950 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.118388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.708548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12628 30.21% 30.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8632 20.65% 50.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4415 10.56% 61.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2749 6.58% 67.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2263 5.41% 73.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1680 4.02% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1442 3.45% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1629 3.90% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6369 15.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41807 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6909 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.954842 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 351.043824 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6907 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52007 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.898321 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.122220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.471226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18183 34.96% 34.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10752 20.67% 55.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5531 10.64% 66.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3167 6.09% 72.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2729 5.25% 77.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1801 3.46% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1676 3.22% 84.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1325 2.55% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6843 13.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52007 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.806818 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 349.983272 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6951 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6909 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.496599 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.404036 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.150839 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6289 91.03% 91.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 13 0.19% 91.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 61 0.88% 92.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 166 2.40% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 127 1.84% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 73 1.06% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 63 0.91% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 29 0.42% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.26% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.17% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.10% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.04% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.03% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.04% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 3 0.04% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 19 0.28% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 5 0.07% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6909 # Writes before turning the bus around for reads -system.physmem.totQLat 5306478250 # Total ticks spent queuing -system.physmem.totMemAccLat 7800537000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 827545000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1666513750 # Total ticks spent accessing banks -system.physmem.avgQLat 32061.57 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10069.02 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6952 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.395339 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.363988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.079809 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5950 85.60% 85.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.50% 86.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 555 7.98% 94.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 213 3.06% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 101 1.45% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 56 0.81% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 23 0.33% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 12 0.17% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6951 # Writes before turning the bus around for reads +system.physmem.totQLat 4829573500 # Total ticks spent queuing +system.physmem.totMemAccLat 7932792250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827525000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29180.83 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47130.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 243.74 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 167.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 243.75 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 167.88 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47930.83 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 243.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 167.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 243.67 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 167.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.22 # Data bus utilization in percentage +system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.busUtilRead 1.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.31 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing -system.physmem.readRowHits 144461 # Number of row buffer hits during reads -system.physmem.writeRowHits 82889 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.71 # Row buffer hit rate for writes -system.physmem.avgGap 155480.97 # Average gap between requests -system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 10.25 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 411625737 # Throughput (bytes/s) +system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 145183 # Number of row buffer hits during reads +system.physmem.writeRowHits 82273 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.17 # Row buffer hit rate for writes +system.physmem.avgGap 155531.24 # Average gap between requests +system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 26086323250 # Time in different power states +system.physmem.memoryStateTime::REF 1451580000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 15933004250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 411492694 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34625 # Transaction distribution system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution @@ -281,40 +269,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1219845000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1219071000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1520840750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1523545750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18742760 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318400 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18742718 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318358 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15507492 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 15507357 # Number of BTB lookups system.cpu.branchPred.BTBHits 4664025 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.075947 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.076208 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277780 # DTB read hits +system.cpu.dtb.read_hits 20277728 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367928 # DTB read accesses -system.cpu.dtb.write_hits 14729056 # DTB write hits +system.cpu.dtb.read_accesses 20367876 # DTB read accesses +system.cpu.dtb.write_hits 14728971 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736308 # DTB write accesses -system.cpu.dtb.data_hits 35006836 # DTB hits +system.cpu.dtb.write_accesses 14736223 # DTB write accesses +system.cpu.dtb.data_hits 35006699 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35104236 # DTB accesses -system.cpu.itb.fetch_hits 12367757 # ITB hits +system.cpu.dtb.data_accesses 35104099 # DTB accesses +system.cpu.itb.fetch_hits 12367762 # ITB hits system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378778 # ITB accesses +system.cpu.itb.fetch_accesses 12378783 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -328,34 +316,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 86917637 # number of cpu cycles simulated +system.cpu.numCycles 86945739 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 8074236 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668524 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74162131 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 10668482 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74162124 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126481381 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 126481374 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14174243 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 14174248 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 35060070 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777932 # Number of Instructions Executed. +system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77191042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77212885 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 229429 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17341864 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69575773 # Number of cycles cpu stages are processed. -system.cpu.activity 80.047934 # Percentage of cycles cpu is active +system.cpu.timesIdled 241035 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17370075 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575664 # Number of cycles cpu stages are processed. +system.cpu.activity 80.021936 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -367,120 +355,120 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.983891 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.984210 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.983891 # CPI: Total CPI of All Threads -system.cpu.ipc 1.016372 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.984210 # CPI: Total CPI of All Threads +system.cpu.ipc 1.016044 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.016372 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34262012 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52655625 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.581059 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44462439 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42455198 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.845320 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 43887105 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43030532 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.507250 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 64797015 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120622 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.450096 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 40875399 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46042238 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.972262 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.016044 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34290146 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655593 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.561442 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44490597 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455142 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.829468 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 43915285 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030454 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.491159 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 64825125 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120614 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.441861 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40903528 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46042211 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.955109 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1905.831723 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250503 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1906.099937 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250492 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760337 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760209 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1905.831723 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930582 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930582 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1906.099937 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930713 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930713 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 24821911 # Number of tag accesses -system.cpu.icache.tags.data_accesses 24821911 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 12250503 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250503 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250503 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250503 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250503 # number of overall hits -system.cpu.icache.overall_hits::total 12250503 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117244 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117244 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117244 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117244 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117244 # number of overall misses -system.cpu.icache.overall_misses::total 117244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1999895234 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1999895234 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1999895234 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1999895234 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1999895234 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1999895234 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367747 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367747 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367747 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009480 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17057.548651 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17057.548651 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17057.548651 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17057.548651 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 343 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 24821923 # Number of tag accesses +system.cpu.icache.tags.data_accesses 24821923 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 12250492 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250492 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250492 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250492 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250492 # number of overall hits +system.cpu.icache.overall_hits::total 12250492 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117261 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117261 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117261 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117261 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117261 # number of overall misses +system.cpu.icache.overall_misses::total 117261 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1989588981 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1989588981 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1989588981 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1989588981 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1989588981 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1989588981 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367753 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367753 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367753 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367753 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367753 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367753 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009481 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009481 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009481 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009481 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009481 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009481 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16967.184153 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16967.184153 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16967.184153 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16967.184153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16967.184153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16967.184153 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.866667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 23.133333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30827 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30827 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30827 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30827 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30827 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30827 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30844 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30844 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30844 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30844 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30844 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30844 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1419611513 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1419611513 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1419611513 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1419611513 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1419611513 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1419611513 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1409598264 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1409598264 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1409598264 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1409598264 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1409598264 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1409598264 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16427.456554 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16427.456554 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16311.585267 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16311.585267 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16311.585267 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16311.585267 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16311.585267 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16311.585267 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 676121104 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 675902573 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution @@ -496,28 +484,28 @@ system.cpu.toL2Bus.data_through_bus 29383424 # To system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 130829487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 130854736 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 323146469 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 326587968 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30877.243576 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30879.620467 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27092.654478 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.905024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1776.684074 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.826802 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061276 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.054220 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.942299 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27087.517417 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.809532 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1783.293518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.826645 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061304 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054422 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.942371 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17173 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13478 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17062 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13579 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3980348 # Number of tag accesses @@ -546,17 +534,17 @@ system.cpu.l2cache.demand_misses::total 165515 # nu system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses system.cpu.l2cache.overall_misses::total 165515 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 537407000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1972226500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2509633500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12899781250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12899781250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 537407000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14872007750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15409414750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 537407000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14872007750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15409414750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 527407000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2000529000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2527936000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12857601250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12857601250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 527407000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14858130250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15385537250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 527407000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14858130250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15385537250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses) @@ -581,17 +569,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.569242 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75659.158102 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71659.999273 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72480.389892 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98554.368172 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98554.368172 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 93099.808174 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 93099.808174 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74251.302267 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72688.358404 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73008.981949 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98232.112843 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98232.112843 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74251.302267 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93794.221713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 92955.546325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74251.302267 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93794.221713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 92955.546325 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -613,17 +601,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165515 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 448296500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1624855000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2073151500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11301062250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11301062250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448296500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12925917250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13374213750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448296500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12925917250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13374213750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 438280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1653149000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2091429000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11252735250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11252735250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12905884250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13344164250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12905884250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13344164250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses @@ -635,58 +623,58 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63113.684359 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59038.405639 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59874.411552 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86340.150126 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86340.150126 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61703.505561 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60066.455926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60402.281588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85970.931698 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85970.931698 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61703.505561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81470.369985 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80622.084101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61703.505561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81470.369985 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80622.084101 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 200251 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.081511 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33755026 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.191917 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33755204 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.184838 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 302612000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.081511 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995137 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995137 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 165.185709 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 301118000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.191917 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995164 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995164 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 922 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 933 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3099 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 69984377 # Number of tag accesses system.cpu.dcache.tags.data_accesses 69984377 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20180293 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180293 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574733 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574733 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33755026 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33755026 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33755026 # number of overall hits -system.cpu.dcache.overall_hits::total 33755026 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96345 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96345 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038644 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038644 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1134989 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1134989 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1134989 # number of overall misses -system.cpu.dcache.overall_misses::total 1134989 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4945314984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4945314984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 82211352380 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 82211352380 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 87156667364 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 87156667364 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 87156667364 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 87156667364 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 20180307 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180307 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574897 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574897 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33755204 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33755204 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33755204 # number of overall hits +system.cpu.dcache.overall_hits::total 33755204 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96331 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96331 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038480 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038480 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1134811 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1134811 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1134811 # number of overall misses +system.cpu.dcache.overall_misses::total 1134811 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5018382484 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5018382484 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 82442485122 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 82442485122 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 87460867606 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 87460867606 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 87460867606 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 87460867606 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -695,40 +683,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032530 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032530 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032530 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032530 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51329.233318 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51329.233318 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79152.580076 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79152.580076 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76790.759526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76790.759526 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5467849 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004751 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004751 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071064 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032525 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032525 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032525 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032525 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52095.197641 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52095.197641 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79387.648411 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79387.648411 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77070.866960 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77070.866960 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77070.866960 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77070.866960 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5473044 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116872 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.784936 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.883943 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks system.cpu.dcache.writebacks::total 168352 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35578 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35578 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895064 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895064 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930642 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930642 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930642 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930642 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35564 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35564 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 894900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 894900 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930464 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930464 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930464 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930464 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -737,14 +725,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2366861266 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2366861266 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13170287765 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13170287765 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15537149031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15537149031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15537149031 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15537149031 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395231766 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395231766 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13128048266 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13128048266 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15523280032 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15523280032 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15523280032 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15523280032 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -753,14 +741,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38949.779749 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38949.779749 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91727.871326 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91727.871326 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39416.653216 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39416.653216 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91433.683424 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91433.683424 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75965.294484 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75965.294484 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75965.294484 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75965.294484 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 7573bf6de..1536d4b0d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024671 # Number of seconds simulated -sim_ticks 24670906500 # Number of ticks simulated -final_tick 24670906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024636 # Number of seconds simulated +sim_ticks 24636200500 # Number of ticks simulated +final_tick 24636200500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168282 # Simulator instruction rate (inst/s) -host_op_rate 168282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52161952 # Simulator tick rate (ticks/s) -host_mem_usage 276592 # Number of bytes of host memory used -host_seconds 472.97 # Real time elapsed on the host +host_inst_rate 166481 # Simulator instruction rate (inst/s) +host_op_rate 166481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51531279 # Simulator tick rate (ticks/s) +host_mem_usage 277620 # Number of bytes of host memory used +host_seconds 478.08 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 489344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153856 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158654 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166300 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19834861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 411572068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 431406929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19834861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19834861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 295777052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 295777052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 295777052 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19834861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 411572068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 727183981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166300 # Number of read requests accepted -system.physmem.writeReqs 114017 # Number of write requests accepted -system.physmem.readBursts 166300 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10642752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7295296 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10643200 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 491136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153600 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 491136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 491136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296704 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296704 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7674 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158650 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166324 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114011 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114011 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19935542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 412141474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 432077016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19935542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19935542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 296178138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 296178138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 296178138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19935542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 412141474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 728255154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166324 # Number of read requests accepted +system.physmem.writeReqs 114011 # Number of write requests accepted +system.physmem.readBursts 166324 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114011 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10644224 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7295040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10644736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7296704 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10427 # Per bank write bursts -system.physmem.perBankRdBursts::1 10465 # Per bank write bursts -system.physmem.perBankRdBursts::2 10308 # Per bank write bursts -system.physmem.perBankRdBursts::3 10056 # Per bank write bursts -system.physmem.perBankRdBursts::4 10424 # Per bank write bursts -system.physmem.perBankRdBursts::5 10403 # Per bank write bursts -system.physmem.perBankRdBursts::6 9851 # Per bank write bursts -system.physmem.perBankRdBursts::7 10318 # Per bank write bursts -system.physmem.perBankRdBursts::8 10615 # Per bank write bursts +system.physmem.perBankRdBursts::0 10435 # Per bank write bursts +system.physmem.perBankRdBursts::1 10464 # Per bank write bursts +system.physmem.perBankRdBursts::2 10314 # Per bank write bursts +system.physmem.perBankRdBursts::3 10058 # Per bank write bursts +system.physmem.perBankRdBursts::4 10432 # Per bank write bursts +system.physmem.perBankRdBursts::5 10406 # Per bank write bursts +system.physmem.perBankRdBursts::6 9849 # Per bank write bursts +system.physmem.perBankRdBursts::7 10311 # Per bank write bursts +system.physmem.perBankRdBursts::8 10614 # Per bank write bursts system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10551 # Per bank write bursts -system.physmem.perBankRdBursts::11 10228 # Per bank write bursts -system.physmem.perBankRdBursts::12 10273 # Per bank write bursts +system.physmem.perBankRdBursts::10 10549 # Per bank write bursts +system.physmem.perBankRdBursts::11 10230 # Per bank write bursts +system.physmem.perBankRdBursts::12 10275 # Per bank write bursts system.physmem.perBankRdBursts::13 10619 # Per bank write bursts -system.physmem.perBankRdBursts::14 10486 # Per bank write bursts -system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankRdBursts::14 10489 # Per bank write bursts +system.physmem.perBankRdBursts::15 10628 # Per bank write bursts system.physmem.perBankWrBursts::0 7082 # Per bank write bursts -system.physmem.perBankWrBursts::1 7259 # Per bank write bursts +system.physmem.perBankWrBursts::1 7254 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts system.physmem.perBankWrBursts::5 7170 # Per bank write bursts -system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7086 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::6 6770 # Per bank write bursts +system.physmem.perBankWrBursts::7 7085 # Per bank write bursts +system.physmem.perBankWrBursts::8 7222 # Per bank write bursts system.physmem.perBankWrBursts::9 6941 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts -system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6963 # Per bank write bursts -system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::13 7286 # Per bank write bursts +system.physmem.perBankWrBursts::14 7286 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24670873000 # Total gap between requests +system.physmem.totGap 24636167000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166300 # Read request sizes (log2) +system.physmem.readPktSize::6 166324 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114017 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 69085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 53344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114011 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 69812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,45 +144,45 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8505 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -193,129 +193,114 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 376.488173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 224.222062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.745587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13435 31.07% 31.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8988 20.78% 51.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4626 10.70% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2682 6.20% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2451 5.67% 74.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1626 3.76% 78.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1548 3.58% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1315 3.04% 84.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6576 15.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43247 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6943 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.949301 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.898812 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6941 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 341.105360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.170415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.733138 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18652 35.47% 35.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10746 20.43% 55.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5782 10.99% 66.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3058 5.81% 72.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2757 5.24% 77.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1645 3.13% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1894 3.60% 84.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1108 2.11% 86.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6949 13.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52591 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.856692 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.122530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6970 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6943 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6943 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.417831 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.341311 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.942818 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6412 92.35% 92.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.20% 92.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 48 0.69% 93.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 135 1.94% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 111 1.60% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 69 0.99% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 62 0.89% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 19 0.27% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 14 0.20% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 9 0.13% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.04% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 6 0.09% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.07% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.06% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.01% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 4 0.06% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 2 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 10 0.14% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6943 # Writes before turning the bus around for reads -system.physmem.totQLat 5579601250 # Total ticks spent queuing -system.physmem.totMemAccLat 7987531250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831465000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1576465000 # Total ticks spent accessing banks -system.physmem.avgQLat 33552.83 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9480.04 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6971 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.351313 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.323948 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.004197 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6065 87.00% 87.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.43% 87.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 507 7.27% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 200 2.87% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 92 1.32% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 44 0.63% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 23 0.33% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 4 0.06% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 3 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6971 # Writes before turning the bus around for reads +system.physmem.totQLat 4932812500 # Total ticks spent queuing +system.physmem.totMemAccLat 8051237500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831580000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29659.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48032.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 431.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 295.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 431.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 295.78 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48409.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 432.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 296.11 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 432.08 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 296.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.68 # Data bus utilization in percentage -system.physmem.busUtilRead 3.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 5.69 # Data bus utilization in percentage +system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 2.31 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing -system.physmem.readRowHits 144952 # Number of row buffer hits during reads -system.physmem.writeRowHits 82533 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.39 # Row buffer hit rate for writes -system.physmem.avgGap 88010.62 # Average gap between requests -system.physmem.pageHitRate 81.15 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 12.46 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 727183981 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35502 # Transaction distribution -system.membus.trans_dist::ReadResp 35502 # Transaction distribution -system.membus.trans_dist::Writeback 114017 # Transaction distribution -system.membus.trans_dist::ReadExReq 130798 # Transaction distribution -system.membus.trans_dist::ReadExResp 130798 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446617 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17940288 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940288 # Total data (bytes) +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 145935 # Number of row buffer hits during reads +system.physmem.writeRowHits 81773 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.75 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.72 # Row buffer hit rate for writes +system.physmem.avgGap 87881.17 # Average gap between requests +system.physmem.pageHitRate 81.23 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 10235619000 # Time in different power states +system.physmem.memoryStateTime::REF 822640000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 13577715750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 728255154 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35531 # Transaction distribution +system.membus.trans_dist::ReadResp 35531 # Transaction distribution +system.membus.trans_dist::Writeback 114011 # Transaction distribution +system.membus.trans_dist::ReadExReq 130793 # Transaction distribution +system.membus.trans_dist::ReadExResp 130793 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446659 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446659 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17941440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17941440 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17941440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1242249500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1239417000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1535210250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1541901750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16545461 # Number of BP lookups -system.cpu.branchPred.condPredicted 10688882 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 416220 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11528806 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7341014 # Number of BTB hits +system.cpu.branchPred.lookups 16532258 # Number of BP lookups +system.cpu.branchPred.condPredicted 10678400 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 414272 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11254854 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7335293 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.675406 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1988101 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 40517 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.174484 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1985053 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41515 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22395847 # DTB read hits -system.cpu.dtb.read_misses 219375 # DTB read misses -system.cpu.dtb.read_acv 51 # DTB read access violations -system.cpu.dtb.read_accesses 22615222 # DTB read accesses -system.cpu.dtb.write_hits 15705719 # DTB write hits -system.cpu.dtb.write_misses 41176 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15746895 # DTB write accesses -system.cpu.dtb.data_hits 38101566 # DTB hits -system.cpu.dtb.data_misses 260551 # DTB misses -system.cpu.dtb.data_acv 53 # DTB access violations -system.cpu.dtb.data_accesses 38362117 # DTB accesses -system.cpu.itb.fetch_hits 13909771 # ITB hits -system.cpu.itb.fetch_misses 35326 # ITB misses +system.cpu.dtb.read_hits 22389116 # DTB read hits +system.cpu.dtb.read_misses 220601 # DTB read misses +system.cpu.dtb.read_acv 47 # DTB read access violations +system.cpu.dtb.read_accesses 22609717 # DTB read accesses +system.cpu.dtb.write_hits 15701492 # DTB write hits +system.cpu.dtb.write_misses 40930 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15742422 # DTB write accesses +system.cpu.dtb.data_hits 38090608 # DTB hits +system.cpu.dtb.data_misses 261531 # DTB misses +system.cpu.dtb.data_acv 51 # DTB access violations +system.cpu.dtb.data_accesses 38352139 # DTB accesses +system.cpu.itb.fetch_hits 13899561 # ITB hits +system.cpu.itb.fetch_misses 35223 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13945097 # ITB accesses +system.cpu.itb.fetch_accesses 13934784 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,139 +314,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49341816 # number of cpu cycles simulated +system.cpu.numCycles 49272404 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15790710 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105357061 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16545461 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9329115 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19544756 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1999793 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7570274 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314157 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13909771 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 205601 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44679590 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.358058 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120608 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15777525 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105311558 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16532258 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9320346 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19533612 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1991452 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7584858 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7736 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 311235 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 81 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13899561 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 206313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44661692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.357984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120695 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25134834 56.26% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1529938 3.42% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1370308 3.07% 62.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1511826 3.38% 66.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4137251 9.26% 75.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1848058 4.14% 79.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 674230 1.51% 81.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1068805 2.39% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7404340 16.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25128080 56.26% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1526401 3.42% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1371052 3.07% 62.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1506745 3.37% 66.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4140649 9.27% 75.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1845293 4.13% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 672736 1.51% 81.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1068547 2.39% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7402189 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44679590 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.335323 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.135249 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16882265 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7097756 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18571135 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 780643 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1347791 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3745694 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 106722 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103639332 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 302042 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1347791 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17356196 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4802628 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85206 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18838214 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2249555 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102372003 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2542 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2130672 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61646955 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123349032 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123030884 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 318147 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44661692 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.335528 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.137333 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16866897 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7111825 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18558707 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 782025 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1342238 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3745907 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106790 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103587056 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304363 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1342238 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17337019 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4756497 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85160 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18837400 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2303378 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102332178 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 523 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2649 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2191032 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61618182 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123319781 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123000606 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319174 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9100074 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5525 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5523 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4824517 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23234080 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16271017 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1195142 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 460766 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90738136 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5320 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88425930 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95845 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10681231 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4663960 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44679590 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.979112 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109137 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9071301 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5539 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5537 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4823048 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23221608 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16268601 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1205921 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 453901 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90714313 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5368 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88410610 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95528 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10671258 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4645313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 785 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44661692 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.979562 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.108908 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16474837 36.87% 36.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6839728 15.31% 52.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5595634 12.52% 64.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4775900 10.69% 75.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4713198 10.55% 85.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2628457 5.88% 91.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1926364 4.31% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1289803 2.89% 99.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 435669 0.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16438268 36.81% 36.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6883864 15.41% 52.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5570491 12.47% 64.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4772833 10.69% 75.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4726674 10.58% 85.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2623655 5.87% 91.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1921880 4.30% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1281202 2.87% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 442825 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44679590 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44661692 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126495 6.81% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 783002 42.16% 48.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 947503 51.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 125753 6.74% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 787939 42.23% 48.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 952099 51.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49357567 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43846 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49354396 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43843 0.05% 55.87% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121254 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121135 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 59 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38967 0.04% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121164 0.14% 56.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 56.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120950 0.14% 56.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 59 0.00% 56.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.19% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued @@ -483,84 +468,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22848069 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15894942 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22839676 25.83% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15891479 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88425930 # Type of FU issued -system.cpu.iq.rate 1.792109 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1857000 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021001 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222881148 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101028016 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86544064 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603147 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414515 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294050 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89981281 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301649 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1467705 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88410610 # Type of FU issued +system.cpu.iq.rate 1.794323 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1865791 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021104 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222840563 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 100994037 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86537266 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603668 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414920 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294049 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89974489 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301912 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467836 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2957442 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4633 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18287 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1657640 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2944970 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5006 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18410 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1655224 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2832 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 88581 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2933 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 89330 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1347791 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3663804 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 77381 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100225939 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 227298 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23234080 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16271017 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5320 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49801 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6534 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18287 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 195800 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160651 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 356451 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87582928 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22618546 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 843002 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1342238 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3674629 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 72016 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100198527 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23221608 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16268601 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5368 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49821 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6531 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18410 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 194109 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 159104 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 353213 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87568841 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22612881 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 841769 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9482483 # number of nop insts executed -system.cpu.iew.exec_refs 38365741 # number of memory reference insts executed -system.cpu.iew.exec_branches 15084551 # Number of branches executed -system.cpu.iew.exec_stores 15747195 # Number of stores executed -system.cpu.iew.exec_rate 1.775024 # Inst execution rate -system.cpu.iew.wb_sent 87227797 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86838114 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33351220 # num instructions producing a value -system.cpu.iew.wb_consumers 43473707 # num instructions consuming a value +system.cpu.iew.exec_nop 9478846 # number of nop insts executed +system.cpu.iew.exec_refs 38355645 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084252 # Number of branches executed +system.cpu.iew.exec_stores 15742764 # Number of stores executed +system.cpu.iew.exec_rate 1.777239 # Inst execution rate +system.cpu.iew.wb_sent 87220375 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86831315 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33345689 # num instructions producing a value +system.cpu.iew.wb_consumers 43460058 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.759929 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767158 # average fanout of values written-back +system.cpu.iew.wb_rate 1.762271 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767272 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8889589 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8854011 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 311933 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43331799 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.038703 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791883 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 309865 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43319454 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.039284 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791171 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20501224 47.31% 47.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7041698 16.25% 63.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3356099 7.75% 71.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2051116 4.73% 76.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2049317 4.73% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1167384 2.69% 83.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1102119 2.54% 86.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 716210 1.65% 87.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5346632 12.34% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20467997 47.25% 47.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7041159 16.25% 63.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3392321 7.83% 71.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2059744 4.75% 76.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2024611 4.67% 80.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1169642 2.70% 83.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1101426 2.54% 86.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 720003 1.66% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5342551 12.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43331799 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43319454 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,229 +556,264 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5346632 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 44395413 50.25% 60.16% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 113689 0.13% 60.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 20276638 22.95% 83.46% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction +system.cpu.commit.bw_lim_events 5342551 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133898086 # The number of ROB reads -system.cpu.rob.rob_writes 195811124 # The number of ROB writes -system.cpu.timesIdled 85852 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4662226 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133854244 # The number of ROB reads +system.cpu.rob.rob_writes 195734344 # The number of ROB writes +system.cpu.timesIdled 83887 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4610712 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.619936 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.619936 # CPI: Total CPI of All Threads -system.cpu.ipc 1.613069 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.613069 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115913702 # number of integer regfile reads -system.cpu.int_regfile_writes 57508814 # number of integer regfile writes -system.cpu.fp_regfile_reads 249357 # number of floating regfile reads -system.cpu.fp_regfile_writes 240037 # number of floating regfile writes -system.cpu.misc_regfile_reads 38036 # number of misc regfile reads +system.cpu.cpi 0.619064 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.619064 # CPI: Total CPI of All Threads +system.cpu.ipc 1.615341 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.615341 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115895624 # number of integer regfile reads +system.cpu.int_regfile_writes 57505324 # number of integer regfile writes +system.cpu.fp_regfile_reads 249507 # number of floating regfile reads +system.cpu.fp_regfile_writes 239755 # number of floating regfile writes +system.cpu.misc_regfile_reads 38031 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1213726946 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143419 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143419 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580053 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 766814 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5976320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.throughput 1215125035 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143416 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186521 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 766565 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5968640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29943744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29943744 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29936064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29936064 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402865000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402814000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141399227 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141250965 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 324564248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 328598748 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91332 # number of replacements -system.cpu.icache.tags.tagsinuse 1925.493490 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13803368 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93380 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.819319 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19891128250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1925.493490 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940182 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940182 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 91212 # number of replacements +system.cpu.icache.tags.tagsinuse 1925.511317 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13793650 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93260 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.905318 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19818994250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1925.511317 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940191 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940191 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1527 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 358 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1531 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 356 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27912922 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27912922 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13803368 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13803368 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13803368 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13803368 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13803368 # number of overall hits -system.cpu.icache.overall_hits::total 13803368 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses -system.cpu.icache.overall_misses::total 106403 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2000796974 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2000796974 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2000796974 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2000796974 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2000796974 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2000796974 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13909771 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13909771 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13909771 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13909771 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13909771 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13909771 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007650 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007650 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007650 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007650 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007650 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007650 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18803.952652 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18803.952652 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18803.952652 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18803.952652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18803.952652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18803.952652 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 263 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27892378 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27892378 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13793650 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13793650 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13793650 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13793650 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13793650 # number of overall hits +system.cpu.icache.overall_hits::total 13793650 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105909 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105909 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105909 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105909 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105909 # number of overall misses +system.cpu.icache.overall_misses::total 105909 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1976186457 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1976186457 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1976186457 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1976186457 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1976186457 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1976186457 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13899559 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13899559 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13899559 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13899559 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13899559 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13899559 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007620 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007620 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007620 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007620 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007620 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007620 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18659.287284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18659.287284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18659.287284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18659.287284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18659.287284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18659.287284 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 681 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.916667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13022 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 13022 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 13022 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 13022 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 13022 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 13022 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93381 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93381 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93381 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93381 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93381 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93381 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1534559773 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1534559773 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1534559773 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1534559773 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1534559773 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1534559773 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006713 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006713 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006713 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16433.319123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16433.319123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16433.319123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16433.319123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16433.319123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16433.319123 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12648 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12648 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12648 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12648 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12648 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12648 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93261 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93261 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93261 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93261 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93261 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93261 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1519348535 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1519348535 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1519348535 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1519348535 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1519348535 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1519348535 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006710 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006710 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006710 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006710 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006710 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006710 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16291.360108 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16291.360108 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16291.360108 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16291.360108 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16291.360108 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16291.360108 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132391 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30672.416469 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 159732 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164458 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.971263 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132413 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30673.735606 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159593 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164480 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.970288 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26335.603733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.899695 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2234.913041 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803699 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064145 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.068204 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.936048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26310.881210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2113.593767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2249.260629 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.802944 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064502 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.068642 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.936088 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32067 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1463 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18089 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12275 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 61 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1480 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18009 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12342 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978607 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4050853 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4050853 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 85734 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34287 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120021 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168929 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168929 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12621 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12621 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 85734 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46908 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132642 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 85734 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46908 # number of overall hits -system.cpu.l2cache.overall_hits::total 132642 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7647 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27856 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35503 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130798 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130798 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7647 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158654 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166301 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7647 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158654 # number of overall misses -system.cpu.l2cache.overall_misses::total 166301 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 583211250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2050433250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2633644500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13218958750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13218958750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 583211250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15269392000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15852603250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 583211250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15269392000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15852603250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 93381 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62143 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 155524 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168929 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168929 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143419 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143419 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 93381 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205562 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 298943 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 93381 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205562 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 298943 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081890 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448256 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.228280 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911999 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911999 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081890 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771806 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.556297 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081890 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771806 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.556297 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76266.673205 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73608.315982 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74180.900206 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101063.921084 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101063.921084 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76266.673205 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96243.347158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 95324.762028 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76266.673205 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96243.347158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 95324.762028 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 4049912 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4049912 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 85586 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34280 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 119866 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168938 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168938 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12623 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12623 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 85586 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46903 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132489 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 85586 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46903 # number of overall hits +system.cpu.l2cache.overall_hits::total 132489 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7675 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27857 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35532 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130793 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130793 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7675 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158650 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166325 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7675 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158650 # number of overall misses +system.cpu.l2cache.overall_misses::total 166325 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 569595000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2069573000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2639168000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13123369250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13123369250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 569595000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15192942250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15762537250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 569595000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15192942250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15762537250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 93261 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62137 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 155398 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168938 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168938 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143416 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143416 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93261 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205553 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 298814 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93261 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205553 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 298814 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082296 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448316 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.228652 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911983 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911983 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082296 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771820 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.556617 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082296 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771820 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.556617 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74214.332248 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74292.745091 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74275.807723 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 100336.938903 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 100336.938903 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74214.332248 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95763.896943 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 94769.500977 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74214.332248 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95763.896943 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 94769.500977 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,155 +822,155 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114017 # number of writebacks -system.cpu.l2cache.writebacks::total 114017 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7647 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27856 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35503 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130798 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130798 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7647 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158654 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166301 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7647 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158654 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166301 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 486616750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695026750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2181643500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11619308250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11619308250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 486616750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13314335000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13800951750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 486616750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13314335000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13800951750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448256 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228280 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911999 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911999 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771806 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556297 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771806 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556297 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63634.987577 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60849.610497 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61449.553559 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88833.990199 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88833.990199 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63634.987577 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83920.575592 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82987.785702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63634.987577 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83920.575592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82987.785702 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114011 # number of writebacks +system.cpu.l2cache.writebacks::total 114011 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7675 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27857 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35532 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130793 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130793 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7675 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158650 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166325 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7675 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158650 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166325 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 472615500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1714074500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2186690000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11513357750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11513357750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472615500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13227432250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13700047750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472615500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13227432250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13700047750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082296 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228652 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911983 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911983 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082296 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771820 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.556617 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082296 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771820 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.556617 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61578.566775 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61531.195032 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61541.427446 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88027.323710 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88027.323710 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61578.566775 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83374.927513 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82369.143244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61578.566775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83374.927513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82369.143244 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201466 # number of replacements -system.cpu.dcache.tags.tagsinuse 4073.410780 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34191132 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205562 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.330022 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 225470250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4073.410780 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994485 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994485 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201457 # number of replacements +system.cpu.dcache.tags.tagsinuse 4073.584909 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34188310 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205553 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.323576 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 223833000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4073.584909 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994528 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994528 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1081 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2933 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2926 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71201646 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71201646 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20617040 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20617040 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574040 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574040 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34191080 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34191080 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34191080 # number of overall hits -system.cpu.dcache.overall_hits::total 34191080 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267573 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267573 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039337 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039337 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306910 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306910 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306910 # number of overall misses -system.cpu.dcache.overall_misses::total 1306910 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15791609498 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15791609498 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85266584825 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85266584825 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 101058194323 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 101058194323 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 101058194323 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 101058194323 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20884613 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20884613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 71195917 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71195917 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20614139 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20614139 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574109 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574109 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34188248 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34188248 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34188248 # number of overall hits +system.cpu.dcache.overall_hits::total 34188248 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267604 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267604 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039268 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039268 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306872 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306872 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306872 # number of overall misses +system.cpu.dcache.overall_misses::total 1306872 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16043231998 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16043231998 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85247557215 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85247557215 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 101290789213 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 101290789213 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 101290789213 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 101290789213 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20881743 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20881743 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35497990 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35497990 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35497990 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35497990 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036816 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036816 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036816 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036816 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59017.948365 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59017.948365 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82039.400911 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82039.400911 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77326.054834 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77326.054834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77326.054834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77326.054834 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4861037 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35495120 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35495120 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35495120 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35495120 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012815 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012815 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036818 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036818 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036818 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036818 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59951.390854 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59951.390854 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82026.539078 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82026.539078 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77506.281574 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77506.281574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77506.281574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77506.281574 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4834178 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 111685 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 104486 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.524529 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.266275 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks -system.cpu.dcache.writebacks::total 168929 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205428 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205428 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895920 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895920 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62145 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62145 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205562 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205562 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205562 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205562 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2457360502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2457360502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13489619744 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13489619744 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15946980246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15946980246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15946980246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15946980246 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168938 # number of writebacks +system.cpu.dcache.writebacks::total 168938 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895855 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895855 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101319 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101319 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101319 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101319 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62140 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62140 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143413 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143413 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205553 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205553 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205553 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205553 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2476433502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2476433502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13394078745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13394078745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15870512247 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15870512247 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15870512247 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15870512247 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses @@ -959,14 +979,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39542.368686 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39542.368686 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94058.722076 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94058.722076 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77577.471741 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77577.471741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77577.471741 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77577.471741 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39852.486353 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39852.486353 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93395.150684 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93395.150684 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77208.857312 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77208.857312 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77208.857312 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77208.857312 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 9c79d9678..36b629088 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1834941 # Simulator instruction rate (inst/s) -host_op_rate 1834940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 918522034 # Simulator tick rate (ticks/s) -host_mem_usage 279452 # Number of bytes of host memory used -host_seconds 48.14 # Real time elapsed on the host +host_inst_rate 2624099 # Simulator instruction rate (inst/s) +host_op_rate 2624098 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1313553455 # Simulator tick rate (ticks/s) +host_mem_usage 264796 # Number of bytes of host memory used +host_seconds 33.67 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -95,5 +95,40 @@ system.cpu.num_busy_cycles 88442007 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched +system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction +system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction +system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction +system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction +system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 88438073 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 51324a43d..005dec492 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 990858 # Simulator instruction rate (inst/s) -host_op_rate 990858 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1498890062 # Simulator tick rate (ticks/s) -host_mem_usage 288280 # Number of bytes of host memory used -host_seconds 89.16 # Real time elapsed on the host +host_inst_rate 1051168 # Simulator instruction rate (inst/s) +host_op_rate 1051168 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1590122468 # Simulator tick rate (ticks/s) +host_mem_usage 273520 # Number of bytes of host memory used +host_seconds 84.04 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -109,6 +109,41 @@ system.cpu.num_busy_cycles 267269454 # Nu system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched +system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction +system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction +system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction +system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction +system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction +system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction +system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction +system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction +system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 88438073 # Class of executed instruction system.cpu.icache.tags.replacements 74391 # number of replacements system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. |