diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/alpha')
3 files changed, 1511 insertions, 1515 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 47efecce5..acacb719c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058585 # Number of seconds simulated -sim_ticks 58584661500 # Number of ticks simulated -final_tick 58584661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059745 # Number of seconds simulated +sim_ticks 59744560000 # Number of ticks simulated +final_tick 59744560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201524 # Simulator instruction rate (inst/s) -host_op_rate 201524 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133496887 # Simulator tick rate (ticks/s) -host_mem_usage 290684 # Number of bytes of host memory used -host_seconds 438.85 # Real time elapsed on the host +host_inst_rate 336953 # Simulator instruction rate (inst/s) +host_op_rate 336953 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 227629544 # Simulator tick rate (ticks/s) +host_mem_usage 304552 # Number of bytes of host memory used +host_seconds 262.46 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 516608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 517248 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10147776 # Number of bytes read from this memory -system.physmem.bytes_read::total 10664384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 516608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 516608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8072 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10665024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 517248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 517248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8082 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166631 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8818144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 173215578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 182033722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8818144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8818144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 124590154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 124590154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 124590154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8818144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 173215578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 306623876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166631 # Number of read requests accepted -system.physmem.writeReqs 114048 # Number of write requests accepted -system.physmem.readBursts 166631 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10663872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10664384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 166641 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8657659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169852720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178510378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8657659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8657659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122170253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122170253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122170253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8657659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169852720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 300680631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166641 # Number of read requests accepted +system.physmem.writeReqs 114047 # Number of write requests accepted +system.physmem.readBursts 166641 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114047 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10664448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10665024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10466 # Per bank write bursts -system.physmem.perBankRdBursts::1 10512 # Per bank write bursts +system.physmem.perBankRdBursts::0 10464 # Per bank write bursts +system.physmem.perBankRdBursts::1 10514 # Per bank write bursts system.physmem.perBankRdBursts::2 10315 # Per bank write bursts -system.physmem.perBankRdBursts::3 10093 # Per bank write bursts -system.physmem.perBankRdBursts::4 10429 # Per bank write bursts +system.physmem.perBankRdBursts::3 10095 # Per bank write bursts +system.physmem.perBankRdBursts::4 10432 # Per bank write bursts system.physmem.perBankRdBursts::5 10431 # Per bank write bursts -system.physmem.perBankRdBursts::6 9849 # Per bank write bursts -system.physmem.perBankRdBursts::7 10302 # Per bank write bursts -system.physmem.perBankRdBursts::8 10595 # Per bank write bursts +system.physmem.perBankRdBursts::6 9850 # Per bank write bursts +system.physmem.perBankRdBursts::7 10303 # Per bank write bursts +system.physmem.perBankRdBursts::8 10594 # Per bank write bursts system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10598 # Per bank write bursts -system.physmem.perBankRdBursts::11 10258 # Per bank write bursts -system.physmem.perBankRdBursts::12 10302 # Per bank write bursts -system.physmem.perBankRdBursts::13 10653 # Per bank write bursts +system.physmem.perBankRdBursts::10 10596 # Per bank write bursts +system.physmem.perBankRdBursts::11 10260 # Per bank write bursts +system.physmem.perBankRdBursts::12 10303 # Per bank write bursts +system.physmem.perBankRdBursts::13 10654 # Per bank write bursts system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10648 # Per bank write bursts +system.physmem.perBankRdBursts::15 10649 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7176 # Per bank write bursts +system.physmem.perBankWrBursts::5 7178 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7223 # Per bank write bursts -system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7096 # Per bank write bursts -system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::7 7080 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts +system.physmem.perBankWrBursts::9 6940 # Per bank write bursts +system.physmem.perBankWrBursts::10 7097 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6967 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58584634500 # Total gap between requests +system.physmem.totGap 59744533000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166631 # Read request sizes (log2) +system.physmem.readPktSize::6 166641 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114048 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114047 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,122 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.259345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.795576 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.998077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19535 35.81% 35.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11763 21.56% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5616 10.30% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3566 6.54% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2684 4.92% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2055 3.77% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1672 3.07% 85.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1540 2.82% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6118 11.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54549 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.746152 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.264922 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7014 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.521940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.158907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.861003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19447 35.57% 35.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11824 21.63% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5661 10.35% 67.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3636 6.65% 74.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2772 5.07% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2160 3.95% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1686 3.08% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1520 2.78% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5967 10.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54673 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.740134 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.174119 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7016 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.250998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.234711 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.764594 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6252 89.11% 89.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 8 0.11% 89.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 591 8.42% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 125 1.78% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 23 0.33% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7016 # Writes before turning the bus around for reads -system.physmem.totQLat 1948128750 # Total ticks spent queuing -system.physmem.totMemAccLat 5072310000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11691.84 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.245939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.230597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.737975 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 17 0.24% 89.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 574 8.18% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 144 2.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 20 0.28% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads +system.physmem.totQLat 1983100250 # Total ticks spent queuing +system.physmem.totMemAccLat 5107450250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11901.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30441.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 182.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 124.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 182.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 124.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30651.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.40 # Data bus utilization in percentage -system.physmem.busUtilRead 1.42 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.97 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.35 # Data bus utilization in percentage +system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.07 # Average write queue length when enqueuing -system.physmem.readRowHits 144841 # Number of row buffer hits during reads -system.physmem.writeRowHits 81248 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.93 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing +system.physmem.readRowHits 144723 # Number of row buffer hits during reads +system.physmem.writeRowHits 81251 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate 71.24 # Row buffer hit rate for writes -system.physmem.avgGap 208724.68 # Average gap between requests -system.physmem.pageHitRate 80.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199077480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108623625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 642681000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367791840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12184332255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24462392250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41791303890 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.356895 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40549753500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem.avgGap 212850.33 # Average gap between requests +system.physmem.pageHitRate 80.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199115280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108644250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 642735600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367778880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12699594585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24706498500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42626547975 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.484810 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40950314500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1994980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16078529000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16799112000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213282720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116374500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 656908200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371038320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12703202685 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24007242750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41894454615 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.117627 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 39789307500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem_1.actEnergy 214197480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116873625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 656962800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371031840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13192492680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24274131750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42727871055 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.180760 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40226086750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1994980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16838471250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17523103250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14678313 # Number of BP lookups -system.cpu.branchPred.condPredicted 9498021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 389703 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9975544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6390264 # Number of BTB hits +system.cpu.branchPred.lookups 14679718 # Number of BP lookups +system.cpu.branchPred.condPredicted 9498983 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 392764 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10434122 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6393495 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.059303 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1709596 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85905 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.274873 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1709689 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85822 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20567455 # DTB read hits -system.cpu.dtb.read_misses 96888 # DTB read misses +system.cpu.dtb.read_hits 20566953 # DTB read hits +system.cpu.dtb.read_misses 96874 # DTB read misses system.cpu.dtb.read_acv 11 # DTB read access violations -system.cpu.dtb.read_accesses 20664343 # DTB read accesses -system.cpu.dtb.write_hits 14665775 # DTB write hits -system.cpu.dtb.write_misses 9411 # DTB write misses +system.cpu.dtb.read_accesses 20663827 # DTB read accesses +system.cpu.dtb.write_hits 14666692 # DTB write hits +system.cpu.dtb.write_misses 9419 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675186 # DTB write accesses -system.cpu.dtb.data_hits 35233230 # DTB hits -system.cpu.dtb.data_misses 106299 # DTB misses +system.cpu.dtb.write_accesses 14676111 # DTB write accesses +system.cpu.dtb.data_hits 35233645 # DTB hits +system.cpu.dtb.data_misses 106293 # DTB misses system.cpu.dtb.data_acv 11 # DTB access violations -system.cpu.dtb.data_accesses 35339529 # DTB accesses -system.cpu.itb.fetch_hits 25627333 # ITB hits -system.cpu.itb.fetch_misses 5261 # ITB misses +system.cpu.dtb.data_accesses 35339938 # DTB accesses +system.cpu.itb.fetch_hits 25640132 # ITB hits +system.cpu.itb.fetch_misses 5244 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25632594 # ITB accesses +system.cpu.itb.fetch_accesses 25645376 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -322,81 +321,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 117169323 # number of cpu cycles simulated +system.cpu.numCycles 119489120 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1098705 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1100288 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.324874 # CPI: cycles per instruction -system.cpu.ipc 0.754789 # IPC: instructions per cycle -system.cpu.tickCycles 91571156 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25598167 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200776 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.523211 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616515 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204872 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.966550 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.523211 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994024 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994024 # Average percentage of cache occupancy +system.cpu.cpi 1.351105 # CPI: cycles per instruction +system.cpu.ipc 0.740135 # IPC: instructions per cycle +system.cpu.tickCycles 91601603 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27887517 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200784 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.582702 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34615842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204880 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.956667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 693853250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.582702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993795 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993795 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 745 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3298 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3372 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176892 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176892 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20283193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20283193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333322 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333322 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616515 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616515 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616515 # number of overall hits -system.cpu.dcache.overall_hits::total 34616515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89440 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89440 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280055 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280055 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369495 # number of overall misses -system.cpu.dcache.overall_misses::total 369495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4407640500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4407640500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19996177500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19996177500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24403818000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24403818000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24403818000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24403818000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70175650 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70175650 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282569 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282569 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333273 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333273 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34615842 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34615842 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34615842 # number of overall hits +system.cpu.dcache.overall_hits::total 34615842 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89439 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89439 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280104 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280104 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369543 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369543 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369543 # number of overall misses +system.cpu.dcache.overall_misses::total 369543 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4793461000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4793461000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21859170750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21859170750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26652631750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26652631750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26652631750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26652631750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34986010 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34986010 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34986010 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34986010 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34985385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985385 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985385 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010561 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010561 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49280.417039 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49280.417039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71400.894467 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71400.894467 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66046.409288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66046.409288 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53594.751730 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53594.751730 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78039.480871 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78039.480871 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72123.221790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72123.221790 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,32 +404,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168546 # number of writebacks -system.cpu.dcache.writebacks::total 168546 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28125 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28125 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136498 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136498 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164623 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164623 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164623 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164623 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61315 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143557 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204872 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204872 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204872 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204872 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2422248250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2422248250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9931035500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9931035500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12353283750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12353283750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12353283750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12353283750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168547 # number of writebacks +system.cpu.dcache.writebacks::total 168547 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28118 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136545 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136545 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16580.645782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16580.645782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16580.645782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16580.645782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,123 +508,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155835 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2348059258 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14202.002175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14202.002175 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14202.002175 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14202.002175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14202.002175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14202.002175 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15060.640369 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15060.640369 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15060.640369 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15060.640369 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15060.640369 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15060.640369 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132704 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.051845 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.461885 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.051845 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.461885 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66631.850798 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68278.904867 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67906.613535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68815.224783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68815.224783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66631.850798 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68721.608360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68620.244296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66631.850798 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68721.608360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68620.244296 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 217149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 217148 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311669 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578290 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 889959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9973376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33872128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 217227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 217226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143560 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143560 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578307 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 890120 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9977984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33877312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 529253 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 529334 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 529253 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 529334 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 529253 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 433172500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 529334 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 433214000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 235311991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 235419242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343212750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343262500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35749 # Transaction distribution -system.membus.trans_dist::ReadResp 35749 # Transaction distribution -system.membus.trans_dist::Writeback 114048 # Transaction distribution +system.membus.trans_dist::ReadReq 35759 # Transaction distribution +system.membus.trans_dist::ReadResp 35759 # Transaction distribution +system.membus.trans_dist::Writeback 114047 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447310 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17963456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447329 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447329 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17964032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17964032 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280679 # Request fanout histogram +system.membus.snoop_fanout::samples 280688 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280679 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280679 # Request fanout histogram -system.membus.reqLayer0.occupancy 1304618000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602414250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.snoop_fanout::total 280688 # Request fanout histogram +system.membus.reqLayer0.occupancy 817068000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 879892750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 6d3efb0ae..c7130e3ac 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022282 # Number of seconds simulated -sim_ticks 22281815500 # Number of ticks simulated -final_tick 22281815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022578 # Number of seconds simulated +sim_ticks 22578120000 # Number of ticks simulated +final_tick 22578120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 227860 # Simulator instruction rate (inst/s) -host_op_rate 227860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63789654 # Simulator tick rate (ticks/s) -host_mem_usage 305428 # Number of bytes of host memory used -host_seconds 349.30 # Real time elapsed on the host +host_inst_rate 224564 # Simulator instruction rate (inst/s) +host_op_rate 224564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63702871 # Simulator tick rate (ticks/s) +host_mem_usage 305848 # Number of bytes of host memory used +host_seconds 354.43 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10151488 # Number of bytes read from this memory -system.physmem.bytes_read::total 10638656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296384 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7612 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158617 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166229 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114006 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114006 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21863928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455595192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 477459119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21863928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21863928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 327459134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 327459134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 327459134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21863928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455595192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 804918253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166229 # Number of read requests accepted -system.physmem.writeReqs 114006 # Number of write requests accepted -system.physmem.readBursts 166229 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114006 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytes_read::cpu.inst 487616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10151104 # Number of bytes read from this memory +system.physmem.bytes_read::total 10638720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 487616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 487616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158611 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166230 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21596838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 449599169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 471196007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21596838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21596838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 323181558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 323181558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 323181558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21596838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 449599169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 794377566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166230 # Number of read requests accepted +system.physmem.writeReqs 114013 # Number of write requests accepted +system.physmem.readBursts 166230 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114013 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10638656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7296384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10638720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7296832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10438 # Per bank write bursts -system.physmem.perBankRdBursts::1 10454 # Per bank write bursts -system.physmem.perBankRdBursts::2 10317 # Per bank write bursts -system.physmem.perBankRdBursts::3 10059 # Per bank write bursts -system.physmem.perBankRdBursts::4 10417 # Per bank write bursts -system.physmem.perBankRdBursts::5 10393 # Per bank write bursts +system.physmem.perBankRdBursts::0 10435 # Per bank write bursts +system.physmem.perBankRdBursts::1 10460 # Per bank write bursts +system.physmem.perBankRdBursts::2 10318 # Per bank write bursts +system.physmem.perBankRdBursts::3 10058 # Per bank write bursts +system.physmem.perBankRdBursts::4 10413 # Per bank write bursts +system.physmem.perBankRdBursts::5 10396 # Per bank write bursts system.physmem.perBankRdBursts::6 9837 # Per bank write bursts -system.physmem.perBankRdBursts::7 10310 # Per bank write bursts -system.physmem.perBankRdBursts::8 10606 # Per bank write bursts -system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10543 # Per bank write bursts -system.physmem.perBankRdBursts::11 10224 # Per bank write bursts -system.physmem.perBankRdBursts::12 10268 # Per bank write bursts -system.physmem.perBankRdBursts::13 10616 # Per bank write bursts -system.physmem.perBankRdBursts::14 10478 # Per bank write bursts -system.physmem.perBankRdBursts::15 10618 # Per bank write bursts +system.physmem.perBankRdBursts::7 10308 # Per bank write bursts +system.physmem.perBankRdBursts::8 10587 # Per bank write bursts +system.physmem.perBankRdBursts::9 10644 # Per bank write bursts +system.physmem.perBankRdBursts::10 10547 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10270 # Per bank write bursts +system.physmem.perBankRdBursts::13 10618 # Per bank write bursts +system.physmem.perBankRdBursts::14 10481 # Per bank write bursts +system.physmem.perBankRdBursts::15 10621 # Per bank write bursts system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7253 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7169 # Per bank write bursts -system.physmem.perBankWrBursts::6 6770 # Per bank write bursts -system.physmem.perBankWrBursts::7 7085 # Per bank write bursts -system.physmem.perBankWrBursts::8 7220 # Per bank write bursts -system.physmem.perBankWrBursts::9 6943 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::5 7171 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 7083 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6939 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts system.physmem.perBankWrBursts::11 6988 # Per bank write bursts system.physmem.perBankWrBursts::12 6964 # Per bank write bursts -system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7283 # Per bank write bursts +system.physmem.perBankWrBursts::13 7288 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22281781500 # Total gap between requests +system.physmem.totGap 22578086500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166229 # Read request sizes (log2) +system.physmem.readPktSize::6 166230 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114006 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14988 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114013 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 52462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32153 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,124 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.580755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.430431 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.457165 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18353 35.17% 35.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10742 20.58% 55.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5641 10.81% 66.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3092 5.92% 72.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2629 5.04% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1694 3.25% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1790 3.43% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1288 2.47% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6960 13.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52189 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6966 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.861757 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.246517 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6964 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.127440 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.641716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.309325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18423 35.25% 35.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10477 20.05% 55.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5934 11.35% 66.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2978 5.70% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2855 5.46% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1509 2.89% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2072 3.96% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 924 1.77% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7088 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52260 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6982 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.804927 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.249057 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6981 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6966 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.363676 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.332802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.079402 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6068 87.12% 87.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.43% 87.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 495 7.11% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 185 2.66% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.31% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.66% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.30% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.14% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6965 # Writes before turning the bus around for reads -system.physmem.totQLat 5436579750 # Total ticks spent queuing -system.physmem.totMemAccLat 8553223500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 6982 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6982 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.325265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.299310 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.979398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6150 88.08% 88.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.36% 88.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 468 6.70% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 181 2.59% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 78 1.12% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.66% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 19 0.27% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 4 0.06% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6982 # Writes before turning the bus around for reads +system.physmem.totQLat 5742111500 # Total ticks spent queuing +system.physmem.totMemAccLat 8858755250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32706.94 # Average queueing delay per DRAM burst +system.physmem.avgQLat 34545.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51456.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 477.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 327.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 477.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 327.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53295.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 471.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 323.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 471.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 323.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.29 # Data bus utilization in percentage -system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 146012 # Number of row buffer hits during reads -system.physmem.writeRowHits 81986 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes -system.physmem.avgGap 79511.06 # Average gap between requests -system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190496880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103941750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641043000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367539120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6553751985 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7617131250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16928894145 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.936312 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12590169250 # Time in different power states -system.physmem_0.memoryStateTime::REF 743860000 # Time in different power states +system.physmem.busUtil 6.21 # Data bus utilization in percentage +system.physmem.busUtilRead 3.68 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing +system.physmem.readRowHits 146222 # Number of row buffer hits during reads +system.physmem.writeRowHits 81709 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.67 # Row buffer hit rate for writes +system.physmem.avgGap 80566.10 # Average gap between requests +system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190685880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 104044875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 641035200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367584480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6555814245 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7792863750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 17126343870 # Total energy per rank (pJ) +system.physmem_0.averagePower 758.721685 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12883309000 # Time in different power states +system.physmem_0.memoryStateTime::REF 753740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8942711000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8935594000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 203779800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111189375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 204104880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111366750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370694880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6762785805 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7433764500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16992123720 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.774895 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12284853000 # Time in different power states -system.physmem_1.memoryStateTime::REF 743860000 # Time in different power states +system.physmem_1.writeEnergy 370701360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6889050495 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7500532500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17204990625 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.206905 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12395641000 # Time in different power states +system.physmem_1.memoryStateTime::REF 753740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9248437000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9423231500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16624924 # Number of BP lookups -system.cpu.branchPred.condPredicted 10755300 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 362268 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10924107 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374828 # Number of BTB hits +system.cpu.branchPred.lookups 16619938 # Number of BP lookups +system.cpu.branchPred.condPredicted 10751763 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 361573 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10694449 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7373128 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.509665 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1991560 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2903 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 68.943505 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990233 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3119 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22639897 # DTB read hits -system.cpu.dtb.read_misses 226363 # DTB read misses -system.cpu.dtb.read_acv 23 # DTB read access violations -system.cpu.dtb.read_accesses 22866260 # DTB read accesses -system.cpu.dtb.write_hits 15870343 # DTB write hits -system.cpu.dtb.write_misses 44837 # DTB write misses +system.cpu.dtb.read_hits 22587975 # DTB read hits +system.cpu.dtb.read_misses 226213 # DTB read misses +system.cpu.dtb.read_acv 17 # DTB read access violations +system.cpu.dtb.read_accesses 22814188 # DTB read accesses +system.cpu.dtb.write_hits 15866557 # DTB write hits +system.cpu.dtb.write_misses 44947 # DTB write misses system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15915180 # DTB write accesses -system.cpu.dtb.data_hits 38510240 # DTB hits -system.cpu.dtb.data_misses 271200 # DTB misses -system.cpu.dtb.data_acv 24 # DTB access violations -system.cpu.dtb.data_accesses 38781440 # DTB accesses -system.cpu.itb.fetch_hits 13919462 # ITB hits -system.cpu.itb.fetch_misses 31654 # ITB misses +system.cpu.dtb.write_accesses 15911504 # DTB write accesses +system.cpu.dtb.data_hits 38454532 # DTB hits +system.cpu.dtb.data_misses 271160 # DTB misses +system.cpu.dtb.data_acv 18 # DTB access violations +system.cpu.dtb.data_accesses 38725692 # DTB accesses +system.cpu.itb.fetch_hits 13913083 # ITB hits +system.cpu.itb.fetch_misses 32600 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13951116 # ITB accesses +system.cpu.itb.fetch_accesses 13945683 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,240 +321,240 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44563634 # number of cpu cycles simulated +system.cpu.numCycles 45156244 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15791560 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106158478 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16624924 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9366388 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27217966 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 963396 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 137 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337279 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13919462 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206375 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43833697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.421846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15767330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106100961 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16619938 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9363361 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27775290 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 962592 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 339291 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13913083 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 207051 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 44368516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.391357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.125574 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24095007 54.97% 54.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538131 3.51% 58.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1406372 3.21% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1524721 3.48% 65.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4235690 9.66% 74.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846144 4.21% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 685371 1.56% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070354 2.44% 83.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7431907 16.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24640012 55.53% 55.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1537852 3.47% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1401576 3.16% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1522530 3.43% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4244947 9.57% 75.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1845094 4.16% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 677475 1.53% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069981 2.41% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7429049 16.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43833697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.373060 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.382177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15105656 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9282610 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18470395 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 592044 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 382992 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3741910 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100605 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104048931 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 315835 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 382992 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15490766 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6387964 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 95966 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18655378 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2820631 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102900646 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4493 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 152365 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 320462 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2296242 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61929819 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124171537 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123841536 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 330000 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44368516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.368054 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.349641 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15099347 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9823247 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18465046 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 597969 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 382907 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3741515 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100209 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104016227 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 314595 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 382907 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15487504 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6707215 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96849 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18654699 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3039342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102867556 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4643 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 101006 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 348263 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2491758 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61906530 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124122948 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123794647 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 328300 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9382938 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5791 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5849 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2464589 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23265416 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16459353 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1262626 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 544604 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91320451 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5681 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89124415 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 80151 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11242959 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4725710 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1098 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43833697 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.033240 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.247678 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9359649 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5745 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5793 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2522683 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23265731 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16453437 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1244012 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 539260 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91299347 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5639 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89055311 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 77552 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11218941 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4714239 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1056 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44368516 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.246117 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17209661 39.26% 39.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5800175 13.23% 52.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5098270 11.63% 64.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4410681 10.06% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4347575 9.92% 84.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649961 6.05% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1950790 4.45% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1381860 3.15% 97.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 984724 2.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17795444 40.11% 40.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5774110 13.01% 53.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5077311 11.44% 64.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4396727 9.91% 74.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4357066 9.82% 84.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2650893 5.97% 90.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1948119 4.39% 94.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1385813 3.12% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 983033 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43833697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44368516 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 244354 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1175209 46.41% 56.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112799 43.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 243204 9.64% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1172094 46.45% 56.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1108166 43.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49663354 55.72% 55.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44187 0.05% 55.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122171 0.14% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121874 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39065 0.04% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23057459 25.87% 81.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16076160 18.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49651741 55.75% 55.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44157 0.05% 55.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121956 0.14% 55.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121436 0.14% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39055 0.04% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23004684 25.83% 81.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16072139 18.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89124415 # Type of FU issued -system.cpu.iq.rate 1.999936 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2532362 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028414 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224079080 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102152200 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87178162 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 615960 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 437940 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 301333 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91348643 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 308134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1658507 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89055311 # Type of FU issued +system.cpu.iq.rate 1.972159 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2523465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028336 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224465346 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102111433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87163804 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 614809 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 433572 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 300747 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91271228 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307548 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1661543 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2988778 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6943 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21591 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1845976 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2989093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6317 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21548 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1840060 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3051 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 325532 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3023 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 186080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 382992 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1216204 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4841557 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100851766 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 147146 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23265416 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16459353 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5598 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3356 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4819285 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21591 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 151679 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 156559 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 308238 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88344034 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22866899 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 780381 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 382907 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1413856 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4974138 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100829471 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 151929 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23265731 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16453437 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5565 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4957861 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21548 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 151078 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 158072 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 309150 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88275465 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22814985 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 779846 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9525634 # number of nop insts executed -system.cpu.iew.exec_refs 38782381 # number of memory reference insts executed -system.cpu.iew.exec_branches 15172546 # Number of branches executed -system.cpu.iew.exec_stores 15915482 # Number of stores executed -system.cpu.iew.exec_rate 1.982424 # Inst execution rate -system.cpu.iew.wb_sent 87895909 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87479495 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33899568 # num instructions producing a value -system.cpu.iew.wb_consumers 44349597 # num instructions consuming a value +system.cpu.iew.exec_nop 9524485 # number of nop insts executed +system.cpu.iew.exec_refs 38726852 # number of memory reference insts executed +system.cpu.iew.exec_branches 15171568 # Number of branches executed +system.cpu.iew.exec_stores 15911867 # Number of stores executed +system.cpu.iew.exec_rate 1.954889 # Inst execution rate +system.cpu.iew.wb_sent 87882002 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87464551 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33900833 # num instructions producing a value +system.cpu.iew.wb_consumers 44342613 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.963024 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764372 # average fanout of values written-back +system.cpu.iew.wb_rate 1.936931 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764520 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9308985 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9282281 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 263562 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42463328 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.080399 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.884681 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 263184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43000551 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.054408 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.876009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20917493 49.26% 49.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6333939 14.92% 64.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2944595 6.93% 71.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1757333 4.14% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1653620 3.89% 79.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1138333 2.68% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1205391 2.84% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 793939 1.87% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5718685 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21467431 49.92% 49.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6329802 14.72% 64.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2918642 6.79% 71.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1760390 4.09% 75.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1670777 3.89% 79.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1138707 2.65% 82.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1203989 2.80% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 794665 1.85% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5716148 13.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42463328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43000551 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,344 +600,344 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5718685 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5716148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133076958 # The number of ROB reads -system.cpu.rob.rob_writes 196673244 # The number of ROB writes -system.cpu.timesIdled 48172 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 729937 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133590014 # The number of ROB reads +system.cpu.rob.rob_writes 196617452 # The number of ROB writes +system.cpu.timesIdled 47547 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 787728 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559903 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559903 # CPI: Total CPI of All Threads -system.cpu.ipc 1.786025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.786025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116925772 # number of integer regfile reads -system.cpu.int_regfile_writes 57936362 # number of integer regfile writes -system.cpu.fp_regfile_reads 255891 # number of floating regfile reads -system.cpu.fp_regfile_writes 241873 # number of floating regfile writes -system.cpu.misc_regfile_reads 38152 # number of misc regfile reads +system.cpu.cpi 0.567348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.567348 # CPI: Total CPI of All Threads +system.cpu.ipc 1.762586 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.762586 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116851082 # number of integer regfile reads +system.cpu.int_regfile_writes 57926468 # number of integer regfile writes +system.cpu.fp_regfile_reads 255690 # number of floating regfile reads +system.cpu.fp_regfile_writes 241313 # number of floating regfile writes +system.cpu.misc_regfile_reads 38160 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201381 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.852002 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34090259 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205477 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.907907 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.852002 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994104 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994104 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.706489 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34086491 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.904910 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 231989000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.706489 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2773 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2590 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71020605 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71020605 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20525911 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20525911 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13564288 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13564288 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34090199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34090199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34090199 # number of overall hits -system.cpu.dcache.overall_hits::total 34090199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268215 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268215 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1049089 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1049089 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 71020044 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71020044 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20525035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20525035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561393 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561393 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34086428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34086428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34086428 # number of overall hits +system.cpu.dcache.overall_hits::total 34086428 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 268817 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 268817 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1051984 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1051984 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1317304 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1317304 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1317304 # number of overall misses -system.cpu.dcache.overall_misses::total 1317304 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16911598996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16911598996 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85714857886 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85714857886 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102626456882 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102626456882 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102626456882 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102626456882 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20794126 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20794126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1320801 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1320801 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1320801 # number of overall misses +system.cpu.dcache.overall_misses::total 1320801 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17503667749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17503667749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89467046923 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89467046923 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 99750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106970714672 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106970714672 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106970714672 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106970714672 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20793852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20793852 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35407503 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35407503 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35407503 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35407503 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012899 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012899 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071790 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071790 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016393 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016393 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037204 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63052.398248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63052.398248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81704.086008 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81704.086008 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77906.433809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77906.433809 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6293239 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146230 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 64 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 64 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35407229 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35407229 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35407229 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35407229 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012928 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012928 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071988 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071988 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015625 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015625 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037303 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037303 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037303 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65113.693513 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65113.693513 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85046.014885 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85046.014885 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80989.274442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80989.274442 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6831456 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 88055 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.036579 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.581693 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168920 # number of writebacks -system.cpu.dcache.writebacks::total 168920 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206147 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206147 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905681 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 905681 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1111828 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1111828 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1111828 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1111828 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62068 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62068 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143408 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143408 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168921 # number of writebacks +system.cpu.dcache.writebacks::total 168921 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206754 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 206754 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908590 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908590 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115344 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115344 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115344 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115344 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62063 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62063 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205476 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205476 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205476 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205476 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3016288253 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3016288253 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13368781676 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13368781676 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16385069929 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16385069929 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16385069929 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16385069929 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 205457 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205457 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205457 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205457 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3191920501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3191920501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14187677704 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14187677704 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 97750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 97750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17379598205 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17379598205 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17379598205 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17379598205 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002985 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002985 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.016393 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.016393 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.015625 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005803 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005803 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48596.511133 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48596.511133 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93222.007670 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93222.007670 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51430.328875 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51430.328875 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98941.920192 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98941.920192 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 97750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 97750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84589.954127 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84589.954127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84589.954127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84589.954127 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 93674 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.313943 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13810732 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 95722 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 144.279601 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18796346250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.313943 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936677 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936677 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 92948 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.254210 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13805160 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 94996 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 145.323593 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19026930250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.254210 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935671 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935671 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1489 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 370 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 379 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27934642 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27934642 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13810732 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13810732 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13810732 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13810732 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13810732 # number of overall hits -system.cpu.icache.overall_hits::total 13810732 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 108728 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 108728 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 108728 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 108728 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 108728 # number of overall misses -system.cpu.icache.overall_misses::total 108728 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2006428959 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2006428959 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2006428959 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2006428959 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2006428959 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2006428959 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13919460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13919460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13919460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13919460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13919460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13919460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007811 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007811 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007811 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007811 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13805160 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13805160 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13805160 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13805160 # number of overall hits +system.cpu.icache.overall_hits::total 13805160 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 107922 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 107922 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 107922 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 107922 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 107922 # number of overall misses +system.cpu.icache.overall_misses::total 107922 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2071977734 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2071977734 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105068.121063 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104000.917398 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -949,105 +946,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114006 # number of writebacks -system.cpu.l2cache.writebacks::total 114006 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7613 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 114013 # number of writebacks +system.cpu.l2cache.writebacks::total 114013 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7620 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130787 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130787 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7613 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158617 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7613 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158617 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166230 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 472609250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2266008500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2738617750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11494650500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11494650500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472609250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13760659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14233268250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472609250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13760659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14233268250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448386 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.224621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.551892 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.551892 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62079.239459 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81423.230327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77268.226448 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87888.326057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87888.326057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 35450 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130781 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130781 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7620 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158611 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7620 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158611 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166231 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 527900750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2422370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2950270750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12290499750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12290499750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 527900750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14712869750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15240770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 527900750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14712869750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15240770500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448415 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.225710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.553264 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.553264 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69278.313648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87041.681639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 83223.434415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93977.716564 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93977.716564 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 157790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579874 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 771319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6126208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23961408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30087616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 157060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157059 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 769830 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6079744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23960256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30040000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 470120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 469376 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 470120 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 469376 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 470120 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 403980000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 469376 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403609000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 144944965 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 321950247 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 143899236 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 325469999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35442 # Transaction distribution -system.membus.trans_dist::ReadResp 35442 # Transaction distribution -system.membus.trans_dist::Writeback 114006 # Transaction distribution -system.membus.trans_dist::ReadExReq 130787 # Transaction distribution -system.membus.trans_dist::ReadExResp 130787 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17935040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 35449 # Transaction distribution +system.membus.trans_dist::ReadResp 35449 # Transaction distribution +system.membus.trans_dist::Writeback 114013 # Transaction distribution +system.membus.trans_dist::ReadExReq 130781 # Transaction distribution +system.membus.trans_dist::ReadExResp 130781 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446473 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446473 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17935552 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280235 # Request fanout histogram +system.membus.snoop_fanout::samples 280243 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280235 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280243 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280235 # Request fanout histogram -system.membus.reqLayer0.occupancy 1235714000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1525262750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) +system.membus.snoop_fanout::total 280243 # Request fanout histogram +system.membus.reqLayer0.occupancy 786749500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 865056500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 06edb9753..987ba828d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133635 # Number of seconds simulated -sim_ticks 133634727000 # Number of ticks simulated -final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133634 # Number of seconds simulated +sim_ticks 133634149500 # Number of ticks simulated +final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1471745 # Simulator instruction rate (inst/s) -host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2226337698 # Simulator tick rate (ticks/s) -host_mem_usage 297712 # Number of bytes of host memory used -host_seconds 60.02 # Real time elapsed on the host +host_inst_rate 1329181 # Simulator instruction rate (inst/s) +host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2010669405 # Simulator tick rate (ticks/s) +host_mem_usage 301232 # Number of bytes of host memory used +host_seconds 66.46 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,41 +25,17 @@ system.physmem.num_reads::cpu.data 158389 # Nu system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 34272 # Transaction distribution -system.membus.trans_dist::ReadResp 34272 # Transaction distribution -system.membus.trans_dist::Writeback 113982 # Transaction distribution -system.membus.trans_dist::ReadExReq 130881 # Transaction distribution -system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 279135 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 279135 # Request fanout histogram -system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267269454 # number of cpu cycles simulated +system.cpu.numCycles 267268299 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267269454 # Number of busy cycles +system.cpu.num_busy_cycles 267268299 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched @@ -152,13 +128,120 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits +system.cpu.dcache.overall_hits::total 34685671 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses +system.cpu.dcache.overall_misses::total 204344 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363527000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7363527000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9308954000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9308954000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9308954000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9308954000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks +system.cpu.dcache.writebacks::total 168375 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1854278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1854278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7148160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7148160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686268 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id @@ -181,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1278112000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1278112000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1278112000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1278112000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1278112000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1278112000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1277887500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1277887500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1277887500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -199,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16721.335496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16721.335496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16721.335496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16721.335496 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -219,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1125240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1125240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1125240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1125240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1125240000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1125240000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1163233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1163233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1163233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1163233500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14721.335496 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14721.335496 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 131235 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30728.805700 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.509533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.833082 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9976 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 654 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21193 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses @@ -284,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 165153 # nu system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158389 # number of overall misses system.cpu.l2cache.overall_misses::total 165153 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 352084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1430874000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1782958000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6805851000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6805851000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 352084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8236725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8588809000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 352084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8236725000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8588809000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 355241500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1444303000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1799544500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6871263500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6871263500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 355241500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8315566500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8670808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 355241500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8315566500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8670808000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) @@ -319,17 +402,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.588194 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52052.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52016.649702 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52023.751167 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.297981 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.297981 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.164908 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.164908 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,17 +434,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165153 system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 270916000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1100778000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1371694000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235279000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses @@ -373,125 +456,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits -system.cpu.dcache.overall_hits::total 34685671 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks -system.cpu.dcache.writebacks::total 168375 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution @@ -521,5 +497,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 114654000 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 34272 # Transaction distribution +system.membus.trans_dist::ReadResp 34272 # Transaction distribution +system.membus.trans_dist::Writeback 113982 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 279135 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 279135 # Request fanout histogram +system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |