diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt | 1170 |
1 files changed, 587 insertions, 583 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 50bae5738..7abf225fd 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058768 # Number of seconds simulated -sim_ticks 58768125500 # Number of ticks simulated -final_tick 58768125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058750 # Number of seconds simulated +sim_ticks 58750410500 # Number of ticks simulated +final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140139 # Simulator instruction rate (inst/s) -host_op_rate 179217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116134728 # Simulator tick rate (ticks/s) -host_mem_usage 275656 # Number of bytes of host memory used -host_seconds 506.03 # Real time elapsed on the host +host_inst_rate 179920 # Simulator instruction rate (inst/s) +host_op_rate 230092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149057017 # Simulator tick rate (ticks/s) +host_mem_usage 281832 # Number of bytes of host memory used +host_seconds 394.15 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 285632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory -system.physmem.bytes_read::total 8210304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 285632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 285632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5517568 # Number of bytes written to this memory -system.physmem.bytes_written::total 5517568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128286 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86212 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86212 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4860322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 134846431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139706753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4860322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4860322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 93887085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 93887085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 93887085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4860322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 134846431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 233593838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128286 # Number of read requests accepted -system.physmem.writeReqs 86212 # Number of write requests accepted -system.physmem.readBursts 128286 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 86212 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8209920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5515840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8210304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5517568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory +system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory +system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128515 # Number of read requests accepted +system.physmem.writeReqs 86552 # Number of write requests accepted +system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8065 # Per bank write bursts -system.physmem.perBankRdBursts::1 8314 # Per bank write bursts -system.physmem.perBankRdBursts::2 8239 # Per bank write bursts -system.physmem.perBankRdBursts::3 8142 # Per bank write bursts -system.physmem.perBankRdBursts::4 8284 # Per bank write bursts -system.physmem.perBankRdBursts::5 8404 # Per bank write bursts -system.physmem.perBankRdBursts::6 8054 # Per bank write bursts -system.physmem.perBankRdBursts::7 7915 # Per bank write bursts -system.physmem.perBankRdBursts::8 8035 # Per bank write bursts -system.physmem.perBankRdBursts::9 7585 # Per bank write bursts -system.physmem.perBankRdBursts::10 7763 # Per bank write bursts -system.physmem.perBankRdBursts::11 7814 # Per bank write bursts -system.physmem.perBankRdBursts::12 7871 # Per bank write bursts -system.physmem.perBankRdBursts::13 7866 # Per bank write bursts -system.physmem.perBankRdBursts::14 7967 # Per bank write bursts -system.physmem.perBankRdBursts::15 7962 # Per bank write bursts -system.physmem.perBankWrBursts::0 5395 # Per bank write bursts -system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5468 # Per bank write bursts -system.physmem.perBankWrBursts::3 5336 # Per bank write bursts -system.physmem.perBankWrBursts::4 5363 # Per bank write bursts -system.physmem.perBankWrBursts::5 5561 # Per bank write bursts -system.physmem.perBankWrBursts::6 5259 # Per bank write bursts -system.physmem.perBankWrBursts::7 5180 # Per bank write bursts -system.physmem.perBankWrBursts::8 5154 # Per bank write bursts -system.physmem.perBankWrBursts::9 5103 # Per bank write bursts -system.physmem.perBankWrBursts::10 5293 # Per bank write bursts -system.physmem.perBankWrBursts::11 5270 # Per bank write bursts -system.physmem.perBankWrBursts::12 5531 # Per bank write bursts +system.physmem.perBankRdBursts::0 8086 # Per bank write bursts +system.physmem.perBankRdBursts::1 8335 # Per bank write bursts +system.physmem.perBankRdBursts::2 8257 # Per bank write bursts +system.physmem.perBankRdBursts::3 8155 # Per bank write bursts +system.physmem.perBankRdBursts::4 8301 # Per bank write bursts +system.physmem.perBankRdBursts::5 8413 # Per bank write bursts +system.physmem.perBankRdBursts::6 8070 # Per bank write bursts +system.physmem.perBankRdBursts::7 7917 # Per bank write bursts +system.physmem.perBankRdBursts::8 8053 # Per bank write bursts +system.physmem.perBankRdBursts::9 7612 # Per bank write bursts +system.physmem.perBankRdBursts::10 7771 # Per bank write bursts +system.physmem.perBankRdBursts::11 7825 # Per bank write bursts +system.physmem.perBankRdBursts::12 7888 # Per bank write bursts +system.physmem.perBankRdBursts::13 7870 # Per bank write bursts +system.physmem.perBankRdBursts::14 7981 # Per bank write bursts +system.physmem.perBankRdBursts::15 7974 # Per bank write bursts +system.physmem.perBankWrBursts::0 5399 # Per bank write bursts +system.physmem.perBankWrBursts::1 5549 # Per bank write bursts +system.physmem.perBankWrBursts::2 5476 # Per bank write bursts +system.physmem.perBankWrBursts::3 5348 # Per bank write bursts +system.physmem.perBankWrBursts::4 5387 # Per bank write bursts +system.physmem.perBankWrBursts::5 5588 # Per bank write bursts +system.physmem.perBankWrBursts::6 5325 # Per bank write bursts +system.physmem.perBankWrBursts::7 5260 # Per bank write bursts +system.physmem.perBankWrBursts::8 5187 # Per bank write bursts +system.physmem.perBankWrBursts::9 5136 # Per bank write bursts +system.physmem.perBankWrBursts::10 5306 # Per bank write bursts +system.physmem.perBankWrBursts::11 5279 # Per bank write bursts +system.physmem.perBankWrBursts::12 5541 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts -system.physmem.perBankWrBursts::14 5703 # Per bank write bursts -system.physmem.perBankWrBursts::15 5431 # Per bank write bursts +system.physmem.perBankWrBursts::14 5706 # Per bank write bursts +system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58768094000 # Total gap between requests +system.physmem.totGap 58750379000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128286 # Read request sizes (log2) +system.physmem.readPktSize::6 128515 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 86212 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86552 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,106 +194,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.665026 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.783131 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.990632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12260 31.60% 31.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8290 21.36% 52.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4146 10.68% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2807 7.23% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2540 6.55% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1701 4.38% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1262 3.25% 85.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1176 3.03% 88.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4621 11.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.212911 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.385643 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5295 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.269398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.253066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.759205 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4663 88.03% 88.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.13% 88.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 496 9.36% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.30% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8 0.15% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads -system.physmem.totQLat 1679255750 # Total ticks spent queuing -system.physmem.totMemAccLat 4084505750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 641400000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13090.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads +system.physmem.totQLat 1552277750 # Total ticks spent queuing +system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31840.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 139.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 139.71 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 93.89 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.82 # Data bus utilization in percentage +system.physmem.busUtil 1.83 # Data bus utilization in percentage system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing -system.physmem.readRowHits 111800 # Number of row buffer hits during reads -system.physmem.writeRowHits 63851 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.15 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.06 # Row buffer hit rate for writes -system.physmem.avgGap 273979.68 # Average gap between requests -system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153014400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83490000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 509886000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279190800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11659704255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25030042500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41553430275 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.134890 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41510709500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1962220000 # Time in different power states +system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing +system.physmem.readRowHits 112029 # Number of row buffer hits during reads +system.physmem.writeRowHits 70027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes +system.physmem.avgGap 273172.45 # Average gap between requests +system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ) +system.physmem_0.averagePower 705.717335 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15290173000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140215320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76506375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 490152000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 279145440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11133864720 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25491305250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41449291425 # Total energy per rank (pJ) -system.physmem_1.averagePower 705.362708 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 42280803500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1962220000 # Time in different power states +system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ) +system.physmem_1.averagePower 704.382975 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14520166000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827521 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922528 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342114 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9663077 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571727 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14827613 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.008637 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719937 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 176106 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158425 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 17681 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 24889 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -323,7 +321,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +351,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +381,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -414,16 +412,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117536251 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117500821 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179302 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.657421 # CPI: cycles per instruction -system.cpu.ipc 0.603347 # IPC: instructions per cycle +system.cpu.cpi 1.656921 # CPI: cycles per instruction +system.cpu.ipc 0.603529 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -459,474 +457,480 @@ system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 97988256 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19547995 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 156444 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.129500 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637241 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160540 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.586402 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 821026500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.129500 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993196 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993196 # Average percentage of cache occupancy +system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked +system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 156451 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2952 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86035236 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86035236 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22879875 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22879875 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642158 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83370 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83370 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522033 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522033 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605403 # number of overall hits -system.cpu.dcache.overall_hits::total 42605403 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47768 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47768 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207743 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207743 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44596 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44596 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 300107 # number of overall misses -system.cpu.dcache.overall_misses::total 300107 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1443300500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1443300500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16810663000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16810663000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18253963500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18253963500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18253963500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18253963500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927643 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927643 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits +system.cpu.dcache.overall_hits::total 42605646 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses +system.cpu.dcache.overall_misses::total 299891 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127966 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127966 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777544 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777544 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905510 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905510 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002083 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002083 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348499 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348499 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005973 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005973 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006995 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006995 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30214.798610 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30214.798610 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80920.478668 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80920.478668 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71441.008411 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71441.008411 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60824.850803 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60824.850803 # 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average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128383 # number of writebacks -system.cpu.dcache.writebacks::total 128383 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18246 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1012 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50231262 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50231262 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25047260 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25047260 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25047260 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25047260 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25047260 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 97176 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31328.460689 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 268173 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.063758 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 10596662000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 480.299456 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1381.968758 # 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average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 86212 # number of writebacks -system.cpu.l2cache.writebacks::total 86212 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks +system.cpu.l2cache.writebacks::total 86552 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8901461500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9212815000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7167902500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7167902500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 323146000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 323146000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1736095500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1736095500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 323146000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8903998000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9227144000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 323146000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8903998000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9227144000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955557 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402650 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402650 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771291 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.622387 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771291 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.622387 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70929.331248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70929.331248 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69747.647849 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69747.647849 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76442.904888 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76442.904888 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 406103 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 200020 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 99083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 43538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38242 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 45581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477524 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 612223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5703552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24194624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96393 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5517568 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 302514 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.189899 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 97176 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 291272 96.28% 96.28% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11213 3.71% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 302514 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 374972500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68384970 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240842435 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 26006 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86212 # Transaction distribution -system.membus.trans_dist::CleanEvict 6916 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26006 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 349700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13727872 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 26198 # Transaction distribution +system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution +system.membus.trans_dist::CleanEvict 7237 # Transaction distribution +system.membus.trans_dist::ReadExReq 102317 # Transaction distribution +system.membus.trans_dist::ReadExResp 102317 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 221414 # Request fanout histogram +system.membus.snoop_fanout::samples 128515 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 221414 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 221414 # Request fanout histogram -system.membus.reqLayer0.occupancy 586752500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 128515 # Request fanout histogram +system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 676437000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |