diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 455 |
1 files changed, 220 insertions, 235 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bdf692e24..bd8287e69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.025578 # Nu sim_ticks 25577832000 # Number of ticks simulated final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 153227 # Simulator instruction rate (inst/s) -host_op_rate 217448 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55271946 # Simulator tick rate (ticks/s) -host_mem_usage 270340 # Number of bytes of host memory used -host_seconds 462.76 # Real time elapsed on the host +host_inst_rate 133487 # Simulator instruction rate (inst/s) +host_op_rate 189436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48151664 # Simulator tick rate (ticks/s) +host_mem_usage 268312 # Number of bytes of host memory used +host_seconds 531.19 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory @@ -85,29 +85,16 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 128779 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 83944 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 312 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 70134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2062 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 83944 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -137,8 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see @@ -161,7 +147,7 @@ system.physmem.wrQLenPdf::19 3649 # Wh system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3204614448 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5248634448 # Sum of mem lat for all requests +system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests system.physmem.totBusLat 643885000 # Total cycles spent in databus access -system.physmem.totBankLat 1400135000 # Total cycles spent in bank access -system.physmem.avgQLat 24884.99 # Average queueing delay per request -system.physmem.avgBankLat 10872.55 # Average bank access latency per request +system.physmem.totBankLat 1400217500 # Total cycles spent in bank access +system.physmem.avgQLat 24884.85 # Average queueing delay per request +system.physmem.avgBankLat 10873.20 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40757.55 # Average memory access latency +system.physmem.avgMemAccLat 40758.05 # Average memory access latency system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s @@ -247,23 +232,23 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 51155665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12532709 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10561174 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179650 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46029302 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335381 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24855702 54.00% 54.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) @@ -275,42 +260,42 @@ system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46029302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14615111 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8910636 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19475070 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1390460 # Number of cycles decode is unblocking +system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116875392 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16327930 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2553995 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 876400 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19102314 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5530638 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115006216 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4672566 # Number of times rename has blocked due to LSQ full +system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115315088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529845526 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529838425 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16182416 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13070329 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4365711 # Number of conflicting stores. +system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued @@ -318,23 +303,23 @@ system.cpu.iq.iqSquashedInstsIssued 274406 # Nu system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46029302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.330365 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.988633 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10776543 23.41% 23.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8085599 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7427656 16.14% 57.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7135117 15.50% 72.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5408591 11.75% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3911102 8.50% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839411 4.00% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46029302 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available @@ -366,7 +351,7 @@ system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # at system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1003479 40.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued @@ -405,15 +390,15 @@ system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Ty system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued system.cpu.iq.rate 2.096836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464043 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022972 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263297262 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105577839 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109728805 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -427,32 +412,32 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 29 # system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1048423 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45681 # Number of cycles IEW is unblocking +system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5224 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106234972 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030082 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9761 # number of nop insts executed system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed system.cpu.iew.exec_branches 14602542 # Number of branches executed system.cpu.iew.exec_stores 21344564 # Number of stores executed system.cpu.iew.exec_rate 2.076700 # Inst execution rate -system.cpu.iew.wb_sent 105797759 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105578008 # cumulative count of insts written-back +system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back system.cpu.iew.wb_producers 53282087 # num instructions producing a value -system.cpu.iew.wb_consumers 103565148 # num instructions consuming a value +system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back @@ -460,23 +445,23 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44391277 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266941 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764740 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15317735 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11646185 26.24% 60.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462928 7.80% 68.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1875712 4.23% 79.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1949355 4.39% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685853 1.55% 85.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 564106 1.27% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6015739 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44391277 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,12 +472,12 @@ system.cpu.commit.branches 13741505 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6015739 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149959303 # The number of ROB reads +system.cpu.rob.rob_reads 149959530 # The number of ROB reads system.cpu.rob.rob_writes 224865260 # The number of ROB writes -system.cpu.timesIdled 74068 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5126363 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated @@ -500,19 +485,19 @@ system.cpu.cpi 0.721441 # CP system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511661177 # number of integer regfile reads -system.cpu.int_regfile_writes 103341315 # number of integer regfile writes +system.cpu.int_regfile_reads 511661173 # number of integer regfile reads +system.cpu.int_regfile_writes 103341311 # number of integer regfile writes system.cpu.fp_regfile_reads 804 # number of floating regfile reads system.cpu.fp_regfile_writes 688 # number of floating regfile writes system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes system.cpu.icache.replacements 28586 # number of replacements -system.cpu.icache.tagsinuse 1814.278230 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.278230 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits @@ -527,12 +512,12 @@ system.cpu.icache.demand_misses::cpu.inst 34686 # n system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses system.cpu.icache.overall_misses::total 34686 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739119000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739119000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 739119000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739119000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 739119000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739119000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses @@ -545,12 +530,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21308.856599 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21308.856599 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21308.856599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21308.856599 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21308.856599 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -571,34 +556,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 30945 system.cpu.icache.demand_mshr_misses::total 30945 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 30945 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 30945 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600341000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 600341000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600341000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 600341000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600341000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 600341000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 600567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 600567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 600567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 600567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 600567000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 600567000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19400.258523 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19400.258523 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19400.258523 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19400.258523 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19407.561803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19407.561803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19407.561803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19407.561803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 95649 # number of replacements -system.cpu.l2cache.tagsinuse 30090.049168 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30090.044330 # Cycle average of tags in use system.cpu.l2cache.total_refs 88124 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 126758 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.695215 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26935.644891 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1374.538058 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1779.866218 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::writebacks 26935.640674 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1374.538102 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1779.865554 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.822011 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.041948 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.054317 # Average percentage of cache occupancy @@ -631,19 +616,19 @@ system.cpu.l2cache.demand_misses::total 128855 # nu system.cpu.l2cache.overall_misses::cpu.inst 4676 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124179 # number of overall misses system.cpu.l2cache.overall_misses::total 128855 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310311500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482845500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1793157000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 310537500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1482354000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1792891500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6640773000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6640773000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 310311500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8123618500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8433930000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 310311500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8123618500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8433930000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6641217500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6641217500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 310537500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8123571500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8434109000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 310537500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8123571500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8434109000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 30501 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55382 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 85883 # number of ReadReq accesses(hits+misses) @@ -672,19 +657,19 @@ system.cpu.l2cache.demand_miss_rate::total 0.667902 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153306 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.764536 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.667902 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66362.596236 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67641.889426 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67416.986240 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66410.928144 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67619.469027 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67407.004286 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 73.717949 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 73.717949 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64941.989301 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64941.989301 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65452.873385 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66362.596236 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.617480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65452.873385 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64946.336192 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64946.336192 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65454.262543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66410.928144 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65418.238994 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65454.262543 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -717,19 +702,19 @@ system.cpu.l2cache.demand_mshr_misses::total 128779 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124118 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128779 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251333698 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209966181 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461299879 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 251555285 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209463318 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1461018603 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3131809 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3131809 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5384861495 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5384861495 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251333698 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594827676 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6846161374 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251333698 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594827676 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6846161374 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5385248857 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5385248857 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 251555285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6594712175 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6846267460 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 251555285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6594712175 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6846267460 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394731 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308815 # mshr miss rate for ReadReq accesses @@ -743,61 +728,61 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.667508 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764160 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.667508 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53922.698563 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55348.162527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55097.650215 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53970.239219 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55325.159782 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55087.044831 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.849359 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.849359 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52660.077012 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52660.077012 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53922.698563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53133.531607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.094550 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52663.865134 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52663.865134 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53970.239219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53132.601033 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53162.918333 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 158328 # number of replacements -system.cpu.dcache.tagsinuse 4072.315266 # Cycle average of tags in use -system.cpu.dcache.total_refs 44370475 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4072.315155 # Cycle average of tags in use +system.cpu.dcache.total_refs 44370468 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 162424 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.176840 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 273.176797 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.315266 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4072.315155 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26070698 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26070698 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 26070691 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26070691 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18267224 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 18267224 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44337922 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44337922 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44337922 # number of overall hits -system.cpu.dcache.overall_hits::total 44337922 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124470 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124470 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 44337915 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44337915 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44337915 # number of overall hits +system.cpu.dcache.overall_hits::total 44337915 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124477 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124477 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 1582677 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 1582677 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707147 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707147 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707147 # number of overall misses -system.cpu.dcache.overall_misses::total 1707147 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247957000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4247957000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98254010480 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98254010480 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1707154 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707154 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707154 # number of overall misses +system.cpu.dcache.overall_misses::total 1707154 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4246899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4246899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102501967480 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102501967480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102501967480 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102501967480 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -820,16 +805,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34128.360247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34128.360247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62080.898680 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62080.898680 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60042.847792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60042.847792 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60042.847792 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked @@ -840,16 +825,16 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks system.cpu.dcache.writebacks::total 129109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69057 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69057 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544391 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544391 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544391 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544391 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses @@ -858,14 +843,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 162756 system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878248000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878248000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6802862990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6802862990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681110990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8681110990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681110990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8681110990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses @@ -874,14 +859,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33895.439698 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33895.439698 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63375.003400 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63375.003400 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53338.193308 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53338.193308 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |