diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1766 |
1 files changed, 887 insertions, 879 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 854b1472f..7d5e42cd5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033525 # Number of seconds simulated -sim_ticks 33524756000 # Number of ticks simulated -final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037283 # Number of seconds simulated +sim_ticks 37283333000 # Number of ticks simulated +final_tick 37283333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 128434 # Simulator instruction rate (inst/s) -host_op_rate 164252 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60722809 # Simulator tick rate (ticks/s) -host_mem_usage 277836 # Number of bytes of host memory used -host_seconds 552.10 # Real time elapsed on the host +host_inst_rate 125888 # Simulator instruction rate (inst/s) +host_op_rate 160996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66191855 # Simulator tick rate (ticks/s) +host_mem_usage 284264 # Number of bytes of host memory used +host_seconds 563.26 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory -system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory -system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 45743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96439 # Number of read requests responded to by this memory -system.physmem.num_reads::total 153088 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97140 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97140 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20819958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 87325080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 184105620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 292250658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20819958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20819958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 185443855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 185443855 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 185443855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20819958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 87325080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 184105620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 477694513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 153089 # Number of read requests accepted -system.physmem.writeReqs 97140 # Number of write requests accepted -system.physmem.readBursts 153089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97140 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9788224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 6215872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9797696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6216960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2379328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5690752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6174592 # Number of bytes read from this memory +system.physmem.bytes_read::total 14244672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2379328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2379328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224768 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224768 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88918 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96478 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222573 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97262 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97262 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 63817470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 152635281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 165612661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 382065412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 63817470 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 63817470 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166958464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166958464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166958464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 63817470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 152635281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 165612661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 549023876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222574 # Number of read requests accepted +system.physmem.writeReqs 97262 # Number of write requests accepted +system.physmem.readBursts 222574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97262 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14235136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 6223360 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14244736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9103 # Per bank write bursts -system.physmem.perBankRdBursts::1 9407 # Per bank write bursts -system.physmem.perBankRdBursts::2 9452 # Per bank write bursts -system.physmem.perBankRdBursts::3 11458 # Per bank write bursts -system.physmem.perBankRdBursts::4 10748 # Per bank write bursts -system.physmem.perBankRdBursts::5 11390 # Per bank write bursts -system.physmem.perBankRdBursts::6 10031 # Per bank write bursts -system.physmem.perBankRdBursts::7 8920 # Per bank write bursts -system.physmem.perBankRdBursts::8 9321 # Per bank write bursts -system.physmem.perBankRdBursts::9 9437 # Per bank write bursts -system.physmem.perBankRdBursts::10 9070 # Per bank write bursts -system.physmem.perBankRdBursts::11 9080 # Per bank write bursts -system.physmem.perBankRdBursts::12 8731 # Per bank write bursts -system.physmem.perBankRdBursts::13 8724 # Per bank write bursts -system.physmem.perBankRdBursts::14 9025 # Per bank write bursts -system.physmem.perBankRdBursts::15 9044 # Per bank write bursts -system.physmem.perBankWrBursts::0 5968 # Per bank write bursts -system.physmem.perBankWrBursts::1 6230 # Per bank write bursts -system.physmem.perBankWrBursts::2 6083 # Per bank write bursts -system.physmem.perBankWrBursts::3 6155 # Per bank write bursts -system.physmem.perBankWrBursts::4 6058 # Per bank write bursts -system.physmem.perBankWrBursts::5 6286 # Per bank write bursts -system.physmem.perBankWrBursts::6 6021 # Per bank write bursts -system.physmem.perBankWrBursts::7 5958 # Per bank write bursts -system.physmem.perBankWrBursts::8 5969 # Per bank write bursts -system.physmem.perBankWrBursts::9 6064 # Per bank write bursts -system.physmem.perBankWrBursts::10 6185 # Per bank write bursts -system.physmem.perBankWrBursts::11 5907 # Per bank write bursts -system.physmem.perBankWrBursts::12 6058 # Per bank write bursts -system.physmem.perBankWrBursts::13 6089 # Per bank write bursts -system.physmem.perBankWrBursts::14 6121 # Per bank write bursts -system.physmem.perBankWrBursts::15 5971 # Per bank write bursts +system.physmem.perBankRdBursts::0 9684 # Per bank write bursts +system.physmem.perBankRdBursts::1 9951 # Per bank write bursts +system.physmem.perBankRdBursts::2 12571 # Per bank write bursts +system.physmem.perBankRdBursts::3 25345 # Per bank write bursts +system.physmem.perBankRdBursts::4 17391 # Per bank write bursts +system.physmem.perBankRdBursts::5 22070 # Per bank write bursts +system.physmem.perBankRdBursts::6 11722 # Per bank write bursts +system.physmem.perBankRdBursts::7 14054 # Per bank write bursts +system.physmem.perBankRdBursts::8 11726 # Per bank write bursts +system.physmem.perBankRdBursts::9 15447 # Per bank write bursts +system.physmem.perBankRdBursts::10 11755 # Per bank write bursts +system.physmem.perBankRdBursts::11 11322 # Per bank write bursts +system.physmem.perBankRdBursts::12 9441 # Per bank write bursts +system.physmem.perBankRdBursts::13 9563 # Per bank write bursts +system.physmem.perBankRdBursts::14 9879 # Per bank write bursts +system.physmem.perBankRdBursts::15 20503 # Per bank write bursts +system.physmem.perBankWrBursts::0 5981 # Per bank write bursts +system.physmem.perBankWrBursts::1 6205 # Per bank write bursts +system.physmem.perBankWrBursts::2 6090 # Per bank write bursts +system.physmem.perBankWrBursts::3 6159 # Per bank write bursts +system.physmem.perBankWrBursts::4 6110 # Per bank write bursts +system.physmem.perBankWrBursts::5 6252 # Per bank write bursts +system.physmem.perBankWrBursts::6 5998 # Per bank write bursts +system.physmem.perBankWrBursts::7 5984 # Per bank write bursts +system.physmem.perBankWrBursts::8 5961 # Per bank write bursts +system.physmem.perBankWrBursts::9 6093 # Per bank write bursts +system.physmem.perBankWrBursts::10 6222 # Per bank write bursts +system.physmem.perBankWrBursts::11 5895 # Per bank write bursts +system.physmem.perBankWrBursts::12 6037 # Per bank write bursts +system.physmem.perBankWrBursts::13 6052 # Per bank write bursts +system.physmem.perBankWrBursts::14 6175 # Per bank write bursts +system.physmem.perBankWrBursts::15 6026 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33524744500 # Total gap between requests +system.physmem.totGap 37283321500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153089 # Read request sizes (log2) +system.physmem.readPktSize::6 222574 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97140 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13705 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 71 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97262 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 113358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14014 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,107 +198,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 96335 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 166.118316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 104.810468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 234.858667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 60546 62.85% 62.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22368 23.22% 86.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3987 4.14% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1542 1.60% 91.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 931 0.97% 92.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 863 0.90% 93.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 636 0.66% 94.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 773 0.80% 95.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4689 4.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 96335 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5845 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.165269 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.412430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5844 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5845 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.616424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.570046 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.313075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4545 77.76% 77.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 48 0.82% 78.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 753 12.88% 91.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 215 3.68% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 127 2.17% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 88 1.51% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 42 0.72% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.29% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.09% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5845 # Writes before turning the bus around for reads -system.physmem.totQLat 6714977565 # Total ticks spent queuing -system.physmem.totMemAccLat 9582621315 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 764705000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43905.67 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 132565 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 154.319345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.621145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 210.186270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82651 62.35% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32256 24.33% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6354 4.79% 91.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2721 2.05% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1163 0.88% 94.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1002 0.76% 95.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 846 0.64% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 812 0.61% 96.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4760 3.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132565 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.864488 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.288279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5866 99.86% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 7 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512747 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.243213 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4672 79.54% 79.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 38 0.65% 80.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 729 12.41% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 209 3.56% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 107 1.82% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 58 0.99% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.53% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 16 0.27% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.19% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5874 # Writes before turning the bus around for reads +system.physmem.totQLat 7261518854 # Total ticks spent queuing +system.physmem.totMemAccLat 11431968854 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112120000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32647.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62655.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 291.97 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 185.41 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 292.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 185.44 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 51397.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 166.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 382.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 166.96 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.73 # Data bus utilization in percentage -system.physmem.busUtilRead 2.28 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.45 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing +system.physmem.busUtil 4.29 # Data bus utilization in percentage +system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing -system.physmem.readRowHits 120882 # Number of row buffer hits during reads -system.physmem.writeRowHits 32837 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes -system.physmem.avgGap 133976.26 # Average gap between requests -system.physmem.pageHitRate 61.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378438480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206489250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 627572400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 315854640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15155251200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6817959750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25690916520 # Total energy per rank (pJ) -system.physmem_0.averagePower 766.433942 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11238384768 # Time in different power states -system.physmem_0.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem.readRowHits 157163 # Number of row buffer hits during reads +system.physmem.writeRowHits 29925 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.77 # Row buffer hit rate for writes +system.physmem.avgGap 116570.12 # Average gap between requests +system.physmem.pageHitRate 58.52 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 537077520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 293048250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 957496800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 315958320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 23206024395 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2012333250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 29756923815 # Total energy per rank (pJ) +system.physmem_0.averagePower 798.183082 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3201879547 # Time in different power states +system.physmem_0.memoryStateTime::REF 1244880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21162395232 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32834079203 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 349513920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 190707000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 564751200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313295040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13737724470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ) -system.physmem_1.averagePower 757.956338 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states -system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states +system.physmem_1.actEnergy 464871960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 253650375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 777051600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313949520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 21592790730 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3427453500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 29264752965 # Total energy per rank (pJ) +system.physmem_1.averagePower 784.981262 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 5568954615 # Time in different power states +system.physmem_1.memoryStateTime::REF 1244880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30467009135 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17055826 # Number of BP lookups -system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits +system.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17068882 # Number of BP lookups +system.cpu.branchPred.condPredicted 11456187 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 597693 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9279962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7373647 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.457728 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1854916 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101589 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233217 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 195584 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37633 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22185 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +330,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +360,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +390,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,130 +421,130 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 67049513 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 74566667 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1224115 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12656 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22418203 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68072 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66043378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.665685 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.303820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5541341 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87099155 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17068882 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9424147 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 65038748 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1222021 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30739 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22432357 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69340 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 71233545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.545306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.327706 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20904696 31.65% 31.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8151419 12.34% 44.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9105743 13.79% 57.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27881520 42.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 26059108 36.58% 36.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8166381 11.46% 48.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9112889 12.79% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27895167 39.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66043378 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.254377 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.297952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8568047 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20331818 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31035970 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5662045 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 445498 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3138719 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168392 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100377883 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2807284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 445498 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13201972 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6021135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 843957 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31848304 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13682512 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98401933 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 864722 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3910657 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69359 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4461482 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5194138 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103316551 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453880702 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114363596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 71233545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.228908 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.168071 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8928507 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 25221623 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30949867 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5689167 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 444381 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3134053 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168503 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100299686 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2798262 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 444381 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13572247 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10675080 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 842433 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31772787 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13926617 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98328841 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 859440 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4124148 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69439 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4596367 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5265270 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103255092 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453545884 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114277398 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 716 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9687182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18952 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18977 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12759909 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24172969 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21779154 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1438398 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2287665 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97467378 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34812 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94518121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 609879 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6819583 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18148637 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1026 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66043378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.431152 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.152558 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9625723 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18974 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19002 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12839389 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24155878 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21759886 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1433320 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2321800 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97398916 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34841 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94478155 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 593843 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6751150 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17960313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1055 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 71233545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.326316 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.168839 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17971444 27.21% 27.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17366377 26.30% 53.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17018277 25.77% 79.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11635318 17.62% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2050574 3.10% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1388 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23112455 32.45% 32.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17441476 24.48% 56.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17040128 23.92% 80.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11602976 16.29% 97.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2035055 2.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1455 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66043378 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 71233545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6745698 22.64% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 37 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11091756 37.22% 59.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11960162 40.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6731709 22.63% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11081856 37.26% 59.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11930481 40.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49324075 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86626 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49303920 52.19% 52.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86563 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -563,89 +565,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23968009 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21139361 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23954982 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21132627 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94518121 # Type of FU issued -system.cpu.iq.rate 1.409676 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29797653 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315259 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285486823 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104332871 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93229184 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 329 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 574 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124315586 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1381077 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94478155 # Type of FU issued +system.cpu.iq.rate 1.267029 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29744084 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314825 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 290527434 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104196109 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93201296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 348 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 616 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124222040 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368179 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1306707 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11900 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1223416 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1289616 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2048 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1204148 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147221 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 186554 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 144864 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185613 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 445498 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 578203 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 566637 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97517928 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 444381 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 624509 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1115710 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97447803 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24172969 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21779154 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18892 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 562180 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11900 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250835 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 223196 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 474031 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93719339 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23701905 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 798782 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24155878 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21759886 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18921 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1617 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1111435 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 249911 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221890 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 471801 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93685311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23691817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 792844 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15738 # number of nop insts executed -system.cpu.iew.exec_refs 44631646 # number of memory reference insts executed -system.cpu.iew.exec_branches 14212084 # Number of branches executed -system.cpu.iew.exec_stores 20929741 # Number of stores executed -system.cpu.iew.exec_rate 1.397763 # Inst execution rate -system.cpu.iew.wb_sent 93338125 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93229268 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44994314 # num instructions producing a value -system.cpu.iew.wb_consumers 76693481 # num instructions consuming a value -system.cpu.iew.wb_rate 1.390454 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586677 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5957514 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 14046 # number of nop insts executed +system.cpu.iew.exec_refs 44616394 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207133 # Number of branches executed +system.cpu.iew.exec_stores 20924577 # Number of stores executed +system.cpu.iew.exec_rate 1.256397 # Inst execution rate +system.cpu.iew.wb_sent 93308677 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93201392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44951021 # num instructions producing a value +system.cpu.iew.wb_consumers 76633881 # num instructions consuming a value +system.cpu.iew.wb_rate 1.249907 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586569 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5894305 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 432296 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65078464 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.393520 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.163869 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431064 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 70277782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.290424 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.118209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31565690 48.50% 48.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16713735 25.68% 74.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4316875 6.63% 80.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4188712 6.44% 87.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1942227 2.98% 90.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1235606 1.90% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 754913 1.16% 93.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 587526 0.90% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3773180 5.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 36842990 52.42% 52.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16674938 23.73% 76.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4291723 6.11% 82.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4149088 5.90% 88.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947878 2.77% 90.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1240751 1.77% 92.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 737656 1.05% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580756 0.83% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3812002 5.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65078464 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 70277782 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -691,546 +693,552 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3773180 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 157925658 # The number of ROB reads -system.cpu.rob.rob_writes 194257744 # The number of ROB writes -system.cpu.timesIdled 27177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1006135 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3812002 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 163022945 # The number of ROB reads +system.cpu.rob.rob_writes 194122181 # The number of ROB writes +system.cpu.timesIdled 54257 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3333122 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.945589 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.945589 # CPI: Total CPI of All Threads -system.cpu.ipc 1.057542 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.057542 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102008139 # number of integer regfile reads -system.cpu.int_regfile_writes 56630693 # number of integer regfile writes -system.cpu.fp_regfile_reads 48 # number of floating regfile reads -system.cpu.fp_regfile_writes 42 # number of floating regfile writes -system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads -system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes -system.cpu.misc_regfile_reads 44112663 # number of misc regfile reads +system.cpu.cpi 1.051603 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.051603 # CPI: Total CPI of All Threads +system.cpu.ipc 0.950930 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.950930 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101976703 # number of integer regfile reads +system.cpu.int_regfile_writes 56611271 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.fp_regfile_writes 48 # number of floating regfile writes +system.cpu.cc_regfile_reads 345090037 # number of cc regfile reads +system.cpu.cc_regfile_writes 38758670 # number of cc regfile writes +system.cpu.misc_regfile_reads 44101489 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 486293 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484862 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.874566 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40338135 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485374 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.107325 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 151605500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.874566 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84467396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84467396 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21414103 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21414103 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18832546 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18832546 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60212 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60212 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15310 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15310 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40239255 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40239255 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40299249 # number of overall hits -system.cpu.dcache.overall_hits::total 40299249 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 567937 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 567937 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1017212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1017212 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68679 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68679 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1585149 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1585149 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1653828 # number of overall misses -system.cpu.dcache.overall_misses::total 1653828 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9485185000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9485185000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14264451930 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14264451930 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5633500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5633500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23749636930 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23749636930 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23749636930 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23749636930 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21974503 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21974503 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40246649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40246649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40306861 # number of overall hits +system.cpu.dcache.overall_hits::total 40306861 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 566310 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 566310 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1017355 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1017355 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68643 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68643 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 613 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 613 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1583665 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583665 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1652308 # number of overall misses +system.cpu.dcache.overall_misses::total 1652308 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13581553500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13581553500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13903205430 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13903205430 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5738500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5738500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27484758930 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27484758930 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27484758930 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27484758930 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980413 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128673 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128673 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15924 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15924 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41824404 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41824404 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41953077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41953077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025845 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025845 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051245 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051245 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.533748 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.533748 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038809 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038809 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037900 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037900 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039421 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039421 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9115.695793 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9115.695793 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14982.589605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks -system.cpu.dcache.writebacks::total 486293 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1136028 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1136028 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1136028 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1136028 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 300545 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 300545 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148576 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148576 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37700 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37700 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 449121 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 449121 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 486821 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 486821 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3693304500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3693304500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2308719470 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2308719470 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1888982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1888982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6002023970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6002023970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7891006470 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7891006470 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013677 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013677 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010738 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010738 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011604 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325000 # number of replacements -system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy +system.cpu.dcache.demand_accesses::cpu.data 41830314 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830314 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41959169 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41959169 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051252 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051252 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532715 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532715 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038498 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037859 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037859 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039379 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039379 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9361.337684 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9361.337684 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17355.159664 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16634.161990 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2820837 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 130956 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 21.540342 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484862 # number of writebacks +system.cpu.dcache.writebacks::total 484862 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267183 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 267183 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868792 # 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number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947913971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8947913971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10858005971 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10858005971 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292546 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292546 # 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Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.404253 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996883 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996883 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22083387 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22083387 # number of overall hits -system.cpu.icache.overall_hits::total 22083387 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 334707 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 334707 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 334707 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 334707 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 334707 # number of overall misses -system.cpu.icache.overall_misses::total 334707 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3526570179 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3526570179 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3526570179 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3526570179 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3526570179 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3526570179 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22418094 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22418094 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22418094 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22418094 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22418094 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22418094 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014930 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014930 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014930 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014930 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014930 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014930 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10536.290484 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10536.290484 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10536.290484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10536.290484 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 264177 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45190725 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45190725 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22094458 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22094458 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22094458 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22094458 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22094458 # number of overall hits +system.cpu.icache.overall_hits::total 22094458 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337685 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337685 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337685 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 337685 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 337685 # number of overall misses +system.cpu.icache.overall_misses::total 337685 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5566889382 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5566889382 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5566889382 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5566889382 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5566889382 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5566889382 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22432143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22432143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22432143 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22432143 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22432143 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22432143 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015054 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015054 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015054 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015054 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015054 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015054 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16485.450589 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16485.450589 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16485.450589 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16485.450589 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 546680 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 53 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25668 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325000 # number of writebacks -system.cpu.icache.writebacks::total 325000 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 9178 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 9178 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 9178 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 9178 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 9178 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325529 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 325529 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 325529 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 325529 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 325529 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 325529 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3259633220 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3259633220 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3259633220 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3259633220 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.298114 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26.500000 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2745 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12082 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 548 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 25510486 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25510486 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 254711 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 254711 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85034.464643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076567 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.076567 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113980 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239434 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239434 # 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average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79172.344515 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78660.847713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81971.927880 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81018.569251 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78660.847713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81971.927880 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81018.569251 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 424 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 97140 # number of writebacks -system.cpu.l2cache.writebacks::total 97140 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3182 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3182 # number of ReadExReq MSHR hits +system.cpu.l2cache.unused_prefetches 412 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 97262 # number of writebacks +system.cpu.l2cache.writebacks::total 97262 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2980 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 2980 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8398 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37178 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37178 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80520 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80520 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 37178 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 88918 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 126096 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 37178 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 88918 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115252 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 241348 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 9954483724 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 680267500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 680267500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2701591500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2701591500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5893524000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5893524000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2701591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6573791500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9275383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2701591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6573791500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 9954483724 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19229866724 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033507 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.110605 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.110605 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069739 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056514 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113894 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239093 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239093 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155329 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.208431 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325529 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 338193 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976039 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1459935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2435974 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41632640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62278272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103910912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318692 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6218112 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1131024 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.140178 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.373630 # Request fanout histogram +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297300 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73193.293592 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73558.106522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79676.925949 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1622603 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810817 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79904 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18775 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 663212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 351973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 556066 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 144126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 326440 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336773 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 978779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455634 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2434413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41749696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62095104 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103844800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 269627 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6225728 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1081438 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091286 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288019 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 983264 86.94% 86.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136975 12.11% 99.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10785 0.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 982719 90.87% 90.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98718 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 33524756000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 144751 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution -system.membus.trans_dist::CleanEvict 28117 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16 # Transaction distribution -system.membus.trans_dist::ReadExReq 8337 # Transaction distribution -system.membus.trans_dist::ReadExResp 8337 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 431450 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16014592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16014592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoop_fanout::total 1081438 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1622078500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 489794228 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 728148836 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 348072 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214175 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97262 # Transaction distribution +system.membus.trans_dist::CleanEvict 28224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 12 # Transaction distribution +system.membus.trans_dist::ReadExReq 8398 # Transaction distribution +system.membus.trans_dist::ReadExResp 8398 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570645 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20469440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20469440 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 278362 # Request fanout histogram +system.membus.snoop_fanout::samples 222586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 278362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 278362 # Request fanout histogram -system.membus.reqLayer0.occupancy 747889943 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222586 # Request fanout histogram +system.membus.reqLayer0.occupancy 837454269 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 799798093 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1175863136 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |