diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 2524 |
1 files changed, 1262 insertions, 1262 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 8304f1e87..477f394fc 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,1266 +1,1266 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.037944 # Number of seconds simulated -sim_ticks 37944194500 # Number of ticks simulated -final_tick 37944194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 220724 # Simulator instruction rate (inst/s) -host_op_rate 282280 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118113932 # Simulator tick rate (ticks/s) -host_mem_usage 283128 # Number of bytes of host memory used -host_seconds 321.25 # Real time elapsed on the host -sim_insts 70907652 # Number of instructions simulated -sim_ops 90682607 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2366464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5687552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176 # Number of bytes read from this memory -system.physmem.bytes_read::total 14232192 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2366464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2366464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6224000 # Number of bytes written to this memory -system.physmem.bytes_written::total 6224000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 36976 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 88868 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96534 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222378 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97250 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97250 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 62366958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 149892548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 162822695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 375082201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 62366958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 62366958 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 164030363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 164030363 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 164030363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 62366958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 149892548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 162822695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 539112564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222379 # Number of read requests accepted -system.physmem.writeReqs 97250 # Number of write requests accepted -system.physmem.readBursts 222379 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97250 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14222400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6222336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14232256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6224000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9631 # Per bank write bursts -system.physmem.perBankRdBursts::1 9947 # Per bank write bursts -system.physmem.perBankRdBursts::2 12518 # Per bank write bursts -system.physmem.perBankRdBursts::3 24674 # Per bank write bursts -system.physmem.perBankRdBursts::4 17362 # Per bank write bursts -system.physmem.perBankRdBursts::5 22065 # Per bank write bursts -system.physmem.perBankRdBursts::6 11751 # Per bank write bursts -system.physmem.perBankRdBursts::7 14087 # Per bank write bursts -system.physmem.perBankRdBursts::8 11655 # Per bank write bursts -system.physmem.perBankRdBursts::9 16110 # Per bank write bursts -system.physmem.perBankRdBursts::10 11699 # Per bank write bursts -system.physmem.perBankRdBursts::11 11328 # Per bank write bursts -system.physmem.perBankRdBursts::12 9447 # Per bank write bursts -system.physmem.perBankRdBursts::13 9546 # Per bank write bursts -system.physmem.perBankRdBursts::14 9858 # Per bank write bursts -system.physmem.perBankRdBursts::15 20547 # Per bank write bursts -system.physmem.perBankWrBursts::0 5941 # Per bank write bursts -system.physmem.perBankWrBursts::1 6221 # Per bank write bursts -system.physmem.perBankWrBursts::2 6116 # Per bank write bursts -system.physmem.perBankWrBursts::3 6136 # Per bank write bursts -system.physmem.perBankWrBursts::4 6032 # Per bank write bursts -system.physmem.perBankWrBursts::5 6294 # Per bank write bursts -system.physmem.perBankWrBursts::6 6000 # Per bank write bursts -system.physmem.perBankWrBursts::7 5967 # Per bank write bursts -system.physmem.perBankWrBursts::8 5964 # Per bank write bursts -system.physmem.perBankWrBursts::9 6073 # Per bank write bursts -system.physmem.perBankWrBursts::10 6219 # Per bank write bursts -system.physmem.perBankWrBursts::11 5919 # Per bank write bursts -system.physmem.perBankWrBursts::12 6077 # Per bank write bursts -system.physmem.perBankWrBursts::13 6073 # Per bank write bursts -system.physmem.perBankWrBursts::14 6160 # Per bank write bursts -system.physmem.perBankWrBursts::15 6032 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37944183500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222379 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97250 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 111691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60016 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15678 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 92 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132661 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 154.093818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.620444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 209.524421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82661 62.31% 62.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32331 24.37% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6343 4.78% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2828 2.13% 93.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1153 0.87% 94.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1000 0.75% 95.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 785 0.59% 95.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 836 0.63% 96.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4724 3.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132661 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5873 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.833986 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 211.191475 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5868 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5873 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.554401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.514141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.221324 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4642 79.04% 79.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 60 1.02% 80.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 721 12.28% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 237 4.04% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 117 1.99% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 0.85% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.36% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.17% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.15% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads -system.physmem.totQLat 8400725955 # Total ticks spent queuing -system.physmem.totMemAccLat 12567444705 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1111125000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37802.79 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56552.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 163.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 375.08 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 164.03 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.21 # Data bus utilization in percentage -system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 156951 # Number of row buffer hits during reads -system.physmem.writeRowHits 29827 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.67 # Row buffer hit rate for writes -system.physmem.avgGap 118713.21 # Average gap between requests -system.physmem.pageHitRate 58.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 506618700 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 269259045 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 871329900 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 254250540 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3004974960.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2939010630 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75129120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12925802790 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1053663840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 77310705 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 21977801430 # Total energy per rank (pJ) -system.physmem_0.averagePower 579.213801 # Core power per rank (mW) -system.physmem_0.totalIdleTime 31303061618 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 43527335 # Time in different power states -system.physmem_0.memoryStateTime::REF 1271434000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 212368250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2743799817 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5326073297 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28346991801 # Time in different power states -system.physmem_1.actEnergy 440652240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 234189450 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 715349460 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 253258740 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2887578720.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2772991290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 73095360 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11918051910 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1378656480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 511952955 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 21185918985 # Total energy per rank (pJ) -system.physmem_1.averagePower 558.344142 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31672221792 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 50102341 # Time in different power states -system.physmem_1.memoryStateTime::REF 1221978000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1946071250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3589983863 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4999892367 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26136166679 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17059712 # Number of BP lookups -system.cpu.branchPred.condPredicted 11436495 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 610883 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9177884 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7343978 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.018205 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1859096 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101568 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 235599 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 198019 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37580 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22235 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 75888390 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5573583 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87028801 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17059712 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9401093 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 65975948 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1248205 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 11552 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 20 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 32118 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22429818 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69336 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 72217323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.523317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.330813 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27066857 37.48% 37.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8167411 11.31% 48.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9106696 12.61% 61.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27876359 38.60% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 72217323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224800 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.146800 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8951903 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 26171728 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30965562 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5674558 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 453572 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6946604 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172649 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100221832 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2852875 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 453572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13609160 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11386876 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 864961 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31760902 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14141852 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98228803 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 864073 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4236637 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68346 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4658326 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5438830 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103135317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453117590 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114171014 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 768 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9505948 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 19046 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12792135 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24137829 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21734716 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1433415 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2312086 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97293576 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34871 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94397579 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 595173 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6645840 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17792691 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1085 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 72217323 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.307132 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.170641 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24111122 33.39% 33.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17469676 24.19% 57.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17013658 23.56% 81.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11592271 16.05% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2029206 2.81% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1390 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 72217323 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6732689 22.67% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 34 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11048676 37.21% 59.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11914326 40.12% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 49 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49269666 52.19% 52.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86409 0.09% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.29% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23933468 25.35% 77.64% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21107870 22.36% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 70 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94397579 # Type of FU issued -system.cpu.iq.rate 1.243900 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29695795 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314582 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291303077 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 103985333 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93134762 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 690 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124093153 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1368431 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1271567 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1549 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11881 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1178978 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 147641 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185447 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 453572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 612952 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1120138 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97344492 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24137829 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21734716 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18951 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1593 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1115880 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11881 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 249751 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 231660 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 481411 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93615083 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23674361 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 782496 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 16045 # number of nop insts executed -system.cpu.iew.exec_refs 44580255 # number of memory reference insts executed -system.cpu.iew.exec_branches 14200394 # Number of branches executed -system.cpu.iew.exec_stores 20905894 # Number of stores executed -system.cpu.iew.exec_rate 1.233589 # Inst execution rate -system.cpu.iew.wb_sent 93237318 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93134858 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44916796 # num instructions producing a value -system.cpu.iew.wb_consumers 76568590 # num instructions consuming a value -system.cpu.iew.wb_rate 1.227261 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586622 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5786029 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 440353 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 71261477 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.272611 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.107279 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 37792643 53.03% 53.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16691471 23.42% 76.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4304606 6.04% 82.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4169247 5.85% 88.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1943443 2.73% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1235947 1.73% 92.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 743394 1.04% 93.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 579944 0.81% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3800782 5.33% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 71261477 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70913204 # Number of instructions committed -system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 43422000 # Number of memory references committed -system.cpu.commit.loads 22866262 # Number of loads committed -system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13741468 # Number of branches committed -system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 81528527 # Number of committed integer instructions. -system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47186033 52.03% 52.03% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20555706 22.67% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3800782 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 163909584 # The number of ROB reads -system.cpu.rob.rob_writes 193905843 # The number of ROB writes -system.cpu.timesIdled 54309 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3671067 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70907652 # Number of Instructions Simulated -system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.070243 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.070243 # CPI: Total CPI of All Threads -system.cpu.ipc 0.934368 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.934368 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101911048 # number of integer regfile reads -system.cpu.int_regfile_writes 56566498 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes -system.cpu.cc_regfile_reads 344842465 # number of cc regfile reads -system.cpu.cc_regfile_writes 38739142 # number of cc regfile writes -system.cpu.misc_regfile_reads 44068796 # number of misc regfile reads -system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484861 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.868864 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40324171 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485373 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.078727 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 154340500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.868864 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84436477 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84436477 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21401665 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21401665 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831129 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831129 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60098 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60098 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15305 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15305 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40232794 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40232794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40292892 # number of overall hits -system.cpu.dcache.overall_hits::total 40292892 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 563103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 563103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018772 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018772 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68943 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68943 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1581875 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1581875 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1650818 # number of overall misses -system.cpu.dcache.overall_misses::total 1650818 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14421291500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14421291500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14222478926 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14222478926 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5900000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5900000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28643770426 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28643770426 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28643770426 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28643770426 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21964768 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21964768 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 129041 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 129041 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41814669 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41814669 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41943710 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41943710 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025637 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025637 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.534272 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.534272 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038812 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038812 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037831 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037831 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039358 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039358 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25610.397210 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25610.397210 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13960.414034 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13960.414034 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9546.925566 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9546.925566 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18107.480317 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18107.480317 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17351.258846 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17351.258846 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 104 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2957939 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131286 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.933333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.530498 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484861 # number of writebacks -system.cpu.dcache.writebacks::total 484861 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263994 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 263994 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870189 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870189 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1134183 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1134183 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1134183 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1134183 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299109 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299109 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148583 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148583 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37695 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37695 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447692 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447692 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485387 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485387 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7100123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7100123000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2335671469 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2335671469 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001428000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001428000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9435794469 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9435794469 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11437222469 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11437222469 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010707 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010707 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011572 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011572 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23737.577271 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23737.577271 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15719.641339 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15719.641339 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53095.317681 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53095.317681 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21076.531341 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21076.531341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23563.100102 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23563.100102 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325105 # number of replacements -system.cpu.icache.tags.tagsinuse 510.398248 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22092527 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 325617 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.848199 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1172472500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.398248 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996872 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996872 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 333 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45184842 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45184842 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22092527 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22092527 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22092527 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22092527 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22092527 # number of overall hits -system.cpu.icache.overall_hits::total 22092527 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 337079 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 337079 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 337079 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 337079 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 337079 # number of overall misses -system.cpu.icache.overall_misses::total 337079 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5811924859 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5811924859 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5811924859 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5811924859 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5811924859 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5811924859 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22429606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22429606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22429606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22429606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22429606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22429606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015028 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015028 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015028 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015028 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17242.025932 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17242.025932 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17242.025932 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17242.025932 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 559324 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 118 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25723 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.744120 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 39.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325105 # number of writebacks -system.cpu.icache.writebacks::total 325105 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11448 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11448 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11448 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 11448 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 11448 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 11448 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325631 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 325631 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 325631 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 325631 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 325631 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 325631 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5369635927 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5369635927 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5369635927 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5369635927 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5369635927 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5369635927 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014518 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014518 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014518 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16489.940844 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16489.940844 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16489.940844 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16489.940844 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16489.940844 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16489.940844 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822760 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825879 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2736 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78985 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 125384 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15697.006900 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 681705 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141714 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.810428 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15640.024987 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 56.981913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.954591 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003478 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958069 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 23 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16307 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 10 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2537 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12202 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 564 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 868 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25485617 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25485617 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 259863 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 259863 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 470316 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 470316 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137267 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137267 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 288609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 288609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 256036 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 256036 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 288609 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 393303 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 681912 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 288609 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 393303 # number of overall hits -system.cpu.l2cache.overall_hits::total 681912 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11350 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11350 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 37008 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 37008 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 80720 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 80720 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 37008 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 92070 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129078 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 37008 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 92070 # number of overall misses -system.cpu.l2cache.overall_misses::total 129078 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1217096500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1217096500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 3145310000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 3145310000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6905491500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6905491500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 3145310000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8122588000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11267898000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 3145310000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8122588000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11267898000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 259863 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 259863 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 470316 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 470316 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148617 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148617 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325617 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 325617 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336756 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 336756 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 325617 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485373 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 810990 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 325617 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485373 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 810990 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076371 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.076371 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.113655 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.113655 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.239699 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.239699 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113655 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.189689 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.159161 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113655 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.189689 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.159161 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107233.171806 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107233.171806 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84990.002162 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84990.002162 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85548.705401 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85548.705401 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84990.002162 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88221.874661 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 87295.263329 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84990.002162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88221.874661 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 87295.263329 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 367 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 97250 # number of writebacks -system.cpu.l2cache.writebacks::total 97250 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3084 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3084 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 31 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 31 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 118 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 118 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3202 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3233 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3202 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3233 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 115040 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 115040 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8266 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8266 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 36977 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 36977 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80602 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80602 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 36977 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 88868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 125845 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 36977 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 88868 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115040 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 240885 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10309951422 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10309951422 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 216500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 216500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 719316500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 719316500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2921107000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2921107000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6413507000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6413507000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2921107000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7132823500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10053930500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2921107000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7132823500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10309951422 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20363881922 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055619 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055619 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113560 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239348 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239348 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.155175 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297026 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89620.579120 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15464.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15464.285714 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87021.110573 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87021.110573 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78997.944668 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78997.944668 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79570.072703 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79570.072703 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79891.378283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84537.774963 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1620984 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80349 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18528 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18483 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 45 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 662386 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357113 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 550103 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28134 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 146171 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148617 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325631 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336756 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455635 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2431987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41646144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62094976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103741120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 271569 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6224896 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1082573 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091409 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.288334 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 983661 90.86% 90.86% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98867 9.13% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 45 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1082573 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1620458000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488577734 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728149334 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 347777 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205067 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214112 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97250 # Transaction distribution -system.membus.trans_dist::CleanEvict 28134 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 8266 # Transaction distribution -system.membus.trans_dist::ReadExResp 8266 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214113 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570155 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20456192 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222393 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222393 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222393 # Request fanout histogram -system.membus.reqLayer0.occupancy 835299244 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1174434906 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.1 # Layer utilization (%) +sim_seconds 0.037944 +sim_ticks 37944194500 +final_tick 37944194500 +sim_freq 1000000000000 +host_inst_rate 98071 +host_op_rate 125422 +host_tick_rate 52480065 +host_mem_usage 294796 +host_seconds 723.02 +sim_insts 70907652 +sim_ops 90682607 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500 +system.physmem.bytes_read::cpu.inst 2366464 +system.physmem.bytes_read::cpu.data 5687552 +system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176 +system.physmem.bytes_read::total 14232192 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+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79570.072703 +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79570.072703 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78997.944668 +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80263.126210 +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79891.378283 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78997.944668 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80263.126210 +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84537.774963 +system.cpu.toL2Bus.snoop_filter.tot_requests 1620984 +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80349 +system.cpu.toL2Bus.snoop_filter.tot_snoops 18528 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18483 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 45 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37944194500 +system.cpu.toL2Bus.trans_dist::ReadResp 662386 +system.cpu.toL2Bus.trans_dist::WritebackDirty 357113 +system.cpu.toL2Bus.trans_dist::WritebackClean 550103 +system.cpu.toL2Bus.trans_dist::CleanEvict 28134 +system.cpu.toL2Bus.trans_dist::HardPFReq 146171 +system.cpu.toL2Bus.trans_dist::UpgradeReq 14 +system.cpu.toL2Bus.trans_dist::UpgradeResp 14 +system.cpu.toL2Bus.trans_dist::ReadExReq 148617 +system.cpu.toL2Bus.trans_dist::ReadExResp 148617 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325631 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336756 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976352 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455635 +system.cpu.toL2Bus.pkt_count::total 2431987 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41646144 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62094976 +system.cpu.toL2Bus.pkt_size::total 103741120 +system.cpu.toL2Bus.snoops 271569 +system.cpu.toL2Bus.snoopTraffic 6224896 +system.cpu.toL2Bus.snoop_fanout::samples 1082573 +system.cpu.toL2Bus.snoop_fanout::mean 0.091409 +system.cpu.toL2Bus.snoop_fanout::stdev 0.288334 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 983661 90.86% 90.86% +system.cpu.toL2Bus.snoop_fanout::1 98867 9.13% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 45 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 1082573 +system.cpu.toL2Bus.reqLayer0.occupancy 1620458000 +system.cpu.toL2Bus.reqLayer0.utilization 4.3 +system.cpu.toL2Bus.respLayer0.occupancy 488577734 +system.cpu.toL2Bus.respLayer0.utilization 1.3 +system.cpu.toL2Bus.respLayer1.occupancy 728149334 +system.cpu.toL2Bus.respLayer1.utilization 1.9 +system.membus.snoop_filter.tot_requests 347777 +system.membus.snoop_filter.hit_single_requests 205067 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 37944194500 +system.membus.trans_dist::ReadResp 214112 +system.membus.trans_dist::WritebackDirty 97250 +system.membus.trans_dist::CleanEvict 28134 +system.membus.trans_dist::UpgradeReq 14 +system.membus.trans_dist::ReadExReq 8266 +system.membus.trans_dist::ReadExResp 8266 +system.membus.trans_dist::ReadSharedReq 214113 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155 +system.membus.pkt_count::total 570155 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192 +system.membus.pkt_size::total 20456192 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 222393 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 222393 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 222393 +system.membus.reqLayer0.occupancy 835299244 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 1174434906 +system.membus.respLayer1.utilization 3.1 ---------- End Simulation Statistics ---------- |