diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt')
-rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt | 398 |
1 files changed, 244 insertions, 154 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 2fff6cef5..0f7cee094 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.133117 # Nu sim_ticks 133117442000 # Number of ticks simulated final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1410680 # Simulator instruction rate (inst/s) -host_tick_rate 1881780580 # Simulator tick rate (ticks/s) -host_mem_usage 226592 # Number of bytes of host memory used -host_seconds 70.74 # Real time elapsed on the host -sim_insts 99791663 # Number of instructions simulated +host_inst_rate 1269489 # Simulator instruction rate (inst/s) +host_op_rate 1800168 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2401339947 # Simulator tick rate (ticks/s) +host_mem_usage 229088 # Number of bytes of host memory used +host_seconds 55.43 # Real time elapsed on the host +sim_insts 70373636 # Number of instructions simulated +sim_ops 99791663 # Number of ops (including micro ops) simulated system.physmem.bytes_read 8570688 # Number of bytes read from this memory system.physmem.bytes_inst_read 294208 # Number of instructions bytes read from this memory system.physmem.bytes_written 5660736 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 1946 # Nu system.cpu.numCycles 266234884 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 99791663 # Number of instructions executed +system.cpu.committedInsts 70373636 # Number of instructions committed +system.cpu.committedOps 99791663 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3287514 # number of times a function call or return occured @@ -89,26 +92,39 @@ system.cpu.icache.total_refs 78126170 # To system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 78126170 # number of ReadReq hits -system.cpu.icache.demand_hits 78126170 # number of demand (read+write) hits -system.cpu.icache.overall_hits 78126170 # number of overall hits -system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses -system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses -system.cpu.icache.overall_misses 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 457786000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 457786000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 457786000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 78145078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 78145078 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 24211.233340 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 24211.233340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1736.182852 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847746 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847746 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 78126170 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126170 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126170 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126170 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126170 # number of overall hits +system.cpu.icache.overall_hits::total 78126170 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses +system.cpu.icache.overall_misses::total 18908 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 457786000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 457786000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 457786000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 457786000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 457786000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 457786000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78145078 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145078 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145078 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145078 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145078 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 401062000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 401062000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 401062000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401062000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 401062000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 401062000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 401062000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401062000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 401062000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use @@ -144,36 +158,57 @@ system.cpu.dcache.total_refs 46862075 # To system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 27087368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 19742869 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 46830237 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 46830237 # number of overall hits -system.cpu.dcache.ReadReq_misses 52966 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 107032 # number of WriteReq misses -system.cpu.dcache.demand_misses 159998 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 1862630000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 5808782000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7671412000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7671412000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 27140334 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 46990235 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 46990235 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.003405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 47946.924337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 47946.924337 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4076.934010 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995345 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995345 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 27087368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27087368 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 46830237 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46830237 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46830237 # number of overall hits +system.cpu.dcache.overall_hits::total 46830237 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses +system.cpu.dcache.overall_misses::total 159998 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1862630000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1862630000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5808782000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5808782000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7671412000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7671412000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7671412000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7671412000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27140334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27140334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46990235 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46990235 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46990235 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46990235 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 122808 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 52966 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 107032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 159998 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1703732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 5487686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7191418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7191418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001952 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.003405 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 122808 # number of writebacks +system.cpu.dcache.writebacks::total 122808 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1703732000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1703732000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5487686000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5487686000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7191418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7191418000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7191418000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7191418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 113660 # number of replacements system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use @@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs 61800 # To system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16025.699940 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.066099 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.489066 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 40584 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 122808 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 4405 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 44989 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 44989 # number of overall hits -system.cpu.l2cache.ReadReq_misses 31290 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 102627 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 133917 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 133917 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 1627080000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 5336604000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 6963684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 6963684000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 122808 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 178906 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.435345 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.958844 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.748533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.748533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 16025.699940 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 701.722418 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1464.198671 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.489066 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021415 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.044684 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.555164 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14311 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 26273 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40584 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 122808 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 122808 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4405 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4405 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14311 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 30678 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 44989 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14311 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 30678 # number of overall hits +system.cpu.l2cache.overall_hits::total 44989 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4597 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 26693 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 31290 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102627 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102627 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4597 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 129320 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 133917 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4597 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 129320 # number of overall misses +system.cpu.l2cache.overall_misses::total 133917 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239044000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1388036000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1627080000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5336604000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5336604000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 239044000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6724640000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6963684000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 239044000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6724640000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6963684000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 122808 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 122808 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243125 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.503965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.958844 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243125 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.808260 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243125 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.808260 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 88449 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 31290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 102627 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 133917 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 133917 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1251600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4105080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 5356680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 5356680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.435345 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.748533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.748533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 88449 # number of writebacks +system.cpu.l2cache.writebacks::total 88449 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4597 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 26693 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 31290 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102627 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102627 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 129320 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 133917 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4597 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 129320 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 133917 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183880000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1067720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1251600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4105080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4105080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183880000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5172800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5356680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183880000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5172800000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5356680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.503965 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.958844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |