diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt | 470 |
1 files changed, 235 insertions, 235 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index f1e03b8eb..b1eb24a6a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133117 # Number of seconds simulated -sim_ticks 133117442000 # Number of ticks simulated -final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132925 # Number of seconds simulated +sim_ticks 132924820000 # Number of ticks simulated +final_tick 132924820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 828989 # Simulator instruction rate (inst/s) -host_op_rate 1175527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1568098699 # Simulator tick rate (ticks/s) -host_mem_usage 237868 # Number of bytes of host memory used -host_seconds 84.89 # Real time elapsed on the host -sim_insts 70373636 # Number of instructions simulated -sim_ops 99791663 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 294208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8276480 # Number of bytes read from this memory -system.physmem.bytes_read::total 8570688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5660736 # Number of bytes written to this memory -system.physmem.bytes_written::total 5660736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 129320 # Number of read requests responded to by this memory -system.physmem.num_reads::total 133917 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88449 # Number of write requests responded to by this memory -system.physmem.num_writes::total 88449 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2210139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62174272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64384410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2210139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2210139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42524375 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42524375 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42524375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2210139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62174272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106908785 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 1112405 # Simulator instruction rate (inst/s) +host_op_rate 1577419 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2101158995 # Simulator tick rate (ticks/s) +host_mem_usage 240528 # Number of bytes of host memory used +host_seconds 63.26 # Real time elapsed on the host +sim_insts 70373628 # Number of instructions simulated +sim_ops 99791654 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8003456 # Number of bytes read from this memory +system.physmem.bytes_read::total 8277184 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 273728 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 273728 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5403392 # Number of bytes written to this memory +system.physmem.bytes_written::total 5403392 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4277 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2059269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60210396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 62269665 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2059269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2059269 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40649985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40649985 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40649985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2059269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60210396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102919650 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,73 +77,73 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 266234884 # number of cpu cycles simulated +system.cpu.numCycles 265849640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373636 # Number of instructions committed -system.cpu.committedOps 99791663 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses +system.cpu.committedInsts 70373628 # Number of instructions committed +system.cpu.committedOps 99791654 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3287514 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10711743 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472788 # number of integer instructions +system.cpu.num_func_calls 3311620 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10711742 # number of instructions that are conditional controls +system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 533542913 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252298 # number of times the integer registers were written +system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read +system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862848 # number of memory refs -system.cpu.num_load_insts 27307109 # Number of load instructions +system.cpu.num_mem_refs 47862847 # number of memory refs +system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 266234884 # Number of busy cycles +system.cpu.num_busy_cycles 265849640 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.182852 # Cycle average of tags in use -system.cpu.icache.total_refs 78126170 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1736.286948 # Cycle average of tags in use +system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.182852 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847746 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847746 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 78126170 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126170 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126170 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126170 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126170 # number of overall hits -system.cpu.icache.overall_hits::total 78126170 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 1736.286948 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847796 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847796 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits +system.cpu.icache.overall_hits::total 78126161 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 457786000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 457786000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 457786000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 457786000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 457786000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 457786000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145078 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145078 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145078 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145078 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 444346000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 444346000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 444346000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 444346000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 444346000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 444346000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24211.233340 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24211.233340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24211.233340 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23500.423101 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23500.423101 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23500.423101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23500.423101 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23500.423101 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,46 +158,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 401062000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 401062000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 401062000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 401062000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401062000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 401062000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387622000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 387622000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387622000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 387622000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387622000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 387622000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21211.233340 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20500.423101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20500.423101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20500.423101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20500.423101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use -system.cpu.dcache.total_refs 46862075 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4076.906689 # Cycle average of tags in use +system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.934010 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995345 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995345 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 27087368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27087368 # number of ReadReq hits +system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1079631000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4076.906689 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995339 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995339 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46830237 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46830237 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46830237 # number of overall hits -system.cpu.dcache.overall_hits::total 46830237 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits +system.cpu.dcache.overall_hits::total 46830236 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses @@ -206,26 +206,26 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1862630000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1862630000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5808782000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5808782000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7671412000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7671412000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7671412000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7671412000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27140334 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27140334 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1695470000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1695470000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5796770000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5796770000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7492240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7492240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7492240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7492240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46990235 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46990235 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46990235 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46990235 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35166.521920 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54271.451529 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47946.924337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47946.924337 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32010.535060 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32010.535060 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54159.223410 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54159.223410 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46827.085339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46827.085339 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46827.085339 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 122808 # number of writebacks -system.cpu.dcache.writebacks::total 122808 # number of writebacks +system.cpu.dcache.writebacks::writebacks 127057 # number of writebacks +system.cpu.dcache.writebacks::total 127057 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1703732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1703732000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5487686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5487686000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7191418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7191418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7191418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7191418000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536572000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012246000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7012246000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012246000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7012246000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32166.521920 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51271.451529 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29010.535060 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29010.535060 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.223410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.223410 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.085339 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.085339 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 113660 # number of replacements -system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use -system.cpu.l2cache.total_refs 61800 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 96735 # number of replacements +system.cpu.l2cache.tagsinuse 28872.647154 # Cycle average of tags in use +system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 16025.699940 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 701.722418 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1464.198671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.489066 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021415 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.044684 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.555164 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14311 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 26273 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40584 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 122808 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 122808 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4405 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4405 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 30678 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 44989 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14311 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 30678 # number of overall hits -system.cpu.l2cache.overall_hits::total 44989 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4597 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 26693 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 31290 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102627 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102627 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4597 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 129320 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 133917 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4597 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 129320 # number of overall misses -system.cpu.l2cache.overall_misses::total 133917 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239044000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1388036000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1627080000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5336604000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5336604000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239044000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6724640000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6963684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 239044000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6724640000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6963684000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 26446.371833 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 949.934371 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1476.340950 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.807079 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.028990 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.045054 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.881123 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 127057 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 127057 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4691 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4691 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14631 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 34944 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 49575 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14631 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 34944 # number of overall hits +system.cpu.l2cache.overall_hits::total 49575 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4277 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 22713 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26990 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102341 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102341 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4277 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 125054 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 129331 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4277 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 125054 # number of overall misses +system.cpu.l2cache.overall_misses::total 129331 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222404000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181076000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1403480000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321732000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5321732000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 222404000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6502808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6725212000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 222404000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6502808000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6725212000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 122808 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 122808 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 127057 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 127057 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_accesses::total 178906 # n system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243125 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.503965 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.435345 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.958844 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.958844 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243125 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.808260 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.748533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243125 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.808260 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.748533 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.226201 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.428822 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.375518 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956172 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.956172 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.226201 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.781597 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.722899 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency @@ -376,41 +376,41 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88449 # number of writebacks -system.cpu.l2cache.writebacks::total 88449 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4597 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 26693 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 31290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102627 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102627 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4597 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 129320 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 133917 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4597 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 129320 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 133917 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1067720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1251600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4105080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4105080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5172800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5356680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5172800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5356680000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.503965 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.435345 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.958844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.958844 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.748533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.748533 # mshr miss rate for overall accesses +system.cpu.l2cache.writebacks::writebacks 84428 # number of writebacks +system.cpu.l2cache.writebacks::total 84428 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4277 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 22713 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26990 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102341 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102341 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4277 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125054 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 129331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4277 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125054 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 129331 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079600000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093640000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093640000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002160000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5173240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002160000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5173240000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956172 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956172 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency |