diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt | 87 |
1 files changed, 72 insertions, 15 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index f30f52adf..f1e03b8eb 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,23 +4,36 @@ sim_seconds 0.133117 # Nu sim_ticks 133117442000 # Number of ticks simulated final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 457869 # Simulator instruction rate (inst/s) -host_op_rate 649270 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 866095863 # Simulator tick rate (ticks/s) -host_mem_usage 237424 # Number of bytes of host memory used -host_seconds 153.70 # Real time elapsed on the host +host_inst_rate 828989 # Simulator instruction rate (inst/s) +host_op_rate 1175527 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1568098699 # Simulator tick rate (ticks/s) +host_mem_usage 237868 # Number of bytes of host memory used +host_seconds 84.89 # Real time elapsed on the host sim_insts 70373636 # Number of instructions simulated sim_ops 99791663 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 8570688 # Number of bytes read from this memory -system.physmem.bytes_inst_read 294208 # Number of instructions bytes read from this memory -system.physmem.bytes_written 5660736 # Number of bytes written to this memory -system.physmem.num_reads 133917 # Number of read requests responded to by this memory -system.physmem.num_writes 88449 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 64384410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2210139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 42524375 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 106908785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 294208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8276480 # Number of bytes read from this memory +system.physmem.bytes_read::total 8570688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 294208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 294208 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5660736 # Number of bytes written to this memory +system.physmem.bytes_written::total 5660736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 129320 # Number of read requests responded to by this memory +system.physmem.num_reads::total 133917 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 88449 # Number of write requests responded to by this memory +system.physmem.num_writes::total 88449 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2210139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62174272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64384410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2210139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2210139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42524375 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42524375 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42524375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2210139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62174272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106908785 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -120,11 +133,17 @@ system.cpu.icache.demand_accesses::total 78145078 # nu system.cpu.icache.overall_accesses::cpu.inst 78145078 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24211.233340 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24211.233340 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24211.233340 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,11 +165,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 401062000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 401062000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 401062000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21211.233340 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21211.233340 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use @@ -202,13 +227,21 @@ system.cpu.dcache.demand_accesses::total 46990235 # nu system.cpu.dcache.overall_accesses::cpu.data 46990235 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 46990235 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35166.521920 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54271.451529 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47946.924337 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47946.924337 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -236,13 +269,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7191418000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7191418000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7191418000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32166.521920 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51271.451529 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44946.924337 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 113660 # number of replacements system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use @@ -307,18 +348,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 159998 system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.243125 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.503965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.435345 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.958844 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.958844 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.243125 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.808260 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.748533 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.243125 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.808260 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.748533 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,18 +402,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5172800000 system.cpu.l2cache.overall_mshr_miss_latency::total 5356680000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.503965 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.435345 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.958844 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.958844 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.748533 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243125 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.808260 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.748533 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |