diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux')
4 files changed, 1502 insertions, 1510 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index b9814d1e2..20f3ef2c3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057816 # Number of seconds simulated -sim_ticks 57815555000 # Number of ticks simulated -final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058730 # Number of seconds simulated +sim_ticks 58730125500 # Number of ticks simulated +final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131971 # Simulator instruction rate (inst/s) -host_op_rate 168772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107593052 # Simulator tick rate (ticks/s) -host_mem_usage 309228 # Number of bytes of host memory used -host_seconds 537.35 # Real time elapsed on the host +host_inst_rate 197162 # Simulator instruction rate (inst/s) +host_op_rate 252141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163284235 # Simulator tick rate (ticks/s) +host_mem_usage 321164 # Number of bytes of host memory used +host_seconds 359.68 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128872 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128871 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8159 # Per bank write bursts -system.physmem.perBankRdBursts::1 8375 # Per bank write bursts -system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::1 8376 # Per bank write bursts +system.physmem.perBankRdBursts::2 8228 # Per bank write bursts system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8320 # Per bank write bursts +system.physmem.perBankRdBursts::4 8319 # Per bank write bursts system.physmem.perBankRdBursts::5 8450 # Per bank write bursts system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7970 # Per bank write bursts +system.physmem.perBankRdBursts::7 7969 # Per bank write bursts system.physmem.perBankRdBursts::8 8071 # Per bank write bursts system.physmem.perBankRdBursts::9 7640 # Per bank write bursts -system.physmem.perBankRdBursts::10 7820 # Per bank write bursts -system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::10 7818 # Per bank write bursts +system.physmem.perBankRdBursts::11 7832 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5183 # Per bank write bursts +system.physmem.perBankRdBursts::15 8007 # Per bank write bursts +system.physmem.perBankWrBursts::0 5180 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5194 # Per bank write bursts -system.physmem.perBankWrBursts::7 5048 # Per bank write bursts +system.physmem.perBankWrBursts::6 5197 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5086 # Per bank write bursts -system.physmem.perBankWrBursts::10 5252 # Per bank write bursts +system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5225 # Per bank write bursts +system.physmem.perBankWrBursts::15 5227 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57815523000 # Total gap between requests +system.physmem.totGap 58730091000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128872 # Read request sizes (log2) +system.physmem.readPktSize::6 128871 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 83951 # Write request sizes (log2) system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,100 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 1505377000 # Total ticks spent queuing -system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads +system.physmem.totQLat 1533027250 # Total ticks spent queuing +system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.84 # Data bus utilization in percentage -system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.81 # Data bus utilization in percentage +system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing -system.physmem.readRowHits 112203 # Number of row buffer hits during reads -system.physmem.writeRowHits 62134 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes -system.physmem.avgGap 271660.13 # Average gap between requests -system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.837327 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing +system.physmem.readRowHits 112070 # Number of row buffer hits during reads +system.physmem.writeRowHits 62147 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes +system.physmem.avgGap 275958.74 # Average gap between requests +system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.329716 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.292941 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.358131 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14822198 # Number of BP lookups -system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits +system.cpu.branchPred.lookups 14827059 # Number of BP lookups +system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -406,89 +404,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115631110 # number of cpu cycles simulated +system.cpu.numCycles 117460251 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.630556 # CPI: cycles per instruction -system.cpu.ipc 0.613288 # IPC: instructions per cycle -system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156428 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy +system.cpu.cpi 1.656350 # CPI: cycles per instruction +system.cpu.ipc 0.603737 # IPC: instructions per cycle +system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked +system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156434 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits -system.cpu.dcache.overall_hits::total 42633064 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses -system.cpu.dcache.overall_misses::total 262131 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits +system.cpu.dcache.overall_hits::total 42634623 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses +system.cpu.dcache.overall_misses::total 262226 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,32 +495,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks -system.cpu.dcache.writebacks::total 128441 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99030 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 101607 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53488 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9597585313 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks +system.cpu.dcache.writebacks::total 128445 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -531,68 +529,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42682 # number of replacements -system.cpu.icache.tags.tagsinuse 1858.929385 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25083355 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44724 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 560.847755 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42774 # number of replacements +system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1858.929385 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.907680 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.907680 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 803 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50300884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50300884 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25083355 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25083355 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25083355 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25083355 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25083355 # number of overall hits -system.cpu.icache.overall_hits::total 25083355 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44725 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44725 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44725 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44725 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44725 # number of overall misses -system.cpu.icache.overall_misses::total 44725 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 895927489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 895927489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 895927489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 895927489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 895927489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 895927489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25128080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25128080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25128080 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25128080 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25128080 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25128080 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20031.917026 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20031.917026 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20031.917026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20031.917026 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits +system.cpu.icache.overall_hits::total 25093452 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses +system.cpu.icache.overall_misses::total 44817 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 937886990 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25138269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25138269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25138269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25138269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25138269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25138269 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001783 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001783 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001783 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001783 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001783 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001783 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.036392 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20927.036392 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,123 +599,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44725 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44725 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44725 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44725 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44725 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44725 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804564511 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 804564511 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804564511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 804564511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804564511 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 804564511 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17989.145020 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44817 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44817 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44817 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44817 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44817 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44817 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 868759010 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 868759010 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 868759010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 868759010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 868759010 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 868759010 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001783 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001783 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19384.586429 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19384.586429 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95733 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29936.958460 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99697 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126852 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 29885.598621 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99802 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126851 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.786766 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1563.058609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1666.382853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047701 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19493 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949677 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2903408 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2903408 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 39644 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31904 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71548 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128441 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128441 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4755 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4755 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 39644 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 76303 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 39644 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits -system.cpu.l2cache.overall_hits::total 76303 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5081 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21584 # number of ReadReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 26636.535052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1559.339588 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1689.723980 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.812883 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047587 # 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Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107036 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89449 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449489 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 538938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2862336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18493760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21356096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98312 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449505 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 539138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2868224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21362624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333690 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333792 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.membus.trans_dist::ReadReq 26591 # Transaction distribution system.membus.trans_dist::ReadResp 26591 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution -system.membus.trans_dist::ReadExReq 102281 # Transaction distribution -system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212823 # Request fanout histogram +system.membus.snoop_fanout::samples 212822 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212823 # Request fanout histogram -system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.snoop_fanout::total 212822 # Request fanout histogram +system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6394c9beb..c55c80533 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033020 # Number of seconds simulated -sim_ticks 33019504000 # Number of ticks simulated -final_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033359 # Number of seconds simulated +sim_ticks 33359312000 # Number of ticks simulated +final_tick 33359312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123822 # Simulator instruction rate (inst/s) -host_op_rate 158353 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57659893 # Simulator tick rate (ticks/s) -host_mem_usage 322352 # Number of bytes of host memory used -host_seconds 572.66 # Real time elapsed on the host +host_inst_rate 125450 # Simulator instruction rate (inst/s) +host_op_rate 160435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59019201 # Simulator tick rate (ticks/s) +host_mem_usage 322444 # Number of bytes of host memory used +host_seconds 565.23 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory -system.physmem.bytes_read::total 9307712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory -system.physmem.bytes_written::total 6262016 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145433 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97844 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145433 # Number of read requests accepted -system.physmem.writeReqs 97844 # Number of write requests accepted -system.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 593600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2515776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6204544 # Number of bytes read from this memory +system.physmem.bytes_read::total 9313920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 593600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 593600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6264768 # Number of bytes written to this memory +system.physmem.bytes_written::total 6264768 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39309 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145530 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97887 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97887 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17794132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75414505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 185991366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 279200003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17794132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17794132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187796679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187796679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187796679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17794132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75414505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 185991366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 466996681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145530 # Number of read requests accepted +system.physmem.writeReqs 97887 # Number of write requests accepted +system.physmem.readBursts 145530 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97887 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9306560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 6263296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9313920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6264768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9146 # Per bank write bursts -system.physmem.perBankRdBursts::1 9381 # Per bank write bursts -system.physmem.perBankRdBursts::2 9349 # Per bank write bursts -system.physmem.perBankRdBursts::3 9489 # Per bank write bursts -system.physmem.perBankRdBursts::4 9691 # Per bank write bursts -system.physmem.perBankRdBursts::5 9742 # Per bank write bursts -system.physmem.perBankRdBursts::6 9065 # Per bank write bursts -system.physmem.perBankRdBursts::7 9033 # Per bank write bursts -system.physmem.perBankRdBursts::8 9160 # Per bank write bursts -system.physmem.perBankRdBursts::9 8585 # Per bank write bursts -system.physmem.perBankRdBursts::10 8818 # Per bank write bursts -system.physmem.perBankRdBursts::11 8754 # Per bank write bursts -system.physmem.perBankRdBursts::12 8666 # Per bank write bursts -system.physmem.perBankRdBursts::13 8713 # Per bank write bursts -system.physmem.perBankRdBursts::14 8726 # Per bank write bursts -system.physmem.perBankRdBursts::15 9002 # Per bank write bursts -system.physmem.perBankWrBursts::0 5993 # Per bank write bursts -system.physmem.perBankWrBursts::1 6194 # Per bank write bursts -system.physmem.perBankWrBursts::2 6159 # Per bank write bursts -system.physmem.perBankWrBursts::3 6198 # Per bank write bursts -system.physmem.perBankWrBursts::4 6133 # Per bank write bursts -system.physmem.perBankWrBursts::5 6325 # Per bank write bursts -system.physmem.perBankWrBursts::6 6074 # Per bank write bursts -system.physmem.perBankWrBursts::7 6046 # Per bank write bursts -system.physmem.perBankWrBursts::8 6012 # Per bank write bursts -system.physmem.perBankWrBursts::9 6139 # Per bank write bursts -system.physmem.perBankWrBursts::10 6243 # Per bank write bursts -system.physmem.perBankWrBursts::11 5934 # Per bank write bursts -system.physmem.perBankWrBursts::12 6049 # Per bank write bursts -system.physmem.perBankWrBursts::13 6103 # Per bank write bursts -system.physmem.perBankWrBursts::14 6164 # Per bank write bursts -system.physmem.perBankWrBursts::15 6052 # Per bank write bursts +system.physmem.perBankRdBursts::0 9160 # Per bank write bursts +system.physmem.perBankRdBursts::1 9419 # Per bank write bursts +system.physmem.perBankRdBursts::2 9305 # Per bank write bursts +system.physmem.perBankRdBursts::3 9483 # Per bank write bursts +system.physmem.perBankRdBursts::4 9789 # Per bank write bursts +system.physmem.perBankRdBursts::5 9711 # Per bank write bursts +system.physmem.perBankRdBursts::6 9074 # Per bank write bursts +system.physmem.perBankRdBursts::7 9074 # Per bank write bursts +system.physmem.perBankRdBursts::8 9205 # Per bank write bursts +system.physmem.perBankRdBursts::9 8628 # Per bank write bursts +system.physmem.perBankRdBursts::10 8849 # Per bank write bursts +system.physmem.perBankRdBursts::11 8741 # Per bank write bursts +system.physmem.perBankRdBursts::12 8642 # Per bank write bursts +system.physmem.perBankRdBursts::13 8695 # Per bank write bursts +system.physmem.perBankRdBursts::14 8691 # Per bank write bursts +system.physmem.perBankRdBursts::15 8949 # Per bank write bursts +system.physmem.perBankWrBursts::0 5976 # Per bank write bursts +system.physmem.perBankWrBursts::1 6255 # Per bank write bursts +system.physmem.perBankWrBursts::2 6149 # Per bank write bursts +system.physmem.perBankWrBursts::3 6169 # Per bank write bursts +system.physmem.perBankWrBursts::4 6151 # Per bank write bursts +system.physmem.perBankWrBursts::5 6334 # Per bank write bursts +system.physmem.perBankWrBursts::6 6086 # Per bank write bursts +system.physmem.perBankWrBursts::7 6007 # Per bank write bursts +system.physmem.perBankWrBursts::8 5979 # Per bank write bursts +system.physmem.perBankWrBursts::9 6153 # Per bank write bursts +system.physmem.perBankWrBursts::10 6241 # Per bank write bursts +system.physmem.perBankWrBursts::11 5938 # Per bank write bursts +system.physmem.perBankWrBursts::12 6061 # Per bank write bursts +system.physmem.perBankWrBursts::13 6105 # Per bank write bursts +system.physmem.perBankWrBursts::14 6219 # Per bank write bursts +system.physmem.perBankWrBursts::15 6041 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33019298500 # Total gap between requests +system.physmem.totGap 33359040500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145433 # Read request sizes (log2) +system.physmem.readPktSize::6 145530 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97844 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97887 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 42093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -148,33 +148,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -197,102 +197,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.072858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.491943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 238.713124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52339 58.86% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22656 25.48% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4441 4.99% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1741 1.96% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1037 1.17% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 849 0.95% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 689 0.77% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 765 0.86% 95.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4410 4.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88927 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.598207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.088924 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 187.219466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads -system.physmem.totQLat 7598607995 # Total ticks spent queuing -system.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 726600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.556251 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512708 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.281856 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4715 79.77% 79.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 33 0.56% 80.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 741 12.54% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 193 3.27% 96.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 104 1.76% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 53 0.90% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 34 0.58% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.29% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.19% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads +system.physmem.totQLat 7478329771 # Total ticks spent queuing +system.physmem.totMemAccLat 10204861021 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 727075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51427.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70177.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 278.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 187.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 279.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 187.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.68 # Data bus utilization in percentage -system.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.physmem.busUtil 3.65 # Data bus utilization in percentage +system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 118226 # Number of row buffer hits during reads -system.physmem.writeRowHits 36119 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes -system.physmem.avgGap 135727.17 # Average gap between requests -system.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.509165 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states -system.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing +system.physmem.readRowHits 118188 # Number of row buffer hits during reads +system.physmem.writeRowHits 36158 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.94 # Row buffer hit rate for writes +system.physmem.avgGap 137044.83 # Average gap between requests +system.physmem.pageHitRate 63.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 343556640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 187456500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 584859600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 318226320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11869125390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9602419500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25084314990 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.005565 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15876395968 # Time in different power states +system.physmem_0.memoryStateTime::REF 1113840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16366332782 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ) -system.physmem_1.averagePower 748.955517 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states -system.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_1.actEnergy 328413960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179194125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 548948400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315725040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11416289175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9999644250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24966885990 # Total energy per rank (pJ) +system.physmem_1.averagePower 748.485148 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16542747198 # Time in different power states +system.physmem_1.memoryStateTime::REF 1113840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15699981552 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17204705 # Number of BP lookups -system.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7673903 # Number of BTB hits +system.cpu.branchPred.lookups 17207670 # Number of BP lookups +system.cpu.branchPred.condPredicted 11518844 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648137 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9345275 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7675164 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.128819 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1873048 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101561 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,234 +413,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66039009 # number of cpu cycles simulated +system.cpu.numCycles 66718625 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 4981358 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88194612 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17207670 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9548212 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60206161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322349 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5969 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13195 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22764676 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68972 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65867882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.694526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296864 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20086614 30.50% 30.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8263984 12.55% 43.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9201027 13.97% 57.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28316257 42.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31530881 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32193949 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65867882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257914 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.321889 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8560400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19609685 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31575881 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5629864 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492052 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179520 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171002 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101414286 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3048471 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492052 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13316863 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5341740 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 787564 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32235527 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13694136 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99203918 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 983561 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3871797 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 66642 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4317748 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5384160 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103925780 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457714134 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115415425 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18665 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10296554 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12695794 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24322207 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21994092 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1403605 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2365005 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98166864 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94891849 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694587 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7414208 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20250811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65867882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.440639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150059 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17597825 26.72% 26.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17436284 26.47% 53.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17101122 25.96% 79.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11678255 17.73% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2053424 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 972 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65867882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6717330 22.42% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11201861 37.39% 59.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12041280 40.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49497025 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89873 0.09% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24063293 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21241620 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94858951 # Type of FU issued -system.cpu.iq.rate 1.436408 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94891849 # Type of FU issued +system.cpu.iq.rate 1.422269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29960509 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315733 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286306469 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105626883 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93465742 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124852240 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1363033 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1455945 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2039 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1438354 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 142055 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 176720 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492052 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 623106 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 467581 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98211247 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24322207 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21994092 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 463043 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303168 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221686 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524854 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93974313 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23756309 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 917536 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9863 # number of nop insts executed -system.cpu.iew.exec_refs 44710370 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251746 # Number of branches executed -system.cpu.iew.exec_stores 20982459 # Number of stores executed -system.cpu.iew.exec_rate 1.422528 # Inst execution rate -system.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93463063 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44927637 # num instructions producing a value -system.cpu.iew.wb_consumers 76497349 # num instructions consuming a value +system.cpu.iew.exec_nop 9861 # number of nop insts executed +system.cpu.iew.exec_refs 44740784 # number of memory reference insts executed +system.cpu.iew.exec_branches 14252664 # Number of branches executed +system.cpu.iew.exec_stores 20984475 # Number of stores executed +system.cpu.iew.exec_rate 1.408517 # Inst execution rate +system.cpu.iew.wb_sent 93587501 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93465799 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44986533 # num instructions producing a value +system.cpu.iew.wb_consumers 76576760 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.415271 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back +system.cpu.iew.wb_rate 1.400895 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587470 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6538748 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479015 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64808930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.399315 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.164562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 706597 1.10% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 586126 0.91% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3803876 5.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31222194 48.18% 48.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16795938 25.92% 74.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4338232 6.69% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4159188 6.42% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1936724 2.99% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1268170 1.96% 92.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 738929 1.14% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579590 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3769965 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64238392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64808930 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,381 +686,381 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction -system.cpu.commit.bw_lim_events 3803876 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3769965 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 157616533 # The number of ROB reads -system.cpu.rob.rob_writes 195472136 # The number of ROB writes -system.cpu.timesIdled 23660 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 744970 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 158240550 # The number of ROB reads +system.cpu.rob.rob_writes 195514428 # The number of ROB writes +system.cpu.timesIdled 23835 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 850743 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.931339 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.931339 # CPI: Total CPI of All Threads -system.cpu.ipc 1.073723 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.073723 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102238235 # number of integer regfile reads -system.cpu.int_regfile_writes 56792997 # number of integer regfile writes +system.cpu.cpi 0.940923 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.940923 # CPI: Total CPI of All Threads +system.cpu.ipc 1.062786 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.062786 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102271067 # number of integer regfile reads +system.cpu.int_regfile_writes 56793819 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 345997909 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804494 # number of cc regfile writes -system.cpu.misc_regfile_reads 44208348 # number of misc regfile reads +system.cpu.cc_regfile_reads 346093039 # number of cc regfile reads +system.cpu.cc_regfile_writes 38805147 # number of cc regfile writes +system.cpu.misc_regfile_reads 44210055 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485280 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.769602 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40441610 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485792 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.248818 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 148406000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.769602 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997597 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485079 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.744077 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40428139 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485591 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.255536 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 152734000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.744077 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997547 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84635072 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84635072 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21513403 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21513403 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834640 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834640 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 62245 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 62245 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 84616103 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84616103 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21501727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21501727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18833421 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18833421 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 61667 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 61667 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40348043 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40348043 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40410288 # number of overall hits -system.cpu.dcache.overall_hits::total 40410288 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 550665 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 550665 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1015261 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1015261 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 66581 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 66581 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40335148 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40335148 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40396815 # number of overall hits +system.cpu.dcache.overall_hits::total 40396815 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 552941 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 552941 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1016480 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1016480 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 67175 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 67175 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1565926 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1565926 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1632507 # number of overall misses -system.cpu.dcache.overall_misses::total 1632507 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8659099753 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8659099753 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14372727937 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14372727937 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4891750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4891750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23031827690 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23031827690 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23031827690 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23031827690 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22064068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1569421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1569421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636596 # number of overall misses +system.cpu.dcache.overall_misses::total 1636596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9116754245 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9116754245 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14723087903 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14723087903 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5168250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5168250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23839842148 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23839842148 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23839842148 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23839842148 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054668 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054668 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128826 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128842 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128842 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41913969 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41913969 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42042795 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42042795 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024958 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024958 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051147 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051147 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516829 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41904569 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904569 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033411 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033411 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025071 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025071 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051208 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051208 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.521375 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.521375 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037360 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037360 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038830 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038830 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15724.805014 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15724.805014 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14156.682801 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14156.682801 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8942.870201 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8942.870201 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14708.120109 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14708.120109 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14108.256620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14108.256620 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2883834 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 127457 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.625937 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.037452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038936 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038936 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16487.752301 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16487.752301 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14484.385234 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14484.385234 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9448.354662 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9448.354662 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15190.214830 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15190.214830 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14566.723949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14566.723949 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3023244 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 128456 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.535249 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 264417 # number of writebacks -system.cpu.dcache.writebacks::total 264417 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 250985 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 250985 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866735 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866735 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 262833 # number of writebacks +system.cpu.dcache.writebacks::total 262833 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 253459 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 253459 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 867955 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 867955 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1117720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1117720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1117720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1117720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148526 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148526 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 448206 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 448206 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485803 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485803 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2833367604 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2833367604 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2154211948 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2154211948 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1934780357 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1934780357 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4987579552 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4987579552 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6922359909 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6922359909 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013582 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013582 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1121414 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1121414 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1121414 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1121414 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299482 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299482 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148525 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148525 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37595 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37595 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 448007 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 448007 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485602 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485602 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3044598863 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3044598863 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2289083292 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2289083292 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2038189218 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2038189218 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5333682155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5333682155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7371871373 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7371871373 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013579 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291843 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291843 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010693 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010693 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9454.643633 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9454.643633 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14503.938354 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14503.938354 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51461.030322 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51461.030322 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11127.873237 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11127.873237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14249.314864 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14249.314864 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291791 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291791 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010691 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10166.216544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10166.216544 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15412.107672 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15412.107672 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54214.369411 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54214.369411 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11905.354503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11905.354503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15180.891703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15180.891703 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322868 # number of replacements -system.cpu.icache.tags.tagsinuse 510.284584 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22426703 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323380 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.350928 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1086653000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.284584 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996650 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996650 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 322801 # number of replacements +system.cpu.icache.tags.tagsinuse 510.305225 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22431720 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323313 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.380817 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1103729250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.305225 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996690 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996690 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 351 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 352 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45841045 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45841045 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22426703 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22426703 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22426703 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22426703 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22426703 # number of overall hits -system.cpu.icache.overall_hits::total 22426703 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 332124 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 332124 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 332124 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 332124 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 332124 # number of overall misses -system.cpu.icache.overall_misses::total 332124 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3299467842 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3299467842 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3299467842 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3299467842 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3299467842 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3299467842 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22758827 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22758827 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22758827 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22758827 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22758827 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22758827 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014593 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014593 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014593 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014593 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014593 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014593 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9934.445695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 9934.445695 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9934.445695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9934.445695 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 226617 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 46 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199496 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69610.297251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79439.189214 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77177.866275 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96760.706913 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13834.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13834.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74344.471100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74344.471100 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76695.563910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90719.765072 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 660352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 262833 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 151427 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 169293 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148563 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1880674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20692032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47899136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68591168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 151438 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1223186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.123797 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.329350 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1071759 87.62% 87.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 151427 12.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1223186 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 798712500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 486658187 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 734620345 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 137181 # Transaction distribution -system.membus.trans_dist::ReadResp 137181 # Transaction distribution -system.membus.trans_dist::Writeback 97844 # Transaction distribution +system.membus.trans_dist::ReadReq 137260 # Transaction distribution +system.membus.trans_dist::ReadResp 137260 # Transaction distribution +system.membus.trans_dist::Writeback 97887 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8252 # Transaction distribution -system.membus.trans_dist::ReadExResp 8252 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8270 # Transaction distribution +system.membus.trans_dist::ReadExResp 8270 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 388959 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15578688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15578688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 243283 # Request fanout histogram +system.membus.snoop_fanout::samples 243423 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 243423 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 243283 # Request fanout histogram -system.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.membus.snoop_fanout::total 243423 # Request fanout histogram +system.membus.reqLayer0.occupancy 692237323 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 758965490 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 23c0d1c87..93e5e3e06 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011000 # Number of ticks simulated final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1376675 # Simulator instruction rate (inst/s) -host_op_rate 1760576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 950486092 # Simulator tick rate (ticks/s) -host_mem_usage 308184 # Number of bytes of host memory used -host_seconds 51.51 # Real time elapsed on the host +host_inst_rate 1566427 # Simulator instruction rate (inst/s) +host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1081494789 # Simulator tick rate (ticks/s) +host_mem_usage 308080 # Number of bytes of host memory used +host_seconds 45.27 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 120930618 # Request fanout histogram -system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram +system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 120930618 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 938385651..6d597c67f 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.127294 # Number of seconds simulated -sim_ticks 127293983000 # Number of ticks simulated -final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.127293 # Number of seconds simulated +sim_ticks 127293405500 # Number of ticks simulated +final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 894668 # Simulator instruction rate (inst/s) -host_op_rate 1142240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618302823 # Simulator tick rate (ticks/s) -host_mem_usage 317432 # Number of bytes of host memory used -host_seconds 78.66 # Real time elapsed on the host +host_inst_rate 802256 # Simulator instruction rate (inst/s) +host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1451138855 # Simulator tick rate (ticks/s) +host_mem_usage 317568 # Number of bytes of host memory used +host_seconds 87.72 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123820 # Nu system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2007071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62253375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64260445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2007071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2007071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42187194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42187194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42187194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254587966 # number of cpu cycles simulated +system.cpu.numCycles 254586811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254587965.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741485 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -230,8 +230,8 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits @@ -240,28 +240,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits -system.cpu.dcache.overall_hits::total 42576328 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits +system.cpu.dcache.overall_hits::total 42576331 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses -system.cpu.dcache.overall_misses::total 177384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses +system.cpu.dcache.overall_misses::total 177381 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,12 +304,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,26 +340,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.675052 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.846521 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.846521 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 414091500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 414091500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 414091500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 414091500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 414091500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 414091500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21900.333192 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21900.333192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21900.333192 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,43 +418,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 376275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 376275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 376275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 376275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 376275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 376275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19900.333192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19900.333192 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30351.010864 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27796.806295 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.765897 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.438673 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.042799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15086 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13934 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses @@ -483,17 +483,17 @@ system.cpu.l2cache.demand_misses::total 127812 # nu system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses system.cpu.l2cache.overall_misses::total 127812 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208207500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1130236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1338443500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321243500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5321243500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 208207500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6451479500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6659687000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 208207500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6451479500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6659687000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210047000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) @@ -518,17 +518,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.714409 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52156.187375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52471.494893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52422.195676 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.236801 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.236801 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52105.334397 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52105.334397 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -550,17 +550,17 @@ system.cpu.l2cache.demand_mshr_misses::total 127812 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159943500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868345500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028289000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091943000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091943000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159943500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4960288500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5120232000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159943500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4960288500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5120232000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses @@ -572,17 +572,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.007014 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40313.161560 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40274.518252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.264372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.264372 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution @@ -597,19 +597,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) @@ -627,19 +625,19 @@ system.membus.pkt_count::total 339533 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214631 # Request fanout histogram +system.membus.snoop_fanout::samples 214640 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214631 # Request fanout histogram -system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_fanout::total 214640 # Request fanout histogram +system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |