diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux')
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt | 1102 | ||||
| -rw-r--r-- | tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1824 |
2 files changed, 1463 insertions, 1463 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 35c099c69..4f45fd20e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060132 # Number of seconds simulated -sim_ticks 60131512500 # Number of ticks simulated -final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060161 # Number of seconds simulated +sim_ticks 60161166500 # Number of ticks simulated +final_tick 60161166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320494 # Simulator instruction rate (inst/s) -host_op_rate 409865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271758284 # Simulator tick rate (ticks/s) -host_mem_usage 281048 # Number of bytes of host memory used -host_seconds 221.27 # Real time elapsed on the host +host_inst_rate 318648 # Simulator instruction rate (inst/s) +host_op_rate 407504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 270326146 # Simulator tick rate (ticks/s) +host_mem_usage 281460 # Number of bytes of host memory used +host_seconds 222.55 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory -system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 286272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7938560 # Number of bytes read from this memory +system.physmem.bytes_read::total 8224832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 286272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286272 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124040 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128513 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128515 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 4758418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 131954888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136713307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4758418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4758418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92074810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92074810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92074810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4758418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 131954888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 228788117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128513 # Number of read requests accepted system.physmem.writeReqs 86552 # Number of write requests accepted -system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128513 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side +system.physmem.bytesWritten 5537792 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8224832 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8086 # Per bank write bursts -system.physmem.perBankRdBursts::1 8335 # Per bank write bursts +system.physmem.perBankRdBursts::1 8337 # Per bank write bursts system.physmem.perBankRdBursts::2 8257 # Per bank write bursts system.physmem.perBankRdBursts::3 8155 # Per bank write bursts -system.physmem.perBankRdBursts::4 8301 # Per bank write bursts -system.physmem.perBankRdBursts::5 8413 # Per bank write bursts -system.physmem.perBankRdBursts::6 8070 # Per bank write bursts +system.physmem.perBankRdBursts::4 8300 # Per bank write bursts +system.physmem.perBankRdBursts::5 8411 # Per bank write bursts +system.physmem.perBankRdBursts::6 8071 # Per bank write bursts system.physmem.perBankRdBursts::7 7917 # Per bank write bursts system.physmem.perBankRdBursts::8 8054 # Per bank write bursts -system.physmem.perBankRdBursts::9 7613 # Per bank write bursts +system.physmem.perBankRdBursts::9 7612 # Per bank write bursts system.physmem.perBankRdBursts::10 7771 # Per bank write bursts -system.physmem.perBankRdBursts::11 7825 # Per bank write bursts +system.physmem.perBankRdBursts::11 7824 # Per bank write bursts system.physmem.perBankRdBursts::12 7888 # Per bank write bursts -system.physmem.perBankRdBursts::13 7870 # Per bank write bursts -system.physmem.perBankRdBursts::14 7981 # Per bank write bursts -system.physmem.perBankRdBursts::15 7974 # Per bank write bursts -system.physmem.perBankWrBursts::0 5400 # Per bank write bursts +system.physmem.perBankRdBursts::13 7869 # Per bank write bursts +system.physmem.perBankRdBursts::14 7983 # Per bank write bursts +system.physmem.perBankRdBursts::15 7973 # Per bank write bursts +system.physmem.perBankWrBursts::0 5399 # Per bank write bursts system.physmem.perBankWrBursts::1 5549 # Per bank write bursts -system.physmem.perBankWrBursts::2 5475 # Per bank write bursts +system.physmem.perBankWrBursts::2 5478 # Per bank write bursts system.physmem.perBankWrBursts::3 5349 # Per bank write bursts system.physmem.perBankWrBursts::4 5387 # Per bank write bursts -system.physmem.perBankWrBursts::5 5586 # Per bank write bursts +system.physmem.perBankWrBursts::5 5588 # Per bank write bursts system.physmem.perBankWrBursts::6 5325 # Per bank write bursts system.physmem.perBankWrBursts::7 5260 # Per bank write bursts system.physmem.perBankWrBursts::8 5187 # Per bank write bursts -system.physmem.perBankWrBursts::9 5135 # Per bank write bursts +system.physmem.perBankWrBursts::9 5136 # Per bank write bursts system.physmem.perBankWrBursts::10 5306 # Per bank write bursts system.physmem.perBankWrBursts::11 5279 # Per bank write bursts system.physmem.perBankWrBursts::12 5541 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 5706 # Pe system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60131481000 # Total gap between requests +system.physmem.totGap 60161135000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128515 # Read request sizes (log2) +system.physmem.readPktSize::6 128513 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,11 +98,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86552 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,28 +145,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -194,115 +194,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 418.627483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 258.357746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.584215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8602 26.17% 26.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6385 19.42% 45.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3434 10.45% 56.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2432 7.40% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2215 6.74% 70.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1621 4.93% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1317 4.01% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1216 3.70% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5649 17.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32871 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5351 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.014390 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.652764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.251849 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5349 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads -system.physmem.totQLat 3049168000 # Total ticks spent queuing -system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5351 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.170435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.160762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.581098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4912 91.80% 91.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.06% 91.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 408 7.62% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 22 0.41% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 5 0.09% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5351 # Writes before turning the bus around for reads +system.physmem.totQLat 3055484500 # Total ticks spent queuing +system.physmem.totMemAccLat 5465009500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23776.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42526.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 136.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 136.71 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.79 # Data bus utilization in percentage system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing -system.physmem.readRowHits 112228 # Number of row buffer hits during reads -system.physmem.writeRowHits 69923 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes -system.physmem.avgGap 279594.18 # Average gap between requests +system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing +system.physmem.readRowHits 112270 # Number of row buffer hits during reads +system.physmem.writeRowHits 69886 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.74 # Row buffer hit rate for writes +system.physmem.avgGap 279734.66 # Average gap between requests system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 123657660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 65710425 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ) -system.physmem_0.averagePower 386.918165 # Core power per rank (mW) -system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states -system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ) -system.physmem_1.averagePower 383.198268 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827796 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits +system.physmem_0.writeEnergy 226208700 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2513877600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2171898930 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 163742880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5875439160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3027961440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8657105625 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23294071200 # Total energy per rank (pJ) +system.physmem_0.averagePower 387.194467 # Core power per rank (mW) +system.physmem_0.totalIdleTime 54970200750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 277627750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1068464000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34200521750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 7885291750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3844571250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12884690000 # Time in different power states +system.physmem_1.actEnergy 111105540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 59035020 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 449634360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 225467460 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2466550320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2149128000 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 155904480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5311061070 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3203698560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8880552330 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23012901840 # Total energy per rank (pJ) +system.physmem_1.averagePower 382.520865 # Core power per rank (mW) +system.physmem_1.totalIdleTime 55040293250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 259491500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1048576000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 35050414500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8342978750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3812745000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 11646960750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14829931 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922625 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 344341 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9711925 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6581090 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 67.762982 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720914 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 175731 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158482 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 17249 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24894 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -332,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -362,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -423,16 +423,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120263025 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120322333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1183243 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.695872 # CPI: cycles per instruction -system.cpu.ipc 0.589667 # IPC: instructions per cycle +system.cpu.cpi 1.696708 # CPI: cycles per instruction +system.cpu.ipc 0.589376 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -472,338 +472,338 @@ system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked -system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 156451 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy +system.cpu.tickCycles 98402849 # Number of cycles that the object actually ticked +system.cpu.idleCycles 21919484 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 156448 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.144261 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42640706 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.601368 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 880402500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.144261 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3045 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86041472 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86041472 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22883524 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22883524 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642139 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642139 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83205 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83205 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits -system.cpu.dcache.overall_hits::total 42605460 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses -system.cpu.dcache.overall_misses::total 299788 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42525663 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42525663 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42608868 # number of overall hits +system.cpu.dcache.overall_hits::total 42608868 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47232 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47232 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207762 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207762 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44764 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44764 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 254994 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 254994 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299758 # number of overall misses +system.cpu.dcache.overall_misses::total 299758 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1840606500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1840606500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18547852000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18547852000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20388458500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20388458500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20388458500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20388458500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22930756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22930756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127969 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127969 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42780657 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42780657 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42908626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42908626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002060 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002060 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349803 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.349803 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005960 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005960 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38969.480437 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38969.480437 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89274.516033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89274.516033 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79956.620548 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79956.620548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68016.394892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68016.394892 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks -system.cpu.dcache.writebacks::total 128145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128143 # number of writebacks +system.cpu.dcache.writebacks::total 128143 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17700 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 17700 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100723 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100723 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 118423 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 118423 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 118423 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 118423 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29532 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29532 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107039 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107039 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23973 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23973 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136571 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136571 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 777371000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 777371000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9483957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9483957500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1891396500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1891396500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10261328500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10261328500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12152725000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12152725000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187334 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187334 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26206.830573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26206.830573 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.730645 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.730645 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.950169 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.950169 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75079.818549 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75079.818549 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75679.561125 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75679.561125 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 43545 # number of replacements -system.cpu.icache.tags.tagsinuse 1851.999823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26323.005553 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26323.005553 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88602.822336 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88602.822336 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78896.946565 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78896.946565 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75135.486304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75135.486304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75697.160903 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75697.160903 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 43580 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.022642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25068801 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 45622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 549.489303 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1851.999823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904297 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904297 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.022642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 897 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1022 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits -system.cpu.icache.overall_hits::total 25048343 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses -system.cpu.icache.overall_misses::total 45588 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042263500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1042263500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1042263500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1042263500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1042263500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1042263500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 50274470 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50274470 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25068801 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25068801 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25068801 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25068801 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25068801 # number of overall hits +system.cpu.icache.overall_hits::total 25068801 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 45623 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 45623 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 45623 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 45623 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 45623 # number of overall misses +system.cpu.icache.overall_misses::total 45623 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1044947000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1044947000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1044947000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1044947000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1044947000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1044947000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25114424 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25114424 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25114424 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25114424 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25114424 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25114424 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.672194 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22862.672194 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22862.672194 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.672194 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22862.672194 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93478.718523 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 110361.457869 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92868.436745 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93478.718523 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -824,128 +824,128 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 60 system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246157500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246157500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446695500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446695500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029647000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029647000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446695500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275804500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10722500000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446695500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275804500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10722500000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102318 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102318 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4474 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4474 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21722 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21722 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4474 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124040 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128514 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4474 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128514 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8250600500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8250600500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 448924000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 448924000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029137000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029137000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448924000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10279737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10728661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448924000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10279737500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10728661500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098065 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405981 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405981 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.623349 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.623349 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80636.842980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80636.842980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100340.634779 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100340.634779 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93413.912163 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93413.912163 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 406195 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 200065 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7850 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 97176 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 99127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43580 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53505 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134825 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5708928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18475968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24184896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 97173 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 303340 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037578 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.190694 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291971 96.25% 96.25% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11339 3.74% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 303340 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374820500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68448469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240848435 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 222299 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 93862 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 26198 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 26195 # Transaction distribution system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution -system.membus.trans_dist::CleanEvict 7237 # Transaction distribution -system.membus.trans_dist::ReadExReq 102317 # Transaction distribution -system.membus.trans_dist::ReadExResp 102317 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 7234 # Transaction distribution +system.membus.trans_dist::ReadExReq 102318 # Transaction distribution +system.membus.trans_dist::ReadExResp 102318 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26195 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 350812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13764160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 128515 # Request fanout histogram +system.membus.snoop_fanout::samples 128513 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 128513 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 128515 # Request fanout histogram -system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 128513 # Request fanout histogram +system.membus.reqLayer0.occupancy 588234000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677366750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index ad340b529..79d31fb69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.038007 # Number of seconds simulated -sim_ticks 38007342000 # Number of ticks simulated -final_tick 38007342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037944 # Number of seconds simulated +sim_ticks 37944194500 # Number of ticks simulated +final_tick 37944194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 224949 # Simulator instruction rate (inst/s) -host_op_rate 287684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120575368 # Simulator tick rate (ticks/s) -host_mem_usage 283980 # Number of bytes of host memory used -host_seconds 315.22 # Real time elapsed on the host +host_inst_rate 220724 # Simulator instruction rate (inst/s) +host_op_rate 282280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118113932 # Simulator tick rate (ticks/s) +host_mem_usage 283128 # Number of bytes of host memory used +host_seconds 321.25 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2373952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5705216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6169536 # Number of bytes read from this memory -system.physmem.bytes_read::total 14248704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2373952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2373952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6224192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6224192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 37093 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 89144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96399 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97253 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97253 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 62460353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 150108261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 162324848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 374893461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 62460353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 62460353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163762886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163762886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163762886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 62460353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 150108261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 162324848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 538656347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222637 # Number of read requests accepted -system.physmem.writeReqs 97253 # Number of write requests accepted -system.physmem.readBursts 222637 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97253 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14240000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6222848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14248768 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6224192 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2366464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5687552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176 # Number of bytes read from this memory +system.physmem.bytes_read::total 14232192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2366464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2366464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224000 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 36976 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88868 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96534 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222378 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97250 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97250 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 62366958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 149892548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 162822695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 375082201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 62366958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 62366958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 164030363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 164030363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 164030363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 62366958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 149892548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 162822695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 539112564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222379 # Number of read requests accepted +system.physmem.writeReqs 97250 # Number of write requests accepted +system.physmem.readBursts 222379 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97250 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14222400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6222336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14232256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9656 # Per bank write bursts -system.physmem.perBankRdBursts::1 9952 # Per bank write bursts -system.physmem.perBankRdBursts::2 12608 # Per bank write bursts -system.physmem.perBankRdBursts::3 25349 # Per bank write bursts -system.physmem.perBankRdBursts::4 17405 # Per bank write bursts -system.physmem.perBankRdBursts::5 22083 # Per bank write bursts -system.physmem.perBankRdBursts::6 11752 # Per bank write bursts -system.physmem.perBankRdBursts::7 14068 # Per bank write bursts -system.physmem.perBankRdBursts::8 11731 # Per bank write bursts -system.physmem.perBankRdBursts::9 15466 # Per bank write bursts -system.physmem.perBankRdBursts::10 11740 # Per bank write bursts -system.physmem.perBankRdBursts::11 11331 # Per bank write bursts -system.physmem.perBankRdBursts::12 9464 # Per bank write bursts -system.physmem.perBankRdBursts::13 9568 # Per bank write bursts -system.physmem.perBankRdBursts::14 9844 # Per bank write bursts -system.physmem.perBankRdBursts::15 20483 # Per bank write bursts -system.physmem.perBankWrBursts::0 5965 # Per bank write bursts -system.physmem.perBankWrBursts::1 6210 # Per bank write bursts -system.physmem.perBankWrBursts::2 6157 # Per bank write bursts -system.physmem.perBankWrBursts::3 6128 # Per bank write bursts -system.physmem.perBankWrBursts::4 6115 # Per bank write bursts -system.physmem.perBankWrBursts::5 6243 # Per bank write bursts -system.physmem.perBankWrBursts::6 6020 # Per bank write bursts -system.physmem.perBankWrBursts::7 5952 # Per bank write bursts -system.physmem.perBankWrBursts::8 5952 # Per bank write bursts -system.physmem.perBankWrBursts::9 6130 # Per bank write bursts -system.physmem.perBankWrBursts::10 6213 # Per bank write bursts -system.physmem.perBankWrBursts::11 5918 # Per bank write bursts -system.physmem.perBankWrBursts::12 6006 # Per bank write bursts -system.physmem.perBankWrBursts::13 6051 # Per bank write bursts -system.physmem.perBankWrBursts::14 6145 # Per bank write bursts -system.physmem.perBankWrBursts::15 6027 # Per bank write bursts +system.physmem.perBankRdBursts::0 9631 # Per bank write bursts +system.physmem.perBankRdBursts::1 9947 # Per bank write bursts +system.physmem.perBankRdBursts::2 12518 # Per bank write bursts +system.physmem.perBankRdBursts::3 24674 # Per bank write bursts +system.physmem.perBankRdBursts::4 17362 # Per bank write bursts +system.physmem.perBankRdBursts::5 22065 # Per bank write bursts +system.physmem.perBankRdBursts::6 11751 # Per bank write bursts +system.physmem.perBankRdBursts::7 14087 # Per bank write bursts +system.physmem.perBankRdBursts::8 11655 # Per bank write bursts +system.physmem.perBankRdBursts::9 16110 # Per bank write bursts +system.physmem.perBankRdBursts::10 11699 # Per bank write bursts +system.physmem.perBankRdBursts::11 11328 # Per bank write bursts +system.physmem.perBankRdBursts::12 9447 # Per bank write bursts +system.physmem.perBankRdBursts::13 9546 # Per bank write bursts +system.physmem.perBankRdBursts::14 9858 # Per bank write bursts +system.physmem.perBankRdBursts::15 20547 # Per bank write bursts +system.physmem.perBankWrBursts::0 5941 # Per bank write bursts +system.physmem.perBankWrBursts::1 6221 # Per bank write bursts +system.physmem.perBankWrBursts::2 6116 # Per bank write bursts +system.physmem.perBankWrBursts::3 6136 # Per bank write bursts +system.physmem.perBankWrBursts::4 6032 # Per bank write bursts +system.physmem.perBankWrBursts::5 6294 # Per bank write bursts +system.physmem.perBankWrBursts::6 6000 # Per bank write bursts +system.physmem.perBankWrBursts::7 5967 # Per bank write bursts +system.physmem.perBankWrBursts::8 5964 # Per bank write bursts +system.physmem.perBankWrBursts::9 6073 # Per bank write bursts +system.physmem.perBankWrBursts::10 6219 # Per bank write bursts +system.physmem.perBankWrBursts::11 5919 # Per bank write bursts +system.physmem.perBankWrBursts::12 6077 # Per bank write bursts +system.physmem.perBankWrBursts::13 6073 # Per bank write bursts +system.physmem.perBankWrBursts::14 6160 # Per bank write bursts +system.physmem.perBankWrBursts::15 6032 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 38007330500 # Total gap between requests +system.physmem.totGap 37944183500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222637 # Read request sizes (log2) +system.physmem.readPktSize::6 222379 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97253 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 112108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97250 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 111691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 47 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,119 +198,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 153.968593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.497917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 209.528989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82983 62.44% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32243 24.26% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6367 4.79% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2726 2.05% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1184 0.89% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1005 0.76% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 875 0.66% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 807 0.61% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4709 3.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132899 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.820840 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 210.672420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5878 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 132661 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 154.093818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.620444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 209.524421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82661 62.31% 62.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32331 24.37% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6343 4.78% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2828 2.13% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1153 0.87% 94.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1000 0.75% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 785 0.59% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 836 0.63% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4724 3.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132661 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5873 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.833986 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.191475 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5868 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.528392 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.490234 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.186972 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4697 79.85% 79.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 46 0.78% 80.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 744 12.65% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 191 3.25% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.55% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 73 1.24% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.34% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 15 0.26% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads -system.physmem.totQLat 8329547257 # Total ticks spent queuing -system.physmem.totMemAccLat 12501422257 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1112500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37436.00 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4999.98 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56185.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 163.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 374.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 163.76 # Average system write bandwidth in MiByte/s +system.physmem.rdPerTurnAround::total 5873 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.514141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.221324 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4642 79.04% 79.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 60 1.02% 80.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 721 12.28% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 237 4.04% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 117 1.99% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.85% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.17% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.15% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads +system.physmem.totQLat 8400725955 # Total ticks spent queuing +system.physmem.totMemAccLat 12567444705 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1111125000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37802.79 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 56552.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 163.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 375.08 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 164.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.21 # Data bus utilization in percentage system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing -system.physmem.readRowHits 157173 # Number of row buffer hits during reads -system.physmem.writeRowHits 29653 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.49 # Row buffer hit rate for writes -system.physmem.avgGap 118813.75 # Average gap between requests -system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 507596880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 269771370 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 877313220 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 254683800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3009892080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2962459860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75632160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13054365150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 948417120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 77983215 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 22038660255 # Total energy per rank (pJ) -system.physmem_0.averagePower 579.852702 # Core power per rank (mW) -system.physmem_0.totalIdleTime 31313307761 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 43781047 # Time in different power states -system.physmem_0.memoryStateTime::REF 1273526000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 214718250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2469720434 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5376727192 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28628869077 # Time in different power states -system.physmem_1.actEnergy 441337680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 234557565 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 711336780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 252841140 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2899256880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2760551040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 73978560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11934955830 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1428119040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 493845795 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 21231004530 # Total energy per rank (pJ) -system.physmem_1.averagePower 558.602674 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31760586804 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 51273339 # Time in different power states -system.physmem_1.memoryStateTime::REF 1226918000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1868150750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3718457459 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4968563857 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26173978595 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17074531 # Number of BP lookups -system.cpu.branchPred.condPredicted 11460402 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598628 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9274722 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374340 # Number of BTB hits +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 156951 # Number of row buffer hits during reads +system.physmem.writeRowHits 29827 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.67 # Row buffer hit rate for writes +system.physmem.avgGap 118713.21 # Average gap between requests +system.physmem.pageHitRate 58.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 506618700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 269259045 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 871329900 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254250540 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3004974960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2939010630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75129120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12925802790 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1053663840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 77310705 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 21977801430 # Total energy per rank (pJ) +system.physmem_0.averagePower 579.213801 # Core power per rank (mW) +system.physmem_0.totalIdleTime 31303061618 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 43527335 # Time in different power states +system.physmem_0.memoryStateTime::REF 1271434000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 212368250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2743799817 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5326073297 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28346991801 # Time in different power states +system.physmem_1.actEnergy 440652240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 234189450 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 715349460 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 253258740 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2887578720.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2772991290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 73095360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11918051910 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1378656480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 511952955 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 21185918985 # Total energy per rank (pJ) +system.physmem_1.averagePower 558.344142 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31672221792 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 50102341 # Time in different power states +system.physmem_1.memoryStateTime::REF 1221978000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1946071250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3589983863 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4999892367 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26136166679 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17059712 # Number of BP lookups +system.cpu.branchPred.condPredicted 11436495 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 610883 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9177884 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7343978 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.510092 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1855435 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101567 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 233050 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195925 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37125 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22231 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 80.018205 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1859096 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101568 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 235599 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 198019 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37580 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22235 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -400,7 +400,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -431,241 +431,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 76014685 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 75888390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5565404 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87125388 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17074531 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9425700 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 66120510 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1223729 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 11256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 32224 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22440736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69274 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 72341306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.522198 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.331033 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5573583 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87028801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17059712 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9401093 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 65975948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1248205 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11552 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 20 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 32118 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22429818 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69336 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 72217323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.523317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.330813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27150688 37.53% 37.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8169627 11.29% 48.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9114831 12.60% 61.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27906160 38.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27066857 37.48% 37.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8167411 11.31% 48.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9106696 12.61% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27876359 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 72341306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224621 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.146165 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8942287 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 26299816 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30976482 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5677371 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 445350 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3133946 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168438 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100318297 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2804928 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 445350 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13582767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11480611 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 882043 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31792045 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14158490 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98346425 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 855389 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4229008 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4663621 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5443965 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103273055 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453619684 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114297516 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 686 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 72217323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224800 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.146800 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8951903 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26171728 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30965562 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5674558 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 453572 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6946604 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172649 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100221832 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2852875 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 453572 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13609160 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11386876 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 864961 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31760902 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14141852 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98228803 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 864073 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4236637 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 68346 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4658326 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5438830 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103135317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453117590 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114171014 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 768 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9643686 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18991 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19021 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12815345 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24159121 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21761593 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1442839 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2330212 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97411129 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34857 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94489103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 595557 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6763379 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17995254 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 72341306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.306157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.170975 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9505948 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 19046 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12792135 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24137829 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21734716 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1433415 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2312086 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97293576 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34871 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94397579 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 595173 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6645840 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17792691 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1085 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 72217323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.307132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.170641 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24199109 33.45% 33.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17470195 24.15% 57.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17034708 23.55% 81.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11601119 16.04% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2034740 2.81% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1435 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24111122 33.39% 33.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17469676 24.19% 57.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17013658 23.56% 81.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11592271 16.05% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2029206 2.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1390 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 72341306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72217323 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6739464 22.68% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 40 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11065982 37.24% 59.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11909373 40.08% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 33 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6732689 22.67% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 34 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11048676 37.21% 59.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11914326 40.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 49 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49308872 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86547 0.09% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 13 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23960981 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21132544 22.37% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 62 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49269666 52.19% 52.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86409 0.09% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23933468 25.35% 77.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21107870 22.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 70 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94489103 # Type of FU issued -system.cpu.iq.rate 1.243037 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29714913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291629642 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104220574 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93205627 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 544 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124203819 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 197 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1369166 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94397579 # Type of FU issued +system.cpu.iq.rate 1.243900 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29695795 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314582 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 291303077 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 103985333 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93134762 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 690 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124093153 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368431 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1292859 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2033 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11913 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1205855 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1271567 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1549 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11881 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1178978 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 148706 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 187344 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 147641 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185447 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 445350 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 625818 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1199933 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97461708 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 453572 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 612952 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1120138 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97344492 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24159121 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21761593 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18937 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1609 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1195657 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11913 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250763 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 222991 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 473754 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93695211 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23697676 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 793892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24137829 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21734716 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18951 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1593 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1115880 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11881 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 249751 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 231660 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 481411 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93615083 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23674361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 782496 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15722 # number of nop insts executed -system.cpu.iew.exec_refs 44622526 # number of memory reference insts executed -system.cpu.iew.exec_branches 14207940 # Number of branches executed -system.cpu.iew.exec_stores 20924850 # Number of stores executed -system.cpu.iew.exec_rate 1.232594 # Inst execution rate -system.cpu.iew.wb_sent 93313259 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93205726 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44957522 # num instructions producing a value -system.cpu.iew.wb_consumers 76634731 # num instructions consuming a value -system.cpu.iew.wb_rate 1.226154 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586647 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5905401 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 16045 # number of nop insts executed +system.cpu.iew.exec_refs 44580255 # number of memory reference insts executed +system.cpu.iew.exec_branches 14200394 # Number of branches executed +system.cpu.iew.exec_stores 20905894 # Number of stores executed +system.cpu.iew.exec_rate 1.233589 # Inst execution rate +system.cpu.iew.wb_sent 93237318 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93134858 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44916796 # num instructions producing a value +system.cpu.iew.wb_consumers 76568590 # num instructions consuming a value +system.cpu.iew.wb_rate 1.227261 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586622 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5786029 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 432114 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 71383083 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.270443 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.106463 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 440353 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 71261477 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.272611 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.107279 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 37916370 53.12% 53.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16693361 23.39% 76.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4299601 6.02% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4172974 5.85% 88.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1943479 2.72% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1233650 1.73% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 737671 1.03% 93.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 579334 0.81% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3806643 5.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 37792643 53.03% 53.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16691471 23.42% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4304606 6.04% 82.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4169247 5.85% 88.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1943443 2.73% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1235947 1.73% 92.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 743394 1.04% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579944 0.81% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3800782 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 71383083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71261477 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -715,552 +715,552 @@ system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3806643 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 164144701 # The number of ROB reads -system.cpu.rob.rob_writes 194146843 # The number of ROB writes -system.cpu.timesIdled 54077 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3673379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3800782 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 163909584 # The number of ROB reads +system.cpu.rob.rob_writes 193905843 # The number of ROB writes +system.cpu.timesIdled 54309 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3671067 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.072024 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.072024 # CPI: Total CPI of All Threads -system.cpu.ipc 0.932815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.932815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101986551 # number of integer regfile reads -system.cpu.int_regfile_writes 56614441 # number of integer regfile writes -system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 345121100 # number of cc regfile reads -system.cpu.cc_regfile_writes 38758964 # number of cc regfile writes -system.cpu.misc_regfile_reads 44102244 # number of misc regfile reads +system.cpu.cpi 1.070243 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.070243 # CPI: Total CPI of All Threads +system.cpu.ipc 0.934368 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.934368 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101911048 # number of integer regfile reads +system.cpu.int_regfile_writes 56566498 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cc_regfile_reads 344842465 # number of cc regfile reads +system.cpu.cc_regfile_writes 38739142 # number of cc regfile writes +system.cpu.misc_regfile_reads 44068796 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484796 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.868688 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40338903 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485308 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.120210 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 154723500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.868688 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997790 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484861 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.868864 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40324171 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485373 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.078727 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 154340500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.868864 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84466908 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84466908 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21416602 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21416602 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830761 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830761 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60264 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60264 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84436477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84436477 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21401665 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21401665 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831129 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831129 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60098 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60098 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15305 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15305 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40247363 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40247363 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40307627 # number of overall hits -system.cpu.dcache.overall_hits::total 40307627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 563583 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 563583 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019140 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019140 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68608 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68608 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 617 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 617 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1582723 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1582723 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1651331 # number of overall misses -system.cpu.dcache.overall_misses::total 1651331 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14467064000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14467064000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14294982430 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14294982430 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6393500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6393500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28762046430 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28762046430 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28762046430 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28762046430 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21980185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21980185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40232794 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40232794 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40292892 # number of overall hits +system.cpu.dcache.overall_hits::total 40292892 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 563103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 563103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018772 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68943 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68943 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1581875 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1581875 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1650818 # number of overall misses +system.cpu.dcache.overall_misses::total 1650818 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14421291500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14421291500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14222478926 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14222478926 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5900000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5900000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28643770426 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28643770426 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28643770426 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28643770426 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21964768 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21964768 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128872 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 129041 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 129041 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41830086 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41830086 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41958958 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41958958 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025641 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025641 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051342 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051342 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532373 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532373 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038749 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038749 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037837 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037837 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039356 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039356 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25669.801964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25669.801964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14026.514934 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14026.514934 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10362.236629 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10362.236629 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18172.508032 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18172.508032 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17417.493180 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17417.493180 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2976739 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131356 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.661614 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484796 # number of writebacks -system.cpu.dcache.writebacks::total 484796 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264511 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 264511 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870576 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870576 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 617 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 617 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135087 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135087 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135087 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135087 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299072 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299072 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148564 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148564 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37686 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37686 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447636 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447636 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485322 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485322 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7113004000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7113004000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2350412971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2350412971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001432500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001432500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9463416971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9463416971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11464849471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11464849471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013606 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013606 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292430 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292430 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010701 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010701 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23783.583886 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23783.583886 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15820.878349 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15820.878349 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53108.117073 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53108.117073 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21140.875557 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21140.875557 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23623.181045 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23623.181045 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325456 # number of replacements -system.cpu.icache.tags.tagsinuse 510.336563 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22103277 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 325967 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.808327 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1174665500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.336563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996751 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996751 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu.dcache.demand_accesses::cpu.data 41814669 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41814669 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41943710 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41943710 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025637 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025637 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051324 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051324 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.534272 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.534272 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037831 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037831 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039358 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039358 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25610.397210 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25610.397210 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13960.414034 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13960.414034 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9546.925566 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9546.925566 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18107.480317 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18107.480317 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17351.258846 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17351.258846 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 104 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2957939 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131286 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.933333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.530498 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484861 # number of writebacks +system.cpu.dcache.writebacks::total 484861 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263994 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 263994 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870189 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1134183 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1134183 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1134183 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1134183 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299109 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299109 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148583 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148583 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37695 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37695 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447692 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485387 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485387 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7100123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7100123000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2335671469 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2335671469 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001428000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001428000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9435794469 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9435794469 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11437222469 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11437222469 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292116 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292116 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010707 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010707 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011572 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011572 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23737.577271 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23737.577271 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15719.641339 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15719.641339 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53095.317681 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53095.317681 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21076.531341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21076.531341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23563.100102 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23563.100102 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 325105 # number of replacements +system.cpu.icache.tags.tagsinuse 510.398248 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22092527 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 325617 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.848199 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1172472500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.398248 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996872 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996872 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 333 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45207041 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45207041 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22103280 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22103280 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22103280 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22103280 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22103280 # number of overall hits -system.cpu.icache.overall_hits::total 22103280 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 337250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 337250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 337250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 337250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 337250 # number of overall misses -system.cpu.icache.overall_misses::total 337250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5803062852 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22429606 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22429606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22429606 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22429606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015028 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015028 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015028 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015028 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015028 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015028 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17242.025932 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17242.025932 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17242.025932 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17242.025932 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 559324 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 118 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25723 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.744120 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 39.333333 # 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Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 681508 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141902 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.802667 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78985 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 125384 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15697.006900 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 681705 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141714 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.810428 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15625.141607 # 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mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113797 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239620 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239620 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.155604 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113797 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183685 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113560 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239348 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239348 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155175 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113560 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297350 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 88935.087621 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15571.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15571.428571 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86694.598747 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86694.598747 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78729.592387 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78729.592387 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79664.569984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79664.569984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79861.016493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84186.597194 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1621556 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810285 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18616 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18570 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 46 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 662693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 549823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 146207 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297026 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89620.579120 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15464.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15464.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87021.110573 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87021.110573 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78997.944668 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78997.944668 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79570.072703 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79570.072703 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79891.378283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84537.774963 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1620984 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80349 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18528 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18483 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 45 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 662386 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 357113 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 550103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28134 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 146171 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325982 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977404 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455440 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2432844 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41691008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62086656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103777664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 271801 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6225152 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1083090 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091523 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.288499 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336756 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455635 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2431987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41646144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62094976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103741120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 271569 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6224896 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1082573 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091409 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288334 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 984008 90.85% 90.85% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 99036 9.14% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 46 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 983661 90.86% 90.86% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98867 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 45 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1083090 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1621030000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1082573 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1620458000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489099244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 488577734 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728047842 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728149334 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 348230 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 347777 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205067 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214175 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97253 # Transaction distribution -system.membus.trans_dist::CleanEvict 28326 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214112 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97250 # Transaction distribution +system.membus.trans_dist::CleanEvict 28134 # Transaction distribution system.membus.trans_dist::UpgradeReq 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 8461 # Transaction distribution -system.membus.trans_dist::ReadExResp 8461 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570866 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570866 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20472896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20472896 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8266 # Transaction distribution +system.membus.trans_dist::ReadExResp 8266 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214113 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570155 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20456192 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222651 # Request fanout histogram +system.membus.snoop_fanout::samples 222393 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222651 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222393 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222651 # Request fanout histogram -system.membus.reqLayer0.occupancy 835869990 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222393 # Request fanout histogram +system.membus.reqLayer0.occupancy 835299244 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1175713686 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1174434906 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |