diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux')
4 files changed, 1654 insertions, 1521 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c949b9a6e..e5a2f02e5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057847 # Number of seconds simulated -sim_ticks 57847312000 # Number of ticks simulated -final_tick 57847312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057816 # Number of seconds simulated +sim_ticks 57815555000 # Number of ticks simulated +final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 186854 # Simulator instruction rate (inst/s) -host_op_rate 238959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152421830 # Simulator tick rate (ticks/s) -host_mem_usage 261476 # Number of bytes of host memory used -host_seconds 379.52 # Real time elapsed on the host +host_inst_rate 199176 # Simulator instruction rate (inst/s) +host_op_rate 254717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 162383906 # Simulator tick rate (ticks/s) +host_mem_usage 320240 # Number of bytes of host memory used +host_seconds 356.04 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8247680 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 8247808 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 128870 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 142576720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142576720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5607037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92880098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92880098 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92880098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 142576720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235456818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128870 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 142657249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 142657249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128872 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128870 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247680 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::0 8159 # Per bank write bursts system.physmem.perBankRdBursts::1 8375 # Per bank write bursts system.physmem.perBankRdBursts::2 8229 # Per bank write bursts system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8319 # Per bank write bursts +system.physmem.perBankRdBursts::4 8320 # Per bank write bursts system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8089 # Per bank write bursts +system.physmem.perBankRdBursts::6 8088 # Per bank write bursts system.physmem.perBankRdBursts::7 7970 # Per bank write bursts system.physmem.perBankRdBursts::8 8071 # Per bank write bursts -system.physmem.perBankRdBursts::9 7641 # Per bank write bursts -system.physmem.perBankRdBursts::10 7819 # Per bank write bursts +system.physmem.perBankRdBursts::9 7640 # Per bank write bursts +system.physmem.perBankRdBursts::10 7820 # Per bank write bursts system.physmem.perBankRdBursts::11 7830 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts system.physmem.perBankRdBursts::14 7977 # Per bank write bursts system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5181 # Per bank write bursts +system.physmem.perBankWrBursts::0 5183 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5198 # Per bank write bursts -system.physmem.perBankWrBursts::7 5047 # Per bank write bursts +system.physmem.perBankWrBursts::6 5194 # Per bank write bursts +system.physmem.perBankWrBursts::7 5048 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::9 5086 # Per bank write bursts +system.physmem.perBankWrBursts::10 5252 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts @@ -78,14 +78,14 @@ system.physmem.perBankWrBursts::14 5451 # Pe system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57847280000 # Total gap between requests +system.physmem.totGap 57815523000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128870 # Read request sizes (log2) +system.physmem.readPktSize::6 128872 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,7 +95,7 @@ system.physmem.writePktSize::5 0 # Wr system.physmem.writePktSize::6 83951 # Write request sizes (log2) system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -140,27 +140,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -189,97 +189,110 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.780687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.561409 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.824723 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12139 31.63% 31.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8088 21.07% 52.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4086 10.65% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2872 7.48% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2530 6.59% 77.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1664 4.34% 81.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1273 3.32% 85.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1227 3.20% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4500 11.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38379 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.981187 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 361.178240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.276377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.259366 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.777117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4528 87.82% 87.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 480 9.31% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 121 2.35% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 14 0.27% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads -system.physmem.totQLat 1539171500 # Total ticks spent queuing -system.physmem.totMemAccLat 3955390250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11944.06 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 1505377000 # Total ticks spent queuing +system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30694.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.88 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.84 # Data bus utilization in percentage system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.48 # Average write queue length when enqueuing -system.physmem.readRowHits 112176 # Number of row buffer hits during reads -system.physmem.writeRowHits 62224 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.12 # Row buffer hit rate for writes -system.physmem.avgGap 271811.90 # Average gap between requests -system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 32236826000 # Time in different power states -system.physmem.memoryStateTime::REF 1931540000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23675959000 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 151237800 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 138899880 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 82520625 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 75788625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 512678400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 492078600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 272322000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 271486080 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 3778092240 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 3778092240 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 11712850200 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 11277598770 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 24432156750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 24813956250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 40941858015 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 40847900445 # Total energy per rank (pJ) -system.physmem.averagePower::0 707.794027 # Core power per rank (mW) -system.physmem.averagePower::1 706.169709 # Core power per rank (mW) -system.cpu.branchPred.lookups 14825675 # Number of BP lookups -system.cpu.branchPred.condPredicted 9917897 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 395023 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9456669 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6745546 # Number of BTB hits +system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing +system.physmem.readRowHits 112203 # Number of row buffer hits during reads +system.physmem.writeRowHits 62134 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes +system.physmem.avgGap 271660.13 # Average gap between requests +system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.837327 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.292941 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 14822198 # Number of BP lookups +system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.331100 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719567 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -301,6 +314,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -322,6 +343,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -343,6 +372,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -365,89 +402,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115694624 # number of cpu cycles simulated +system.cpu.numCycles 115631110 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1146301 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.631452 # CPI: cycles per instruction -system.cpu.ipc 0.612951 # IPC: instructions per cycle -system.cpu.tickCycles 96938261 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18756363 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156422 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.596798 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42665450 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160518 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.798540 # Average number of references to valid blocks. +system.cpu.cpi 1.630556 # CPI: cycles per instruction +system.cpu.ipc 0.613288 # IPC: instructions per cycle +system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156428 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.596798 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993310 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993310 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.581764 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993306 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 750 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3296 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86015580 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86015580 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 22989734 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22989734 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19643878 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643878 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 22989229 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 19643835 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 42633612 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42633612 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 42633612 # number of overall hits -system.cpu.dcache.overall_hits::total 42633612 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 56058 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56058 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 206023 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206023 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 262081 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262081 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 262081 # number of overall misses -system.cpu.dcache.overall_misses::total 262081 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2156088187 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2156088187 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15241867750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15241867750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17397955937 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17397955937 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17397955937 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17397955937 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 23045792 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23045792 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 42633064 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 42633064 # number of overall hits +system.cpu.dcache.overall_hits::total 42633064 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 56065 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 206066 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 262131 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 262131 # number of overall misses +system.cpu.dcache.overall_misses::total 262131 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2147242437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15196521000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 17343763437 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 17343763437 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42895693 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42895693 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42895693 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42895693 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002432 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002432 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010379 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010379 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38461.739395 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38461.739395 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73981.389214 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73981.389214 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66383.888710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66383.888710 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66383.888710 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 42895195 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42895195 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002433 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.006111 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.006111 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38299.160564 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73745.892093 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66164.488126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,32 +493,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128433 # number of writebacks -system.cpu.dcache.writebacks::total 128433 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2574 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2574 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 98989 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 98989 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 101563 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101563 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 101563 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101563 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53484 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53484 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107034 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107034 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9597585313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9597585313 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses @@ -490,68 +527,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # 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Number of tag accesses -system.cpu.icache.tags.data_accesses 50299111 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25082437 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25082437 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25082437 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25082437 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25082437 # number of overall hits -system.cpu.icache.overall_hits::total 25082437 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44746 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44746 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44746 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44746 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44746 # number of overall misses -system.cpu.icache.overall_misses::total 44746 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20061.653287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20061.653287 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50300884 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50300884 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25083355 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25083355 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25083355 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25083355 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25083355 # number of overall hits +system.cpu.icache.overall_hits::total 25083355 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44725 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44725 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44725 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20031.917026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20031.917026 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -560,103 +597,103 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44746 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44746 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44746 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44746 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44746 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44746 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 806263262 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 806263262 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 806263262 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 806263262 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 806263262 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 806263262 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001781 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001781 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001781 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001781 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18018.666741 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18018.666741 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18018.666741 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18018.666741 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44725 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44725 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44725 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44725 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44725 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44725 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804564511 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 804564511 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804564511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 804564511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804564511 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 804564511 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9726 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19542 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3229.441462 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098555 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9778 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19493 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2903460 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2903460 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 71567 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71567 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128433 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128433 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4753 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4753 # 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number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128433 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128433 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 205264 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 205264 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 205264 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 205264 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271434 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.271434 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955594 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955594 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628186 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.628186 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628186 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.628186 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74534.017177 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74534.017177 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 73125.934924 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73125.934924 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73417.097732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73417.097732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73417.097732 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 128946 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128946 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 128946 # number of overall misses +system.cpu.l2cache.overall_misses::total 128946 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978063750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1978063750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7455355000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7455355000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9433418750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9433418750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9433418750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9433418750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 98213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 98213 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128441 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128441 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107036 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107036 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 205249 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205249 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 205249 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205249 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.271502 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.271502 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955576 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955576 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628242 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.628242 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628242 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.628242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74182.027002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74182.027002 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72890.908380 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73157.901370 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,52 +710,52 @@ system.cpu.l2cache.demand_mshr_hits::cpu.inst 73 system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26590 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26590 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26592 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102281 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 128871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128871 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 128871 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128871 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1644904750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1644904750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6188348750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6188348750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7833253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7833253500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7833253500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7833253500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270691 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270691 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627831 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627831 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627831 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61861.780745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61861.780745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60503.404836 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60503.404836 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60783.679028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60783.679028 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 128873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128873 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 128873 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128873 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1635105500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1635105500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6164329000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6164329000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7799434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7799434500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7799434500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7799434500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.270758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270758 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955576 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955576 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.627886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627886 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.627886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627886 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61488.624398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61488.624398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60268.564054 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60268.564054 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89491 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449469 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 538960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2863680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21356544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128441 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107036 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107036 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89449 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449489 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 538938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2862336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18493760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21356096 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333697 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333690 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -727,41 +764,41 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 333697 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333697 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295281500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68080238 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268447937 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26589 # Transaction distribution -system.membus.trans_dist::ReadResp 26589 # Transaction distribution +system.membus.trans_dist::ReadReq 26591 # Transaction distribution +system.membus.trans_dist::ReadResp 26591 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution system.membus.trans_dist::ReadExReq 102281 # Transaction distribution system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212821 # Request fanout histogram +system.membus.snoop_fanout::samples 212823 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212821 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212821 # Request fanout histogram -system.membus.reqLayer0.occupancy 929388500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 212823 # Request fanout histogram +system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1213397000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index d04d5cf1b..6394c9beb 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.032615 # Number of seconds simulated -sim_ticks 32615215000 # Number of ticks simulated -final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033020 # Number of seconds simulated +sim_ticks 33019504000 # Number of ticks simulated +final_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125661 # Simulator instruction rate (inst/s) -host_op_rate 160706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57800178 # Simulator tick rate (ticks/s) -host_mem_usage 335740 # Number of bytes of host memory used -host_seconds 564.28 # Real time elapsed on the host +host_inst_rate 123822 # Simulator instruction rate (inst/s) +host_op_rate 158353 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57659893 # Simulator tick rate (ticks/s) +host_mem_usage 322352 # Number of bytes of host memory used +host_seconds 572.66 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory -system.physmem.bytes_read::total 9977536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory -system.physmem.bytes_written::total 6303424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory -system.physmem.num_reads::total 155899 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 98491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 155899 # Number of read requests accepted -system.physmem.writeReqs 98491 # Number of write requests accepted -system.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory +system.physmem.bytes_read::total 9307712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory +system.physmem.bytes_written::total 6262016 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145433 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97844 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145433 # Number of read requests accepted +system.physmem.writeReqs 97844 # Number of write requests accepted +system.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue +system.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10106 # Per bank write bursts -system.physmem.perBankRdBursts::1 10077 # Per bank write bursts -system.physmem.perBankRdBursts::2 9750 # Per bank write bursts -system.physmem.perBankRdBursts::3 10345 # Per bank write bursts -system.physmem.perBankRdBursts::4 10619 # Per bank write bursts -system.physmem.perBankRdBursts::5 10733 # Per bank write bursts -system.physmem.perBankRdBursts::6 9548 # Per bank write bursts -system.physmem.perBankRdBursts::7 9567 # Per bank write bursts -system.physmem.perBankRdBursts::8 9971 # Per bank write bursts -system.physmem.perBankRdBursts::9 9445 # Per bank write bursts -system.physmem.perBankRdBursts::10 9639 # Per bank write bursts -system.physmem.perBankRdBursts::11 9476 # Per bank write bursts -system.physmem.perBankRdBursts::12 8930 # Per bank write bursts -system.physmem.perBankRdBursts::13 9084 # Per bank write bursts -system.physmem.perBankRdBursts::14 9062 # Per bank write bursts -system.physmem.perBankRdBursts::15 9408 # Per bank write bursts -system.physmem.perBankWrBursts::0 6017 # Per bank write bursts -system.physmem.perBankWrBursts::1 6275 # Per bank write bursts -system.physmem.perBankWrBursts::2 6171 # Per bank write bursts -system.physmem.perBankWrBursts::3 6231 # Per bank write bursts -system.physmem.perBankWrBursts::4 6142 # Per bank write bursts -system.physmem.perBankWrBursts::5 6389 # Per bank write bursts -system.physmem.perBankWrBursts::6 6054 # Per bank write bursts -system.physmem.perBankWrBursts::7 6025 # Per bank write bursts -system.physmem.perBankWrBursts::8 6057 # Per bank write bursts -system.physmem.perBankWrBursts::9 6227 # Per bank write bursts -system.physmem.perBankWrBursts::10 6350 # Per bank write bursts -system.physmem.perBankWrBursts::11 5949 # Per bank write bursts -system.physmem.perBankWrBursts::12 6129 # Per bank write bursts -system.physmem.perBankWrBursts::13 6148 # Per bank write bursts -system.physmem.perBankWrBursts::14 6212 # Per bank write bursts -system.physmem.perBankWrBursts::15 6088 # Per bank write bursts +system.physmem.perBankRdBursts::0 9146 # Per bank write bursts +system.physmem.perBankRdBursts::1 9381 # Per bank write bursts +system.physmem.perBankRdBursts::2 9349 # Per bank write bursts +system.physmem.perBankRdBursts::3 9489 # Per bank write bursts +system.physmem.perBankRdBursts::4 9691 # Per bank write bursts +system.physmem.perBankRdBursts::5 9742 # Per bank write bursts +system.physmem.perBankRdBursts::6 9065 # Per bank write bursts +system.physmem.perBankRdBursts::7 9033 # Per bank write bursts +system.physmem.perBankRdBursts::8 9160 # Per bank write bursts +system.physmem.perBankRdBursts::9 8585 # Per bank write bursts +system.physmem.perBankRdBursts::10 8818 # Per bank write bursts +system.physmem.perBankRdBursts::11 8754 # Per bank write bursts +system.physmem.perBankRdBursts::12 8666 # Per bank write bursts +system.physmem.perBankRdBursts::13 8713 # Per bank write bursts +system.physmem.perBankRdBursts::14 8726 # Per bank write bursts +system.physmem.perBankRdBursts::15 9002 # Per bank write bursts +system.physmem.perBankWrBursts::0 5993 # Per bank write bursts +system.physmem.perBankWrBursts::1 6194 # Per bank write bursts +system.physmem.perBankWrBursts::2 6159 # Per bank write bursts +system.physmem.perBankWrBursts::3 6198 # Per bank write bursts +system.physmem.perBankWrBursts::4 6133 # Per bank write bursts +system.physmem.perBankWrBursts::5 6325 # Per bank write bursts +system.physmem.perBankWrBursts::6 6074 # Per bank write bursts +system.physmem.perBankWrBursts::7 6046 # Per bank write bursts +system.physmem.perBankWrBursts::8 6012 # Per bank write bursts +system.physmem.perBankWrBursts::9 6139 # Per bank write bursts +system.physmem.perBankWrBursts::10 6243 # Per bank write bursts +system.physmem.perBankWrBursts::11 5934 # Per bank write bursts +system.physmem.perBankWrBursts::12 6049 # Per bank write bursts +system.physmem.perBankWrBursts::13 6103 # Per bank write bursts +system.physmem.perBankWrBursts::14 6164 # Per bank write bursts +system.physmem.perBankWrBursts::15 6052 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32615126500 # Total gap between requests +system.physmem.totGap 33019298500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155899 # Read request sizes (log2) +system.physmem.readPktSize::6 145433 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 98491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97844 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,31 +148,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -197,125 +197,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads -system.physmem.totQLat 7435933847 # Total ticks spent queuing -system.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 778800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads +system.physmem.totQLat 7598607995 # Total ticks spent queuing +system.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 726600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.90 # Data bus utilization in percentage -system.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing -system.physmem.readRowHits 126861 # Number of row buffer hits during reads -system.physmem.writeRowHits 35985 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes -system.physmem.avgGap 128209.15 # Average gap between requests -system.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states -system.physmem.memoryStateTime::REF 1088880000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 352167480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 337674960 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 192154875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 184247250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 628633200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 584321400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 319101120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 318206880 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 2129849280 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 2129849280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 12060126405 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 11622718665 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 8986386750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 9370077750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 24668419110 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 24547096185 # Total energy per rank (pJ) -system.physmem.averagePower::0 756.489386 # Core power per rank (mW) -system.physmem.averagePower::1 752.768859 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 149976 # Transaction distribution -system.membus.trans_dist::ReadResp 149976 # Transaction distribution -system.membus.trans_dist::Writeback 98491 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 5923 # Transaction distribution -system.membus.trans_dist::ReadExResp 5923 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 254396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 254396 # Request fanout histogram -system.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.4 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 17209876 # Number of BP lookups -system.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7675638 # Number of BTB hits +system.physmem.busUtil 3.68 # Data bus utilization in percentage +system.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 118226 # Number of row buffer hits during reads +system.physmem.writeRowHits 36119 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes +system.physmem.avgGap 135727.17 # Average gap between requests +system.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.509165 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states +system.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ) +system.physmem_1.averagePower 748.955517 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states +system.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.branchPred.lookups 17204705 # Number of BP lookups +system.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7673903 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -337,6 +323,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -358,6 +352,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -379,6 +381,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -401,131 +411,131 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 65230431 # number of cpu cycles simulated +system.cpu.numCycles 66039009 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322461 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31532227 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32193664 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31530881 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32193949 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18671 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18665 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued @@ -551,84 +561,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94860274 # Type of FU issued -system.cpu.iq.rate 1.454233 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 94858951 # Type of FU issued +system.cpu.iq.rate 1.436408 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9866 # number of nop insts executed -system.cpu.iew.exec_refs 44709300 # number of memory reference insts executed -system.cpu.iew.exec_branches 14252629 # Number of branches executed -system.cpu.iew.exec_stores 20981511 # Number of stores executed -system.cpu.iew.exec_rate 1.440176 # Inst execution rate -system.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93464426 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44933898 # num instructions producing a value -system.cpu.iew.wb_consumers 76510027 # num instructions consuming a value +system.cpu.iew.exec_nop 9863 # number of nop insts executed +system.cpu.iew.exec_refs 44710370 # number of memory reference insts executed +system.cpu.iew.exec_branches 14251746 # Number of branches executed +system.cpu.iew.exec_stores 20982459 # Number of stores executed +system.cpu.iew.exec_rate 1.422528 # Inst execution rate +system.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93463063 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44927637 # num instructions producing a value +system.cpu.iew.wb_consumers 76497349 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.432835 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back +system.cpu.iew.wb_rate 1.415271 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 706597 1.10% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 586126 0.91% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3803876 5.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64238392 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -674,506 +684,528 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction -system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3803876 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 157213253 # The number of ROB reads -system.cpu.rob.rob_writes 195483388 # The number of ROB writes -system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 157616533 # The number of ROB reads +system.cpu.rob.rob_writes 195472136 # The number of ROB writes +system.cpu.timesIdled 23660 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 744970 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.919935 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads -system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102236524 # number of integer regfile reads -system.cpu.int_regfile_writes 56794814 # number of integer regfile writes +system.cpu.cpi 0.931339 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.931339 # CPI: Total CPI of All Threads +system.cpu.ipc 1.073723 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.073723 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102238235 # number of integer regfile reads +system.cpu.int_regfile_writes 56792997 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346002142 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804540 # number of cc regfile writes -system.cpu.misc_regfile_reads 44207937 # number of misc regfile reads +system.cpu.cc_regfile_reads 345997909 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804494 # number of cc regfile writes +system.cpu.misc_regfile_reads 44208348 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 261186 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 323466 # number of replacements -system.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323978 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.239069 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1054590000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.438944 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996951 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996951 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485280 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.769602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40441610 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485792 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.248818 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 148406000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.769602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 84635072 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84635072 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21513403 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21513403 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18834640 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18834640 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 62245 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 62245 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 40348043 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40348043 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40410288 # number of overall hits +system.cpu.dcache.overall_hits::total 40410288 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 550665 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 550665 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1015261 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1015261 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 66581 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 66581 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1565926 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1565926 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1632507 # number of overall misses +system.cpu.dcache.overall_misses::total 1632507 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8659099753 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8659099753 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14372727937 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14372727937 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4891750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4891750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23031827690 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23031827690 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23031827690 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23031827690 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 41913969 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41913969 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42042795 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42042795 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024958 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.024958 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051147 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051147 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037360 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037360 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038830 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038830 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15724.805014 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15724.805014 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14156.682801 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14156.682801 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8942.870201 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8942.870201 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14708.120109 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14708.120109 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14108.256620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14108.256620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2883834 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 127457 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.625937 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 264417 # number of writebacks +system.cpu.dcache.writebacks::total 264417 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 250985 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 250985 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866735 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 866735 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # 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Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 267 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 351 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45851126 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45851126 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22431935 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22431935 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22431935 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22431935 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22431935 # number of overall hits -system.cpu.icache.overall_hits::total 22431935 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 331634 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 331634 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 331634 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 331634 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 331634 # number of overall misses -system.cpu.icache.overall_misses::total 331634 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2861760504 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2861760504 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2861760504 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2861760504 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2861760504 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2861760504 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22763569 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22763569 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22763569 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22763569 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22763569 # 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number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 46 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14091 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.082393 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7645 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7645 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7645 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7645 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7645 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7645 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323989 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323989 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323989 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323989 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323989 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323989 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325660123 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2325660123 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325660123 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2325660123 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8733 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8733 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8733 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8733 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8733 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8733 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323391 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 3266027 # number of hwpf identified -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 304781 # number of hwpf that were already in mshr -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2719229 # number of hwpf that were already in the cache -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 25673 # number of hwpf that were already in the prefetch queue -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 17215 # number of hwpf removed because MSHR allocated -system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 199121 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2632.995635 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.700814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018430 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.103150 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.160705 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.983100 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 869 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15446 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 244 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 234 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2751 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11585 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 388 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 623 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.053040 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942749 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17367214 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17367214 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 320997 # 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Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001709 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.992004 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 17471961 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17471961 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 314144 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 305991 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 620135 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 264417 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 264417 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 137166 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137166 # 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number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 5918 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 5918 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 36526 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 38597 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 36526 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 199121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 237718 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159067500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2245450503 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2404518003 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 12215795775 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 36006 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 36006 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 395713000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 395713000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159067500 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8240 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9199 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 39322 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 48521 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9199 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 39322 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112599 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 161120 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 569300762 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2303617903 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872918665 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 11396158527 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39006 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39006 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 539005297 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 539005297 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 569300762 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2842623200 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3411923962 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 569300762 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2842623200 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14808082489 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092170 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060976 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.039835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.039835 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.047662 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055463 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059964 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.293549 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 76807.098020 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73361.555900 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73579.913798 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61348.605998 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66866.002028 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66866.002028 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72550.483276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63167.394888 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199118 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61887.244483 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74114.210894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71321.930066 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 101210.121999 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6501 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65413.264199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65413.264199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70318.500484 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 485318 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.841997 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40443714 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485830 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.246638 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 139928000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.841997 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997738 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997738 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84640426 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84640426 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21515343 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21515343 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834765 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834765 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 62288 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 62288 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15377 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15377 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40350108 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40350108 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40412396 # number of overall hits -system.cpu.dcache.overall_hits::total 40412396 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 551365 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 551365 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1015136 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1015136 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 66556 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 66556 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 549 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 549 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1566501 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1566501 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1633057 # number of overall misses -system.cpu.dcache.overall_misses::total 1633057 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8548612161 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8548612161 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13150540915 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13150540915 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5021750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5021750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 21699153076 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 21699153076 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 21699153076 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 21699153076 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22066708 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22066708 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128844 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41916609 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41916609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42045453 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42045453 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024986 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024986 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051141 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051141 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516563 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.516563 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034472 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034472 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037372 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037372 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038840 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038840 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15504.451971 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15504.451971 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12954.462176 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12954.462176 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9147.085610 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9147.085610 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13851.988014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13851.988014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13287.443779 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13287.443779 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2567726 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 127351 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.214286 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 20.162590 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 256573 # number of writebacks -system.cpu.dcache.writebacks::total 256573 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 251643 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 251643 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866615 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866615 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 549 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 549 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118258 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118258 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118258 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 169293 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 137181 # Transaction distribution +system.membus.trans_dist::ReadResp 137181 # Transaction distribution +system.membus.trans_dist::Writeback 97844 # Transaction distribution +system.membus.trans_dist::UpgradeReq 6 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 8252 # Transaction distribution +system.membus.trans_dist::ReadExResp 8252 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 243283 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 243283 # Request fanout histogram +system.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index b1db16392..23c0d1c87 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011000 # Number of ticks simulated final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264072 # Simulator instruction rate (inst/s) -host_op_rate 337712 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182321320 # Simulator tick rate (ticks/s) -host_mem_usage 304496 # Number of bytes of host memory used -host_seconds 268.54 # Real time elapsed on the host +host_inst_rate 1376675 # Simulator instruction rate (inst/s) +host_op_rate 1760576 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 950486092 # Simulator tick rate (ticks/s) +host_mem_usage 308184 # Number of bytes of host memory used +host_seconds 51.51 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,37 +35,15 @@ system.physmem.bw_write::total 1606621596 # Wr system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 100925135 # Transaction distribution -system.membus.trans_dist::ReadResp 100941054 # Transaction distribution -system.membus.trans_dist::WriteReq 19849901 # Transaction distribution -system.membus.trans_dist::WriteResp 19849901 # Transaction distribution -system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution -system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930618 # Request fanout histogram -system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram -system.membus.snoop_fanout::total 120930618 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -87,6 +65,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -108,6 +94,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -129,6 +123,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -211,5 +213,35 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction +system.membus.trans_dist::ReadReq 100925135 # Transaction distribution +system.membus.trans_dist::ReadResp 100941054 # Transaction distribution +system.membus.trans_dist::WriteReq 19849901 # Transaction distribution +system.membus.trans_dist::WriteResp 19849901 # Transaction distribution +system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution +system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution +system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 120930618 # Request fanout histogram +system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 120930618 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index baa7e0631..938385651 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.127294 # Nu sim_ticks 127293983000 # Number of ticks simulated final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 949441 # Simulator instruction rate (inst/s) -host_op_rate 1212170 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1717378261 # Simulator tick rate (ticks/s) -host_mem_usage 313972 # Number of bytes of host memory used -host_seconds 74.12 # Real time elapsed on the host +host_inst_rate 894668 # Simulator instruction rate (inst/s) +host_op_rate 1142240 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618302823 # Simulator tick rate (ticks/s) +host_mem_usage 317432 # Number of bytes of host memory used +host_seconds 78.66 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,31 +36,15 @@ system.physmem.bw_total::writebacks 42187194 # To system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 25532 # Transaction distribution -system.membus.trans_dist::ReadResp 25532 # Transaction distribution -system.membus.trans_dist::Writeback 83909 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214631 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214631 # Request fanout histogram -system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -82,6 +66,14 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -103,6 +95,14 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -124,6 +124,14 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits @@ -206,6 +214,143 @@ system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits +system.cpu.dcache.overall_hits::total 42576328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses +system.cpu.dcache.overall_misses::total 177384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks +system.cpu.dcache.writebacks::total 128239 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. @@ -439,143 +584,6 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits -system.cpu.dcache.overall_hits::total 42576328 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses -system.cpu.dcache.overall_misses::total 177384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks -system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution @@ -609,5 +617,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 28362000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 25532 # Transaction distribution +system.membus.trans_dist::ReadResp 25532 # Transaction distribution +system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214631 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214631 # Request fanout histogram +system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- |