diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm/linux')
6 files changed, 1339 insertions, 1314 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini index 802d9b780..4b3e2746a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -15,6 +15,7 @@ boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain eventq_index=0 +exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true @@ -24,6 +25,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= @@ -132,9 +134,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -148,6 +150,7 @@ system=system tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.dcache_port mem_side=system.cpu.toL2Bus.slave[1] @@ -591,9 +594,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 @@ -607,6 +610,7 @@ system=system tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 +writeback_clean=true cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.slave[0] @@ -626,6 +630,7 @@ eventq_index=0 [system.cpu.isa] type=ArmISA +decoderFlavour=Generic eventq_index=0 fpsid=1090793632 id_aa64afr0_el1=0 @@ -701,9 +706,9 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -717,6 +722,7 @@ system=system tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 +writeback_clean=false cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] @@ -732,12 +738,14 @@ size=2097152 [system.cpu.toL2Bus] type=CoherentXBar +children=snoop_filter clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 -snoop_filter=Null +snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 system=system use_default_range=false @@ -745,6 +753,13 @@ width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + [system.cpu.tracer] type=ExeTracer eventq_index=0 @@ -759,7 +774,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false @@ -794,6 +809,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr index 341b479f7..f9e2ef3b2 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr @@ -1,2 +1 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout index f97f5968b..9ad30ac44 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 14 2015 23:29:19 -gem5 started Sep 15 2015 03:05:45 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 16:24:45 +gem5 executing on dinar2c11, pid 15928 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 56986224500 because target called exit() +Exiting @ tick 56966152500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 6fa7b21e8..357735e21 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,49 +1,49 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.056961 # Number of seconds simulated -sim_ticks 56960656500 # Number of ticks simulated -final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056966 # Number of seconds simulated +sim_ticks 56966152500 # Number of ticks simulated +final_tick 56966152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189048 # Simulator instruction rate (inst/s) -host_op_rate 241764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151847358 # Simulator tick rate (ticks/s) -host_mem_usage 327812 # Number of bytes of host memory used -host_seconds 375.12 # Real time elapsed on the host -sim_insts 70915128 # Number of instructions simulated -sim_ops 90690084 # Number of ops (including micro ops) simulated +host_inst_rate 83103 # Simulator instruction rate (inst/s) +host_op_rate 106277 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66756773 # Simulator tick rate (ticks/s) +host_mem_usage 309512 # Number of bytes of host memory used +host_seconds 853.34 # Real time elapsed on the host +sim_insts 70915150 # Number of instructions simulated +sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 285184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924608 # Number of bytes read from this memory -system.physmem.bytes_read::total 8209792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory +system.physmem.bytes_read::total 8209856 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 285184 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 285184 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5517504 # Number of bytes written to this memory system.physmem.bytes_written::total 5517504 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 4456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123822 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128279 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86211 # Number of write requests responded to by this memory system.physmem.num_writes::total 86211 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5006684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 139124239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144130923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5006684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5006684 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96865176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96865176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96865176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5006684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 139124239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 240996099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128278 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 5006201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139111940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144118141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5006201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5006201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96855830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96855830 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96855830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5006201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139111940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 240973971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128279 # Number of read requests accepted system.physmem.writeReqs 86211 # Number of write requests accepted -system.physmem.readBursts 128278 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128279 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86211 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8209408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8209472 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5515712 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8209792 # Total read bytes from the system interface side +system.physmem.bytesWritten 5515584 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8209856 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -53,11 +53,11 @@ system.physmem.perBankRdBursts::1 8314 # Pe system.physmem.perBankRdBursts::2 8233 # Per bank write bursts system.physmem.perBankRdBursts::3 8140 # Per bank write bursts system.physmem.perBankRdBursts::4 8284 # Per bank write bursts -system.physmem.perBankRdBursts::5 8402 # Per bank write bursts -system.physmem.perBankRdBursts::6 8056 # Per bank write bursts +system.physmem.perBankRdBursts::5 8403 # Per bank write bursts +system.physmem.perBankRdBursts::6 8055 # Per bank write bursts system.physmem.perBankRdBursts::7 7915 # Per bank write bursts system.physmem.perBankRdBursts::8 8035 # Per bank write bursts -system.physmem.perBankRdBursts::9 7586 # Per bank write bursts +system.physmem.perBankRdBursts::9 7587 # Per bank write bursts system.physmem.perBankRdBursts::10 7763 # Per bank write bursts system.physmem.perBankRdBursts::11 7815 # Per bank write bursts system.physmem.perBankRdBursts::12 7871 # Per bank write bursts @@ -66,12 +66,12 @@ system.physmem.perBankRdBursts::14 7968 # Pe system.physmem.perBankRdBursts::15 7962 # Per bank write bursts system.physmem.perBankWrBursts::0 5394 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts -system.physmem.perBankWrBursts::2 5465 # Per bank write bursts +system.physmem.perBankWrBursts::2 5468 # Per bank write bursts system.physmem.perBankWrBursts::3 5335 # Per bank write bursts -system.physmem.perBankWrBursts::4 5367 # Per bank write bursts -system.physmem.perBankWrBursts::5 5560 # Per bank write bursts -system.physmem.perBankWrBursts::6 5259 # Per bank write bursts -system.physmem.perBankWrBursts::7 5181 # Per bank write bursts +system.physmem.perBankWrBursts::4 5366 # Per bank write bursts +system.physmem.perBankWrBursts::5 5559 # Per bank write bursts +system.physmem.perBankWrBursts::6 5257 # Per bank write bursts +system.physmem.perBankWrBursts::7 5180 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts system.physmem.perBankWrBursts::9 5101 # Per bank write bursts system.physmem.perBankWrBursts::10 5292 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 5703 # Pe system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56960624500 # Total gap between requests +system.physmem.totGap 56966120500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128278 # Read request sizes (log2) +system.physmem.readPktSize::6 128279 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86211 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116041 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5446 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 5300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,98 +193,101 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 353.305769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 214.370646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.820424 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12327 31.74% 31.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8308 21.39% 53.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4009 10.32% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2908 7.49% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2579 6.64% 77.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1645 4.23% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1295 3.33% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1183 3.05% 88.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4589 11.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38843 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5293 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.231438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.038332 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5291 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.679870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.740030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.847890 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12299 31.70% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8268 21.31% 53.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4108 10.59% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2801 7.22% 70.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2598 6.70% 77.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1655 4.27% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1337 3.45% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1145 2.95% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4592 11.83% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.235639 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.487123 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5289 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5293 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5293 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.282449 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.265601 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.771117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4623 87.34% 87.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.11% 87.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 534 10.09% 97.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 111 2.10% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 13 0.25% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5293 # Writes before turning the bus around for reads -system.physmem.totQLat 1678352000 # Total ticks spent queuing -system.physmem.totMemAccLat 4083452000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 641360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13084.32 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.285147 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.266957 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.809216 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4635 87.59% 87.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.11% 87.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 507 9.58% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 117 2.21% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 17 0.32% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads +system.physmem.totQLat 1670425750 # Total ticks spent queuing +system.physmem.totMemAccLat 4075544500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 641365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13022.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31834.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.83 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31772.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.12 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.88 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing -system.physmem.readRowHits 111810 # Number of row buffer hits during reads -system.physmem.writeRowHits 63793 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 265564.32 # Average gap between requests -system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 509862600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11565367830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24028947750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40340244195 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.261877 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39847901500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1901900000 # Time in different power states +system.physmem.avgWrQLen 23.35 # Average write queue length when enqueuing +system.physmem.readRowHits 111858 # Number of row buffer hits during reads +system.physmem.writeRowHits 63787 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.20 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes +system.physmem.avgGap 265588.70 # Average gap between requests +system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 152953920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83457000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 510065400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 279210240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3720624960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11616680655 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23988608250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40351600425 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.364424 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39782190750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1902160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15206891000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15280128000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140419440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76617750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 490214400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 140358960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76584750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3720116400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10938128715 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24579157500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40223793165 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.217322 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40763292250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1901900000 # Time in different power states +system.physmem_1.refreshEnergy 3720624960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10974085740 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24552288000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40233397170 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.289389 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40717988750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1902160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14291603250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14344414250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14800638 # Number of BP lookups -system.cpu.branchPred.condPredicted 9905777 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381686 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9438449 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6732187 # Number of BTB hits +system.cpu.branchPred.lookups 14806373 # Number of BP lookups +system.cpu.branchPred.condPredicted 9910083 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 383814 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9538678 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6734058 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.327259 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1714133 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.597393 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1715002 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,97 +407,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 113921313 # number of cpu cycles simulated +system.cpu.numCycles 113932305 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70915128 # Number of instructions committed -system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144928 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 70915150 # Number of instructions committed +system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1148486 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.606446 # CPI: cycles per instruction -system.cpu.ipc 0.622492 # IPC: instructions per cycle -system.cpu.tickCycles 95595424 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18325889 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156436 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.127430 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42624259 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160532 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.518769 # Average number of references to valid blocks. +system.cpu.cpi 1.606600 # CPI: cycles per instruction +system.cpu.ipc 0.622432 # IPC: instructions per cycle +system.cpu.tickCycles 95622082 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18310223 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156441 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.130215 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42625643 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160537 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.519120 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 822760500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127430 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.130215 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992952 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1105 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2947 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1097 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2955 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86016734 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86016734 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22866824 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22866824 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642179 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642179 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83418 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83418 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86019473 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86019473 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22868200 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22868200 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83417 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83417 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42509003 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42509003 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42592421 # number of overall hits -system.cpu.dcache.overall_hits::total 42592421 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51533 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51533 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207722 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207722 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44587 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44587 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259255 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259255 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 303842 # number of overall misses -system.cpu.dcache.overall_misses::total 303842 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489955500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1489955500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16807631000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16807631000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18297586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18297586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18297586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18297586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42510388 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42510388 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42593805 # number of overall hits +system.cpu.dcache.overall_hits::total 42593805 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51522 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51522 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44590 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44590 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303825 # number of overall misses +system.cpu.dcache.overall_misses::total 303825 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1488627000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1488627000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16793358000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16793358000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18281985000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18281985000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18281985000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18281985000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22919722 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22919722 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128007 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128007 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348322 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.348322 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses +system.cpu.dcache.demand_accesses::cpu.data 42769623 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42769623 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42897630 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42897630 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002248 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002248 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348340 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348340 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006061 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006061 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28912.648206 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28912.648206 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80914.063027 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80914.063027 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70577.564560 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70577.564560 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60220.728207 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60220.728207 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28893.035985 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28893.035985 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80848.853948 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80848.853948 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70522.826779 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70522.826779 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60172.747470 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60172.747470 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,110 +506,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128377 # number of writebacks -system.cpu.dcache.writebacks::total 128377 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22014 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22014 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100694 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100694 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122708 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122708 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122708 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122708 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29519 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29519 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128384 # number of writebacks +system.cpu.dcache.writebacks::total 128384 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22002 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22002 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100685 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100685 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122687 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122687 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122687 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122687 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29520 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29520 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136547 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136547 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 577658500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 577658500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488450500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488450500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1712416500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1712416500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066109000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9066109000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10778525500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10778525500 # number of overall MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23989 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23989 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136548 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136548 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160537 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160537 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 575604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 575604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8480832000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8480832000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713530500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713530500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9056436000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9056436000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10769966500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10769966500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187404 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187404 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19569.040279 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19569.040279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79310.558919 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79310.558919 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71395.309568 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71395.309568 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66395.519491 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66395.519491 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67142.535445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67142.535445 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19498.780488 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19498.780488 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79239.376612 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79239.376612 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71429.842845 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71429.842845 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66324.193690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66324.193690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67087.129447 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67087.129447 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42868 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.481887 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24941232 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44910 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.360321 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42871 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.494475 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24951243 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44913 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.546123 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.481887 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904532 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904532 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.494475 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904538 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 917 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50017196 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50017196 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24941232 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24941232 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24941232 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24941232 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24941232 # number of overall hits -system.cpu.icache.overall_hits::total 24941232 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44911 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44911 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44911 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44911 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44911 # number of overall misses -system.cpu.icache.overall_misses::total 44911 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 896725000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 896725000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 896725000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 896725000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 896725000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 896725000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24986143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24986143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24986143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24986143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24986143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24986143 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 50037227 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50037227 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24951243 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24951243 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24951243 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24951243 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24951243 # number of overall hits +system.cpu.icache.overall_hits::total 24951243 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44914 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44914 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44914 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44914 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44914 # number of overall misses +system.cpu.icache.overall_misses::total 44914 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 896931500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 896931500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 896931500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 896931500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 896931500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 896931500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24996157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24996157 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24996157 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24996157 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24996157 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24996157 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001797 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001797 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001797 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001797 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001797 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001797 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19966.711941 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19966.711941 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19966.711941 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19966.711941 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19966.711941 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19969.975954 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19969.975954 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19969.975954 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19969.975954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19969.975954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19969.975954 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,135 +618,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 42868 # number of writebacks -system.cpu.icache.writebacks::total 42868 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44911 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44911 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44911 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44911 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44911 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44911 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 851815000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 851815000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 851815000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 851815000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 851815000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 851815000 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 42871 # number of writebacks +system.cpu.icache.writebacks::total 42871 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44914 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44914 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44914 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44914 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44914 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 852018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 852018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 852018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 852018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 852018500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 852018500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001797 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001797 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001797 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001797 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18966.734208 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18966.734208 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18966.734208 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18966.734208 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18969.998219 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18969.998219 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18969.998219 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18969.998219 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18969.998219 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18969.998219 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96386 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29871.418055 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 162162 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127539 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.271470 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 96387 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29871.556792 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 162176 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127540 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.271570 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26782.423909 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.670582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1657.323564 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.817335 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043691 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050578 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.911603 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26781.739932 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1431.627084 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1658.189777 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.817314 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043690 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.050604 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911608 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1851 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12724 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15788 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 593 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1857 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12727 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15784 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 594 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3410031 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3410031 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 128377 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128377 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 39288 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 39288 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 40441 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 40441 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31897 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31897 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 40441 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36648 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77089 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 40441 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36648 # number of overall hits -system.cpu.l2cache.overall_hits::total 77089 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102277 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102277 # number of ReadExReq misses +system.cpu.l2cache.tags.tag_accesses 3410152 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3410152 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 128384 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 128384 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 39291 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 39291 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 40444 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 40444 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31900 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 31900 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 40444 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36652 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 77096 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 40444 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36652 # number of overall hits +system.cpu.l2cache.overall_hits::total 77096 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 102276 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102276 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4470 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 4470 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21607 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21607 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21609 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 21609 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 4470 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123884 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128354 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128355 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 4470 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123884 # number of overall misses -system.cpu.l2cache.overall_misses::total 128354 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8277973500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8277973500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 355961000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 355961000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1870485000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1870485000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 355961000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10148458500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10504419500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 355961000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10148458500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10504419500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 128377 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 128377 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 39288 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 39288 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses +system.cpu.l2cache.overall_misses::total 128355 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8270346500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8270346500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356128000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 356128000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1869505500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1869505500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 356128000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10139852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10495980000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 356128000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10139852000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10495980000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 128384 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 128384 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 39291 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 39291 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107028 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107028 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44911 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 44911 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53504 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 53504 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 44911 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 160532 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 205443 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 44911 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 160532 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 205443 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955610 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955610 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099530 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099530 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 44914 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 44914 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53509 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 53509 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 44914 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160537 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44914 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160537 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955600 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955600 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.099524 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.099524 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403839 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403839 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099530 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771709 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.624767 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099530 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771709 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.624767 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80936.803974 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80936.803974 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79633.333333 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79633.333333 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86568.473180 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86568.473180 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81839.440142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79633.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81919.041200 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81839.440142 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099524 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771691 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.624748 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099524 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771691 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.624748 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80863.022605 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80863.022605 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79670.693512 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79670.693512 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86515.132584 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86515.132584 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79670.693512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81848.908262 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81773.051303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79670.693512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81848.908262 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81773.051303 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,119 +769,119 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 62 system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102277 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102276 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102276 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4457 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4457 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21545 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21545 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21547 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21547 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 4457 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123822 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128280 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 4457 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123822 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128279 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7255203500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7255203500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310493500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310493500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649955000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649955000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310493500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8905158500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9215652000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310493500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8905158500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9215652000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128280 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7247586500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7247586500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310540000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310540000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1649696000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1649696000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310540000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8897282500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9207822500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310540000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8897282500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9207822500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955610 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955610 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099241 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099234 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402680 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402680 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.624402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099241 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771323 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.624402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70936.803974 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70936.803974 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69664.236033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69664.236033 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76581.805523 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76581.805523 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69664.236033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71919.032967 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71840.690994 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771305 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.624382 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099234 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771305 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.624382 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70863.022605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70863.022605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69674.669060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69674.669060 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76562.676939 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76562.676939 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69674.669060 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71854.845223 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71779.096508 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69674.669060 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71854.845223 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71779.096508 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 404747 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 199340 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7814 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 404763 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 199348 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7815 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3362 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 42868 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 42871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38233 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132689 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477500 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 610189 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5617792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24107968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 96386 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.189864 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 44914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53509 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132698 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477515 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 610213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5618176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24109120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 96387 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 301838 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037245 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.189869 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 290617 96.29% 96.29% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11183 3.71% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 290625 96.29% 96.29% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11184 3.71% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 301829 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 373618500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 301838 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 373636500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67384461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67388961 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240832431 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240839931 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 26001 # Transaction distribution +system.membus.trans_dist::ReadResp 26003 # Transaction distribution system.membus.trans_dist::WritebackDirty 86211 # Transaction distribution -system.membus.trans_dist::CleanEvict 6908 # Transaction distribution -system.membus.trans_dist::ReadExReq 102277 # Transaction distribution -system.membus.trans_dist::ReadExResp 102277 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26001 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349675 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 349675 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13727296 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 6909 # Transaction distribution +system.membus.trans_dist::ReadExReq 102276 # Transaction distribution +system.membus.trans_dist::ReadExResp 102276 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26003 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349678 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 349678 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13727360 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 221397 # Request fanout histogram +system.membus.snoop_fanout::samples 221399 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 221397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 221399 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 221397 # Request fanout histogram -system.membus.reqLayer0.occupancy 590585500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 221399 # Request fanout histogram +system.membus.reqLayer0.occupancy 590619000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 676907000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 676896750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 84fd6d051..afe952dfb 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 19:53:43 -gem5 started Mar 15 2016 20:46:50 -gem5 executing on dinar2c11, pid 11157 +gem5 compiled Mar 16 2016 15:51:04 +gem5 started Mar 16 2016 17:20:18 +gem5 executing on dinar2c11, pid 17075 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 33784139000 because target called exit() +Exiting @ tick 33708718000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index cb62ae8cf..7ec2ce465 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033784 # Number of seconds simulated -sim_ticks 33784139000 # Number of ticks simulated -final_tick 33784139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033709 # Number of seconds simulated +sim_ticks 33708718000 # Number of ticks simulated +final_tick 33708718000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59206 # Simulator instruction rate (inst/s) -host_op_rate 75718 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28209032 # Simulator tick rate (ticks/s) -host_mem_usage 312216 # Number of bytes of host memory used -host_seconds 1197.64 # Real time elapsed on the host -sim_insts 70907630 # Number of instructions simulated -sim_ops 90682585 # Number of ops (including micro ops) simulated +host_inst_rate 58097 # Simulator instruction rate (inst/s) +host_op_rate 74299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27618733 # Simulator tick rate (ticks/s) +host_mem_usage 312228 # Number of bytes of host memory used +host_seconds 1220.50 # Real time elapsed on the host +sim_insts 70907652 # Number of instructions simulated +sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 781248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2836288 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6167232 # Number of bytes read from this memory -system.physmem.bytes_read::total 9784768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 781248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 781248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6226432 # Number of bytes written to this memory -system.physmem.bytes_written::total 6226432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 12207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 44317 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96363 # Number of read requests responded to by this memory -system.physmem.num_reads::total 152887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97288 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97288 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 23124698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 83953242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 182548148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 289626088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 23124698 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 23124698 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 184300449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 184300449 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 184300449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 23124698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 83953242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 182548148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 473926537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 152888 # Number of read requests accepted -system.physmem.writeReqs 97288 # Number of write requests accepted -system.physmem.readBursts 152888 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97288 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9777152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 6224960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9784832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6226432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 642112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2851904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6180288 # Number of bytes read from this memory +system.physmem.bytes_read::total 9674304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 642112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 642112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6216192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6216192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 44561 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96567 # Number of read requests responded to by this memory +system.physmem.num_reads::total 151161 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97128 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97128 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19048841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 84604345 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 183343905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 286997091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19048841 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19048841 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 184409030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 184409030 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 184409030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19048841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 84604345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 183343905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 471406121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 151162 # Number of read requests accepted +system.physmem.writeReqs 97128 # Number of write requests accepted +system.physmem.readBursts 151162 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97128 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9665216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue +system.physmem.bytesWritten 6214528 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9674368 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6216192 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9124 # Per bank write bursts -system.physmem.perBankRdBursts::1 9348 # Per bank write bursts -system.physmem.perBankRdBursts::2 9757 # Per bank write bursts -system.physmem.perBankRdBursts::3 12566 # Per bank write bursts -system.physmem.perBankRdBursts::4 10929 # Per bank write bursts -system.physmem.perBankRdBursts::5 10090 # Per bank write bursts -system.physmem.perBankRdBursts::6 9786 # Per bank write bursts -system.physmem.perBankRdBursts::7 8974 # Per bank write bursts -system.physmem.perBankRdBursts::8 9178 # Per bank write bursts -system.physmem.perBankRdBursts::9 9832 # Per bank write bursts -system.physmem.perBankRdBursts::10 9165 # Per bank write bursts -system.physmem.perBankRdBursts::11 8819 # Per bank write bursts -system.physmem.perBankRdBursts::12 8693 # Per bank write bursts -system.physmem.perBankRdBursts::13 8672 # Per bank write bursts -system.physmem.perBankRdBursts::14 8813 # Per bank write bursts -system.physmem.perBankRdBursts::15 9022 # Per bank write bursts -system.physmem.perBankWrBursts::0 5950 # Per bank write bursts -system.physmem.perBankWrBursts::1 6192 # Per bank write bursts -system.physmem.perBankWrBursts::2 6162 # Per bank write bursts -system.physmem.perBankWrBursts::3 6171 # Per bank write bursts -system.physmem.perBankWrBursts::4 6089 # Per bank write bursts -system.physmem.perBankWrBursts::5 6262 # Per bank write bursts -system.physmem.perBankWrBursts::6 6013 # Per bank write bursts -system.physmem.perBankWrBursts::7 5971 # Per bank write bursts -system.physmem.perBankWrBursts::8 5978 # Per bank write bursts -system.physmem.perBankWrBursts::9 6080 # Per bank write bursts -system.physmem.perBankWrBursts::10 6215 # Per bank write bursts -system.physmem.perBankWrBursts::11 5915 # Per bank write bursts -system.physmem.perBankWrBursts::12 6050 # Per bank write bursts -system.physmem.perBankWrBursts::13 6057 # Per bank write bursts -system.physmem.perBankWrBursts::14 6142 # Per bank write bursts -system.physmem.perBankWrBursts::15 6018 # Per bank write bursts +system.physmem.perBankRdBursts::0 9070 # Per bank write bursts +system.physmem.perBankRdBursts::1 9361 # Per bank write bursts +system.physmem.perBankRdBursts::2 9561 # Per bank write bursts +system.physmem.perBankRdBursts::3 11292 # Per bank write bursts +system.physmem.perBankRdBursts::4 10590 # Per bank write bursts +system.physmem.perBankRdBursts::5 10416 # Per bank write bursts +system.physmem.perBankRdBursts::6 9949 # Per bank write bursts +system.physmem.perBankRdBursts::7 8975 # Per bank write bursts +system.physmem.perBankRdBursts::8 9423 # Per bank write bursts +system.physmem.perBankRdBursts::9 9187 # Per bank write bursts +system.physmem.perBankRdBursts::10 9162 # Per bank write bursts +system.physmem.perBankRdBursts::11 8879 # Per bank write bursts +system.physmem.perBankRdBursts::12 8652 # Per bank write bursts +system.physmem.perBankRdBursts::13 8689 # Per bank write bursts +system.physmem.perBankRdBursts::14 8733 # Per bank write bursts +system.physmem.perBankRdBursts::15 9080 # Per bank write bursts +system.physmem.perBankWrBursts::0 5971 # Per bank write bursts +system.physmem.perBankWrBursts::1 6177 # Per bank write bursts +system.physmem.perBankWrBursts::2 6109 # Per bank write bursts +system.physmem.perBankWrBursts::3 6172 # Per bank write bursts +system.physmem.perBankWrBursts::4 6049 # Per bank write bursts +system.physmem.perBankWrBursts::5 6259 # Per bank write bursts +system.physmem.perBankWrBursts::6 6017 # Per bank write bursts +system.physmem.perBankWrBursts::7 5953 # Per bank write bursts +system.physmem.perBankWrBursts::8 5939 # Per bank write bursts +system.physmem.perBankWrBursts::9 6100 # Per bank write bursts +system.physmem.perBankWrBursts::10 6208 # Per bank write bursts +system.physmem.perBankWrBursts::11 5866 # Per bank write bursts +system.physmem.perBankWrBursts::12 6052 # Per bank write bursts +system.physmem.perBankWrBursts::13 6067 # Per bank write bursts +system.physmem.perBankWrBursts::14 6159 # Per bank write bursts +system.physmem.perBankWrBursts::15 6004 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33784127500 # Total gap between requests +system.physmem.totGap 33708706500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152888 # Read request sizes (log2) +system.physmem.readPktSize::6 151162 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97288 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 50168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97128 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 48274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54259 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -148,33 +148,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -197,98 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95539 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 167.474225 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 105.587098 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 235.887781 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59486 62.26% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22475 23.52% 85.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4141 4.33% 90.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1560 1.63% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 915 0.96% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 855 0.89% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 603 0.63% 94.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 793 0.83% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4711 4.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95539 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5851 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.107332 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.473486 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5850 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 94915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 167.290734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 105.391717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 236.347458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59184 62.35% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22349 23.55% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4070 4.29% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1460 1.54% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 942 0.99% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 824 0.87% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 583 0.61% 94.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 753 0.79% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4750 5.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94915 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5848 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.821990 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.480384 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5847 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5851 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5851 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.623654 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.576655 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.320793 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4551 77.78% 77.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.51% 78.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 752 12.85% 91.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 225 3.85% 94.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 138 2.36% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 80 1.37% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 45 0.77% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.38% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.14% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5851 # Writes before turning the bus around for reads -system.physmem.totQLat 6694958033 # Total ticks spent queuing -system.physmem.totMemAccLat 9559358033 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 763840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43824.35 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5848 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5848 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.604309 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.557483 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.326112 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4590 78.49% 78.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 34 0.58% 79.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 732 12.52% 91.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 206 3.52% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 140 2.39% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 85 1.45% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 32 0.55% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 13 0.22% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.09% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 7 0.12% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5848 # Writes before turning the bus around for reads +system.physmem.totQLat 6766168330 # Total ticks spent queuing +system.physmem.totMemAccLat 9597774580 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 755095000 # Total ticks spent in databus transfers +system.physmem.avgQLat 44803.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62574.35 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 289.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 184.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 289.63 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 184.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 63553.42 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 286.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 184.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 287.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 184.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.70 # Data bus utilization in percentage -system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.68 # Data bus utilization in percentage +system.physmem.busUtilRead 2.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 121417 # Number of row buffer hits during reads -system.physmem.writeRowHits 33065 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 33.99 # Row buffer hit rate for writes -system.physmem.avgGap 135041.44 # Average gap between requests -system.physmem.pageHitRate 61.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 374855040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204534000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 627829800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 316068480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15176758725 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6953261250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25859440575 # Total energy per rank (pJ) -system.physmem_0.averagePower 765.592889 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11461051997 # Time in different power states -system.physmem_0.memoryStateTime::REF 1127880000 # Time in different power states +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.44 # Average write queue length when enqueuing +system.physmem.readRowHits 120218 # Number of row buffer hits during reads +system.physmem.writeRowHits 32977 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.95 # Row buffer hit rate for writes +system.physmem.avgGap 135763.45 # Average gap between requests +system.physmem.pageHitRate 61.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 372428280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 203209875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 617682000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 315563040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2201556240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14512366440 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7494015750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25716821625 # Total energy per rank (pJ) +system.physmem_0.averagePower 762.953400 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12364292410 # Time in different power states +system.physmem_0.memoryStateTime::REF 1125540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21188094253 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20217117590 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 346777200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 189213750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562754400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313787520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13818315060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8144878500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25581859710 # Total energy per rank (pJ) -system.physmem_1.averagePower 757.374848 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13453093141 # Time in different power states -system.physmem_1.memoryStateTime::REF 1127880000 # Time in different power states +system.physmem_1.actEnergy 345038400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 188265000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 559977600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313554240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2201556240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13559944320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8329473750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25497809550 # Total energy per rank (pJ) +system.physmem_1.averagePower 756.455863 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13760038430 # Time in different power states +system.physmem_1.memoryStateTime::REF 1125540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19196289859 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18821462070 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17214384 # Number of BP lookups -system.cpu.branchPred.condPredicted 11522342 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 650449 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9351216 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7679376 # Number of BTB hits +system.cpu.branchPred.lookups 17213709 # Number of BP lookups +system.cpu.branchPred.condPredicted 11523003 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 650148 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9341134 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7678896 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.121683 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872997 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 82.205180 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872990 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -408,95 +413,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 67568279 # number of cpu cycles simulated +system.cpu.numCycles 67417437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5160872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88245051 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17214384 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9552373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60651743 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1327287 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6028 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5107349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88247579 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17213709 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9551886 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60722717 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1326923 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12780 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22780660 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69845 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66495093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.679326 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300807 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 12869 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22781060 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69770 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66511361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.678949 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300919 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20690371 31.12% 31.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8267529 12.43% 43.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9212157 13.85% 57.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28325036 42.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20706181 31.13% 31.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8267608 12.43% 43.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9211127 13.85% 57.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28326445 42.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66495093 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.306013 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8713541 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20066003 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31587262 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5634718 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 493569 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3182821 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172049 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101434518 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3052676 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 493569 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13478922 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5884192 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 838725 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32239032 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13560653 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99228097 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 981180 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3845119 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69162 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4384146 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5165586 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103939784 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457840373 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115445962 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 66511361 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.255330 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.308973 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8663293 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20135580 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31585821 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5633203 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 493464 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3182521 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171963 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101430430 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3050546 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 493464 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13424917 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5969682 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 834240 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32240480 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13548578 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99223336 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 980873 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3826325 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 67087 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4382425 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5163178 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103933922 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457817395 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115439825 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10310558 # Number of HB maps that are undone due to squashing +system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 10304553 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 18670 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12730367 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24327975 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22005134 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1415958 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2369050 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98190630 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34517 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94916965 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 695759 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7542562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20296667 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66495093 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.427428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151996 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 18666 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12721444 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24327620 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22002844 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1418421 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2362163 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98185716 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34529 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94914966 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694952 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7537638 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20282691 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66511361 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.427049 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.152183 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18174968 27.33% 27.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17486428 26.30% 53.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17117325 25.74% 79.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11670567 17.55% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2044839 3.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 966 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18195190 27.36% 27.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17483152 26.29% 53.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17116175 25.73% 79.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11668879 17.54% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2046998 3.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 967 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66495093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66511361 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6711532 22.43% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 41 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6715190 22.43% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 42 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.43% # attempts to use FU when none available @@ -524,13 +529,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.43% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.43% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11180045 37.36% 59.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12034310 40.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11181767 37.35% 59.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12039186 40.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49505832 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89861 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49504183 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89872 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -558,94 +563,94 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24073706 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21247526 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24074068 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21246803 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94916965 # Type of FU issued -system.cpu.iq.rate 1.404756 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29925928 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315285 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286950501 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105779157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93480434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94914966 # Type of FU issued +system.cpu.iq.rate 1.407870 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29936185 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315400 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286972221 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105769455 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93478190 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124842774 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124851032 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1366701 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1366282 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1461713 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2105 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11942 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1449396 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1461358 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2098 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12063 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1447106 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 140491 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185859 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 140885 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185939 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 493569 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 630289 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 523749 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98235038 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 493464 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 630348 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 519071 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98230120 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24327975 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22005134 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18597 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1652 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 519239 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11942 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303965 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221737 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 525702 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93996105 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23765772 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 920860 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24327620 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22002844 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18609 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1657 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 514382 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12063 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303781 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221600 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 525381 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93994405 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23766194 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 920561 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9891 # number of nop insts executed -system.cpu.iew.exec_refs 44755693 # number of memory reference insts executed -system.cpu.iew.exec_branches 14254152 # Number of branches executed -system.cpu.iew.exec_stores 20989921 # Number of stores executed -system.cpu.iew.exec_rate 1.391128 # Inst execution rate -system.cpu.iew.wb_sent 93602702 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93480493 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44980132 # num instructions producing a value -system.cpu.iew.wb_consumers 76556790 # num instructions consuming a value -system.cpu.iew.wb_rate 1.383497 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587539 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6559945 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9875 # number of nop insts executed +system.cpu.iew.exec_refs 44755394 # number of memory reference insts executed +system.cpu.iew.exec_branches 14253394 # Number of branches executed +system.cpu.iew.exec_stores 20989200 # Number of stores executed +system.cpu.iew.exec_rate 1.394215 # Inst execution rate +system.cpu.iew.wb_sent 93600457 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93478249 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44984526 # num instructions producing a value +system.cpu.iew.wb_consumers 76573166 # num instructions consuming a value +system.cpu.iew.wb_rate 1.386559 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587471 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6555355 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 480375 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65432608 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.385978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157554 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 480151 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65449475 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.385621 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157530 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31819625 48.63% 48.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16816004 25.70% 74.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4349451 6.65% 80.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4164400 6.36% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1932309 2.95% 90.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1260445 1.93% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 747040 1.14% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580342 0.89% 94.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3762992 5.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31837500 48.64% 48.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16816023 25.69% 74.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4347616 6.64% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4166544 6.37% 87.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1933514 2.95% 90.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1257718 1.92% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 744905 1.14% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580044 0.89% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3765611 5.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65432608 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70913182 # Number of instructions committed -system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 65449475 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70913204 # Number of instructions committed +system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 43422000 # Number of memory references committed system.cpu.commit.loads 22866262 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13741486 # Number of branches committed +system.cpu.commit.branches 13741468 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. +system.cpu.commit.int_insts 81528527 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47186011 52.03% 52.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47186033 52.03% 52.03% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction @@ -678,387 +683,389 @@ system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Cl system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3762992 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158892399 # The number of ROB reads -system.cpu.rob.rob_writes 195560325 # The number of ROB writes -system.cpu.timesIdled 28658 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1073186 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70907630 # Number of Instructions Simulated -system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.952906 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.952906 # CPI: Total CPI of All Threads -system.cpu.ipc 1.049422 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049422 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102292438 # number of integer regfile reads -system.cpu.int_regfile_writes 56802415 # number of integer regfile writes +system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction +system.cpu.commit.bw_lim_events 3765611 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158902079 # The number of ROB reads +system.cpu.rob.rob_writes 195550630 # The number of ROB writes +system.cpu.timesIdled 26501 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 906076 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70907652 # Number of Instructions Simulated +system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.950778 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.950778 # CPI: Total CPI of All Threads +system.cpu.ipc 1.051770 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.051770 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102290676 # number of integer regfile reads +system.cpu.int_regfile_writes 56801575 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads system.cpu.fp_regfile_writes 22 # number of floating regfile writes -system.cpu.cc_regfile_reads 346166780 # number of cc regfile reads -system.cpu.cc_regfile_writes 38809001 # number of cc regfile writes -system.cpu.misc_regfile_reads 44218310 # number of misc regfile reads +system.cpu.cc_regfile_reads 346161860 # number of cc regfile reads +system.cpu.cc_regfile_writes 38808202 # number of cc regfile writes +system.cpu.misc_regfile_reads 44217642 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485025 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.752435 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40412261 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485537 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.232094 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 485010 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.749644 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40413326 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485522 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.236858 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.752435 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997563 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997563 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 510.749644 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997558 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997558 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 455 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84614979 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84614979 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21489272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21489272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831416 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831416 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60267 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60267 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15347 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15347 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84616114 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84616114 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21490425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21490425 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831304 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831304 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60283 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60283 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15350 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15350 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40320688 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40320688 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40380955 # number of overall hits -system.cpu.dcache.overall_hits::total 40380955 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 564863 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 564863 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018485 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018485 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68573 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68573 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 579 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 579 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1583348 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1583348 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1651921 # number of overall misses -system.cpu.dcache.overall_misses::total 1651921 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9285321000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9285321000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14250906929 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14250906929 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5341000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5341000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23536227929 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23536227929 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23536227929 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23536227929 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40321729 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40321729 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40382012 # number of overall hits +system.cpu.dcache.overall_hits::total 40382012 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 564289 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 564289 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018597 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018597 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68553 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68553 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 576 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 576 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1582886 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1582886 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1651439 # number of overall misses +system.cpu.dcache.overall_misses::total 1651439 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9271463500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9271463500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14268416431 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14268416431 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5543500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5543500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23539879931 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23539879931 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23539879931 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23539879931 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054714 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054714 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128840 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128840 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128836 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128836 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904036 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904036 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42032876 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42032876 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025613 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025613 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051309 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532234 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532234 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036356 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036356 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037785 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037785 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039301 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039301 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16438.182356 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16438.182356 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13992.260003 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13992.260003 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9224.525043 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9224.525043 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14864.848365 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14864.848365 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14247.792678 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14247.792678 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 81 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2899485 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904615 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904615 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033451 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033451 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025586 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025586 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051315 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051315 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532095 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532095 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036167 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037774 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037774 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039289 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039289 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16430.345975 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16430.345975 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14007.911304 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14007.911304 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9624.131944 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9624.131944 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14871.494176 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14871.494176 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14254.162540 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14254.162540 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2905402 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131229 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.363636 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.094849 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 131245 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.727273 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.137240 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 485025 # number of writebacks -system.cpu.dcache.writebacks::total 485025 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265446 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 265446 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 869952 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 869952 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 579 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 579 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135398 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135398 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135398 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135398 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447950 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447950 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485547 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3589129000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3589129000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306203970 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306203970 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1890576000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1890576000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5895332970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5895332970 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7785908970 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7785908970 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 485010 # number of writebacks +system.cpu.dcache.writebacks::total 485010 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264882 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 264882 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870061 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870061 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 576 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1134943 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1134943 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1134943 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1134943 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299407 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299407 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148536 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148536 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37590 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37590 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447943 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447943 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485533 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485533 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3623952500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3623952500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306335972 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306335972 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1883780500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1883780500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5930288472 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5930288472 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7814068972 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7814068972 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291812 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291766 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291766 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11987.058183 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11987.058183 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15526.542721 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15526.542721 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50285.288720 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50285.288720 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13160.694207 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13160.694207 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16035.335343 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16035.335343 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.766779 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.766779 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15527.117817 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15527.117817 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50113.873371 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50113.873371 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13238.935472 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13238.935472 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16093.795833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16093.795833 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 323129 # number of replacements -system.cpu.icache.tags.tagsinuse 510.280955 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22445799 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323641 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.354003 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.280955 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996642 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996642 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 322968 # number of replacements +system.cpu.icache.tags.tagsinuse 510.276903 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22446876 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323480 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.391851 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1134274500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.276903 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996635 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996635 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 335 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 338 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45884745 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45884745 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22445799 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22445799 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22445799 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22445799 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22445799 # number of overall hits -system.cpu.icache.overall_hits::total 22445799 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 334748 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 334748 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 334748 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 334748 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 334748 # number of overall misses -system.cpu.icache.overall_misses::total 334748 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3612917411 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3612917411 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3612917411 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3612917411 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3612917411 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3612917411 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22780547 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22780547 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22780547 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22780547 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22780547 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22780547 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014694 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014694 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014694 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014694 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014694 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014694 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10792.946966 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10792.946966 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10792.946966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10792.946966 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10792.946966 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 264495 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45885393 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45885393 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22446876 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22446876 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22446876 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22446876 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22446876 # number of overall hits +system.cpu.icache.overall_hits::total 22446876 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334075 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334075 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334075 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334075 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334075 # number of overall misses +system.cpu.icache.overall_misses::total 334075 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3448429403 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3448429403 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3448429403 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3448429403 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3448429403 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3448429403 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22780951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22780951 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22780951 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22780951 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22780951 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22780951 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014665 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014665 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014665 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014665 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014665 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014665 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10322.321045 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10322.321045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10322.321045 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10322.321045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10322.321045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10322.321045 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 262312 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 50 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16626 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16368 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 15.908517 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.025904 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 323129 # number of writebacks -system.cpu.icache.writebacks::total 323129 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11096 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11096 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11096 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 11096 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 11096 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 11096 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323652 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323652 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323652 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323652 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323652 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323652 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3313255946 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 3313255946 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3313255946 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 3313255946 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3313255946 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 3313255946 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014207 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014207 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014207 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014207 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10237.093996 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10237.093996 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10237.093996 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10237.093996 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 322968 # number of writebacks +system.cpu.icache.writebacks::total 322968 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10583 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 10583 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 10583 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 10583 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 10583 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 10583 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323492 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323492 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323492 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323492 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323492 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323492 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3173672438 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 3173672438 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3173672438 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3173672438 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3173672438 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3173672438 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014200 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014200 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9810.667460 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9810.667460 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9810.667460 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9810.667460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9810.667460 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9810.667460 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 821921 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825508 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 3147 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 822850 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826406 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 3117 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78532 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 128137 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15990.250829 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1182553 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 144496 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.183984 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78938 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 127914 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15989.309751 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1181667 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 144275 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.190379 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15899.758864 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 90.491965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.970444 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005523 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.975967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 33 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16326 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15893.511070 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 95.798681 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.970063 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005847 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.975910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 28 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16333 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 17 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2752 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 551 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 772 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002014 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996460 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 24991467 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 24991467 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 256728 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 256728 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 471596 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 471596 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137032 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137032 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 311398 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 311398 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300922 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 300922 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 311398 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 437954 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 749352 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 311398 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 437954 # number of overall hits -system.cpu.l2cache.overall_hits::total 749352 # number of overall hits +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2736 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12138 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 528 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 795 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001709 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996887 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 24987971 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 24987971 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 259400 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 259400 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 468713 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 468713 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 137243 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137243 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 313417 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 313417 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300447 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 300447 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 313417 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 437690 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 751107 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 313417 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 437690 # number of overall hits +system.cpu.l2cache.overall_hits::total 751107 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11535 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11535 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12242 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 12242 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36048 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 36048 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 12242 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 47583 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 59825 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 12242 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 47583 # number of overall misses -system.cpu.l2cache.overall_misses::total 59825 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1188658000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1188658000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 916670500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 916670500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2966913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2966913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 916670500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4155571000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 5072241500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 916670500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4155571000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 5072241500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 256728 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 256728 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 471596 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 471596 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323640 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 323640 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336970 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 336970 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 323640 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485537 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 809177 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 323640 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485537 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 809177 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077642 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.077642 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.037826 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.037826 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.106977 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.106977 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.037826 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.098001 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.073933 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.037826 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.098001 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.073933 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103047.941049 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103047.941049 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74879.145564 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74879.145564 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82304.510652 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82304.510652 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84784.646887 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74879.145564 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87333.102158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84784.646887 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 11329 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 11329 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10064 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 10064 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 36503 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 36503 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10064 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 47832 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 57896 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10064 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 47832 # number of overall misses +system.cpu.l2cache.overall_misses::total 57896 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1187627500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1187627500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 761841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 761841000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2998033500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 2998033500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 761841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4185661000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4947502000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 761841000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4185661000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4947502000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 259400 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 259400 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 468713 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 468713 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 11 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 11 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 148572 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 148572 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 323481 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 323481 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 336950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 336950 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 323481 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 485522 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 809003 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 323481 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 485522 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 809003 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.909091 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.909091 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076253 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.076253 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.031112 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.031112 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.108334 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.108334 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.031112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.098517 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071565 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.031112 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.098517 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071565 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104830.744108 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104830.744108 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75699.622417 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75699.622417 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82131.153604 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82131.153604 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75699.622417 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87507.547249 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 85454.988255 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75699.622417 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87507.547249 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 85454.988255 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1067,155 +1074,155 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97288 # number of writebacks -system.cpu.l2cache.writebacks::total 97288 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3173 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3173 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 34 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 34 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 93 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 93 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 34 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3266 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3300 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 34 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3266 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3300 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112494 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 112494 # number of HardPFReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 97128 # number of writebacks +system.cpu.l2cache.writebacks::total 97128 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3171 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3171 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 30 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 30 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 100 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 100 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 30 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3271 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3301 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 30 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3271 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3301 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112673 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 112673 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8362 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8362 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12208 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12208 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 35955 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 35955 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12208 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 44317 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 56525 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12208 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 44317 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112494 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 169019 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10322993748 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 147000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 147000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 658062000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 658062000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 841432500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 841432500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2745124500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2745124500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 841432500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3403186500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4244619000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 841432500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3403186500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10322993748 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14567612748 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8158 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8158 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10034 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10034 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 36403 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 36403 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10034 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 44561 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 54595 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10034 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 44561 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 167268 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10413466023 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10413466023 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 149500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 149500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 654073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 654073000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 699673000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 699673000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2773387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2773387500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 699673000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3427460500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4127133500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 699673000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3427460500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10413466023 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14540599523 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056284 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056284 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037721 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.106701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.106701 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069855 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091274 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.909091 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.909091 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.054909 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.054909 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.031019 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.031019 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.108037 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.108037 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.031019 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091780 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067484 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.031019 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091780 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.208878 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91764.838551 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78696.723272 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78696.723272 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68924.680537 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68924.680537 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76348.894451 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76348.894451 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75092.773109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86189.202090 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.206758 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 92422.017901 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14950 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14950 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80175.655798 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80175.655798 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69730.217261 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69730.217261 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76185.685246 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76185.685246 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69730.217261 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76916.148650 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75595.448301 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69730.217261 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76916.148650 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86929.953864 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1617353 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 808194 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67170 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10592 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660621 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 354016 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 551426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 79011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142034 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336970 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 970420 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2426539 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41393152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62115968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103509120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318345 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1127532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.139813 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.372899 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 1617003 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 808019 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 65377 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56343 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 9034 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660441 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 356528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 548578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 77222 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323492 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336950 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 969940 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2426016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41372672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62114048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103486720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 316702 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1125716 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.137094 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.366537 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 980480 86.96% 86.96% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136460 12.10% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10592 0.94% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 980421 87.09% 87.09% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136261 12.10% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 9034 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1127532 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1616830500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1125716 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1616479500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485918614 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485683604 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728566986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728543988 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 144525 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97288 # Transaction distribution -system.membus.trans_dist::CleanEvict 27973 # Transaction distribution +system.membus.trans_dist::ReadResp 143003 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97128 # Transaction distribution +system.membus.trans_dist::CleanEvict 27951 # Transaction distribution system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 8362 # Transaction distribution -system.membus.trans_dist::ReadExResp 8362 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144526 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431046 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 431046 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16011200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16011200 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8158 # Transaction distribution +system.membus.trans_dist::ReadExResp 8158 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 143004 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 427412 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 427412 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15890496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15890496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 278159 # Request fanout histogram +system.membus.snoop_fanout::samples 276251 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 278159 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 276251 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 278159 # Request fanout histogram -system.membus.reqLayer0.occupancy 748401121 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 276251 # Request fanout histogram +system.membus.reqLayer0.occupancy 745073302 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 798557507 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 789293648 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |