diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref/arm')
4 files changed, 1637 insertions, 1603 deletions
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index a19ba8014..c63d403d5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064367 # Number of seconds simulated -sim_ticks 64366581500 # Number of ticks simulated -final_tick 64366581500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056337 # Number of seconds simulated +sim_ticks 56337328500 # Number of ticks simulated +final_tick 56337328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99170 # Simulator instruction rate (inst/s) -host_op_rate 140730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90012135 # Simulator tick rate (ticks/s) -host_mem_usage 295432 # Number of bytes of host memory used -host_seconds 715.09 # Real time elapsed on the host +host_inst_rate 184341 # Simulator instruction rate (inst/s) +host_op_rate 235745 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 146446418 # Simulator tick rate (ticks/s) +host_mem_usage 326872 # Number of bytes of host memory used +host_seconds 384.70 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated -sim_ops 100634375 # Number of ops (including micro ops) simulated +sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 8259328 # Number of bytes read from this memory -system.physmem.bytes_read::total 8259328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 325696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 325696 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5373248 # Number of bytes written to this memory -system.physmem.bytes_written::total 5373248 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 129052 # Number of read requests responded to by this memory -system.physmem.num_reads::total 129052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83957 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83957 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 128317021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128317021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5060017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5060017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 83478847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 83478847 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 83478847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 128317021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 211795868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 129052 # Number of read requests accepted -system.physmem.writeReqs 83957 # Number of write requests accepted -system.physmem.readBursts 129052 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83957 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8258880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8259328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5373248 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 8247168 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 323904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 323904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 128862 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128862 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 146389050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 146389050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5749367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5749367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 95369520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 95369520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 95369520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 146389050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241758570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128862 # Number of read requests accepted +system.physmem.writeReqs 83951 # Number of write requests accepted +system.physmem.readBursts 128862 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8246784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8196 # Per bank write bursts -system.physmem.perBankRdBursts::1 8381 # Per bank write bursts -system.physmem.perBankRdBursts::2 8249 # Per bank write bursts -system.physmem.perBankRdBursts::3 8185 # Per bank write bursts -system.physmem.perBankRdBursts::4 8327 # Per bank write bursts -system.physmem.perBankRdBursts::5 8459 # Per bank write bursts -system.physmem.perBankRdBursts::6 8094 # Per bank write bursts -system.physmem.perBankRdBursts::7 7981 # Per bank write bursts -system.physmem.perBankRdBursts::8 8076 # Per bank write bursts -system.physmem.perBankRdBursts::9 7644 # Per bank write bursts -system.physmem.perBankRdBursts::10 7831 # Per bank write bursts -system.physmem.perBankRdBursts::11 7843 # Per bank write bursts -system.physmem.perBankRdBursts::12 7891 # Per bank write bursts -system.physmem.perBankRdBursts::13 7884 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8027 # Per bank write bursts -system.physmem.perBankWrBursts::0 5181 # Per bank write bursts -system.physmem.perBankWrBursts::1 5375 # Per bank write bursts -system.physmem.perBankWrBursts::2 5284 # Per bank write bursts +system.physmem.perBankRdBursts::0 8164 # Per bank write bursts +system.physmem.perBankRdBursts::1 8373 # Per bank write bursts +system.physmem.perBankRdBursts::2 8238 # Per bank write bursts +system.physmem.perBankRdBursts::3 8169 # Per bank write bursts +system.physmem.perBankRdBursts::4 8316 # Per bank write bursts +system.physmem.perBankRdBursts::5 8449 # Per bank write bursts +system.physmem.perBankRdBursts::6 8089 # Per bank write bursts +system.physmem.perBankRdBursts::7 7969 # Per bank write bursts +system.physmem.perBankRdBursts::8 8071 # Per bank write bursts +system.physmem.perBankRdBursts::9 7635 # Per bank write bursts +system.physmem.perBankRdBursts::10 7816 # Per bank write bursts +system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7876 # Per bank write bursts +system.physmem.perBankRdBursts::14 7976 # Per bank write bursts +system.physmem.perBankRdBursts::15 8004 # Per bank write bursts +system.physmem.perBankWrBursts::0 5182 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts +system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5265 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5201 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts -system.physmem.perBankWrBursts::8 5034 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5146 # Per bank write bursts -system.physmem.perBankWrBursts::12 5344 # Per bank write bursts +system.physmem.perBankWrBursts::6 5198 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5033 # Per bank write bursts +system.physmem.perBankWrBursts::9 5086 # Per bank write bursts +system.physmem.perBankWrBursts::10 5252 # Per bank write bursts +system.physmem.perBankWrBursts::11 5143 # Per bank write bursts +system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5227 # Per bank write bursts +system.physmem.perBankWrBursts::15 5224 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64366550000 # Total gap between requests +system.physmem.totGap 56337297000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 129052 # Read request sizes (log2) +system.physmem.readPktSize::6 128862 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83957 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 128466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 557 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83951 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 126556 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2278 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -140,25 +140,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 610 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -189,96 +189,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.055332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.918314 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.655421 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12445 32.06% 32.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8253 21.26% 53.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4125 10.63% 63.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2767 7.13% 71.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2567 6.61% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1675 4.31% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1312 3.38% 85.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1197 3.08% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4479 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38820 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.028123 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 359.400532 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38348 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.034109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.640084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.462166 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12103 31.56% 31.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8116 21.16% 52.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4102 10.70% 63.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2869 7.48% 70.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2471 6.44% 77.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1658 4.32% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1256 3.28% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1197 3.12% 88.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4576 11.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38348 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.976149 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 361.694607 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.280116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.263015 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.779231 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4514 87.57% 87.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.14% 87.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 501 9.72% 97.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 114 2.21% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 12 0.23% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.273415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.256579 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.772702 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4535 87.94% 87.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 9 0.17% 88.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 476 9.23% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 113 2.19% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 16 0.31% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.10% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5155 # Writes before turning the bus around for reads -system.physmem.totQLat 1458157250 # Total ticks spent queuing -system.physmem.totMemAccLat 3877751000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 645225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11299.60 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads +system.physmem.totQLat 1494390000 # Total ticks spent queuing +system.physmem.totMemAccLat 3910440000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644280000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11597.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30049.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 128.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 83.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 128.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 83.48 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30347.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 146.38 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 95.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 146.39 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 95.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.65 # Data bus utilization in percentage -system.physmem.busUtilRead 1.00 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.65 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.89 # Data bus utilization in percentage +system.physmem.busUtilRead 1.14 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.63 # Average write queue length when enqueuing -system.physmem.readRowHits 112129 # Number of row buffer hits during reads -system.physmem.writeRowHits 62016 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.87 # Row buffer hit rate for writes -system.physmem.avgGap 302177.61 # Average gap between requests -system.physmem.pageHitRate 81.76 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 37447706500 # Time in different power states -system.physmem.memoryStateTime::REF 2149160000 # Time in different power states +system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing +system.physmem.readRowHits 112251 # Number of row buffer hits during reads +system.physmem.writeRowHits 62167 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.05 # Row buffer hit rate for writes +system.physmem.avgGap 264726.76 # Average gap between requests +system.physmem.pageHitRate 81.96 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 31175393250 # Time in different power states +system.physmem.memoryStateTime::REF 1881100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 24764549750 # Time in different power states +system.physmem.memoryStateTime::ACT 23277299250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 211795868 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26785 # Transaction distribution -system.membus.trans_dist::ReadResp 26785 # Transaction distribution -system.membus.trans_dist::Writeback 83957 # Transaction distribution -system.membus.trans_dist::ReadExReq 102267 # Transaction distribution -system.membus.trans_dist::ReadExResp 102267 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13632576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13632576 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13632576 # Total data (bytes) +system.membus.throughput 241758570 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26583 # Transaction distribution +system.membus.trans_dist::ReadResp 26583 # Transaction distribution +system.membus.trans_dist::Writeback 83951 # Transaction distribution +system.membus.trans_dist::ReadExReq 102279 # Transaction distribution +system.membus.trans_dist::ReadExResp 102279 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341675 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341675 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13620032 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13620032 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 975516500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1243562250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 942262500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1221459500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16883830 # Number of BP lookups -system.cpu.branchPred.condPredicted 12871662 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 417499 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11152919 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7446252 # Number of BTB hits +system.cpu.branchPred.lookups 14808792 # Number of BP lookups +system.cpu.branchPred.condPredicted 9910132 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 393085 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9534896 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6736289 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.765050 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1514690 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 511 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.648794 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1716012 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -364,70 +362,70 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 128733163 # number of cpu cycles simulated +system.cpu.numCycles 112674657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed -system.cpu.committedOps 100634375 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2952341 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1227274 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.815313 # CPI: cycles per instruction -system.cpu.ipc 0.550869 # IPC: instructions per cycle -system.cpu.tickCycles 109168240 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19564923 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 43522 # number of replacements -system.cpu.icache.tags.tagsinuse 1864.297124 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27427302 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45564 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 601.951146 # Average number of references to valid blocks. +system.cpu.cpi 1.588866 # CPI: cycles per instruction +system.cpu.ipc 0.629380 # IPC: instructions per cycle +system.cpu.tickCycles 93712970 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18961687 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 42434 # number of replacements +system.cpu.icache.tags.tagsinuse 1857.452171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24948252 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44476 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 560.937404 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1864.297124 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1857.452171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.906959 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.906959 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 727 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1194 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 846 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1075 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 54991298 # Number of tag accesses -system.cpu.icache.tags.data_accesses 54991298 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27427302 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27427302 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27427302 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27427302 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27427302 # number of overall hits -system.cpu.icache.overall_hits::total 27427302 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45565 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45565 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45565 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45565 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45565 # number of overall misses -system.cpu.icache.overall_misses::total 45565 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 909865240 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 909865240 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 909865240 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 909865240 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 909865240 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 909865240 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27472867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27472867 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27472867 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27472867 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27472867 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27472867 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001659 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001659 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001659 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001659 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001659 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001659 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19968.511796 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19968.511796 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19968.511796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19968.511796 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19968.511796 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50029934 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50029934 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24948252 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24948252 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24948252 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24948252 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24948252 # number of overall hits +system.cpu.icache.overall_hits::total 24948252 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44477 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44477 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44477 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44477 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44477 # number of overall misses +system.cpu.icache.overall_misses::total 44477 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 894991489 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 894991489 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 894991489 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 894991489 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 894991489 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 894991489 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24992729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24992729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24992729 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24992729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24992729 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24992729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20122.568721 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20122.568721 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20122.568721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20122.568721 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20122.568721 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,123 +434,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45565 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 45565 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 45565 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 45565 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 45565 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 45565 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 816831760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 816831760 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 816831760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 816831760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 816831760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 816831760 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001659 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001659 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001659 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001659 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17926.736750 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17926.736750 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17926.736750 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17926.736750 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44477 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44477 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44477 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44477 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44477 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44477 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804116511 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 804116511 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804116511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 804116511 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804116511 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 804116511 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18079.378353 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18079.378353 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18079.378353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18079.378353 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 333181591 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 99493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 99492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91129 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 450487 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 541616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2916096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18529664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 21445760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 21445760 # Total data (bytes) +system.cpu.toL2Bus.throughput 378768688 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 97959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 97958 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107038 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107038 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 88953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 538416 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2846464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 21338816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 21338816 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 296110500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 295133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 69298740 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67675489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 269478689 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 95911 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30027.975303 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 100921 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127032 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.794453 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 268454939 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu.l2cache.tags.replacements 95725 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29924.855625 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99436 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126843 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.783930 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26739.140336 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3288.834967 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.816014 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.100367 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.916381 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1012 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9483 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19900 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 597 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2914793 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2914793 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 72636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 72636 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128565 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128565 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 4766 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4766 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 77402 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 77402 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 77402 # number of overall hits -system.cpu.l2cache.overall_hits::total 77402 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 26857 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26857 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.inst 102267 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102267 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 129124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129124 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 129124 # number of overall misses -system.cpu.l2cache.overall_misses::total 129124 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1992283500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1992283500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7436939000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7436939000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9429222500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9429222500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9429222500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9429222500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 99493 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 99493 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128565 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128565 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107033 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107033 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 206526 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 206526 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 206526 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 206526 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269939 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.269939 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955472 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955472 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.625219 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.625219 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.625219 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.625219 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74181.163198 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74181.163198 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72720.809254 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72720.809254 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73024.553917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73024.553917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73024.553917 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 26686.795429 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.060196 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.814416 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098818 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.913234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9890 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19364 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2901241 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2901241 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 71304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71304 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128423 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128423 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.inst 4759 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4759 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 76063 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 76063 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 76063 # number of overall hits +system.cpu.l2cache.overall_hits::total 76063 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 26655 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26655 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.inst 102279 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102279 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 128934 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128934 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 128934 # number of overall misses +system.cpu.l2cache.overall_misses::total 128934 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1978942750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1978942750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 7452442750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7452442750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9431385500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9431385500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9431385500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9431385500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 97959 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 97959 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128423 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128423 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.inst 107038 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107038 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 204997 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 204997 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 204997 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 204997 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.272104 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.272104 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.955539 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955539 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.628956 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.628956 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.628956 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.628956 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74242.834365 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74242.834365 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 72863.860128 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72863.860128 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73148.940543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73148.940543 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73148.940543 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -561,119 +559,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83957 # number of writebacks -system.cpu.l2cache.writebacks::total 83957 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83951 # number of writebacks +system.cpu.l2cache.writebacks::total 83951 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 71 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26786 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26786 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102267 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102267 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 129053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 129053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 129053 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 129053 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1646558250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1646558250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6118064000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6118064000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7764622250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7764622250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7764622250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7764622250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269225 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269225 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955472 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955472 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.624875 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.624875 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.624875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61470.852311 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61470.852311 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 59824.420390 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59824.420390 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60166.150729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60166.150729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 26584 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26584 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 102279 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102279 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 128863 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128863 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 128863 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128863 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1636163750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1636163750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 6153335250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6153335250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7789499000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7789499000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7789499000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7789499000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.271379 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.271379 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.955539 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955539 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.628609 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.628609 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.628609 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61546.936127 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61546.936127 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 60162.254715 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60162.254715 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60447.909796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60447.909796 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 156865 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.633737 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 47252087 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160961 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 293.562335 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 802561250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 4070.633737 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.993807 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993807 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 156424 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.182682 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42664218 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160520 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.787553 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 770315250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 4068.182682 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.993209 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993209 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 711 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3335 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 95193929 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 95193929 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 27577955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27577955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 19642294 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642294 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86013120 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86013120 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 22988546 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22988546 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 19643834 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643834 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.inst 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 47220249 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47220249 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 47220249 # number of overall hits -system.cpu.dcache.overall_hits::total 47220249 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 56790 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56790 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 207607 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207607 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.inst 264397 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 264397 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 264397 # number of overall misses -system.cpu.dcache.overall_misses::total 264397 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2169299439 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2169299439 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15315314750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15315314750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 17484614189 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17484614189 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 17484614189 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17484614189 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 27634745 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27634745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.inst 42632380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42632380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 42632380 # number of overall hits +system.cpu.dcache.overall_hits::total 42632380 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 56015 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56015 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 206067 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206067 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.inst 262082 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262082 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 262082 # number of overall misses +system.cpu.dcache.overall_misses::total 262082 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 2143200689 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2143200689 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 15189809250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15189809250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 17333009939 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17333009939 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 17333009939 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17333009939 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 23044561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23044561 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 47484646 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47484646 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 47484646 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47484646 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010459 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.005568 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005568 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.005568 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005568 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38198.616640 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38198.616640 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73770.704986 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73770.704986 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66130.153478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66130.153478 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66130.153478 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 42894462 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42894462 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 42894462 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42894462 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002431 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002431 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.006110 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006110 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.006110 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006110 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 38261.192341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38261.192341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 73712.963502 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73712.963502 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 66135.827485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66135.827485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 66135.827485 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -682,48 +680,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128565 # number of writebacks -system.cpu.dcache.writebacks::total 128565 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2862 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2862 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 100574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100574 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 103436 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 103436 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 103436 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 103436 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53928 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53928 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107033 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 160961 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160961 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 160961 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160961 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 2001760311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2001760311 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7591657000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7591657000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593417311 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9593417311 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593417311 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9593417311 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.001951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128423 # number of writebacks +system.cpu.dcache.writebacks::total 128423 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 2533 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2533 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 99029 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99029 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 101562 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101562 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 101562 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101562 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 53482 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53482 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 107038 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107038 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 160520 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160520 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 160520 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160520 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 1986266811 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1986266811 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 7607104750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7607104750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9593371561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9593371561 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9593371561 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9593371561 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002321 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003390 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003390 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003390 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37119.127559 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37119.127559 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70928.190371 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70928.190371 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59600.880406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59600.880406 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 37138.977806 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37138.977806 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 71069.197388 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71069.197388 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 59764.338157 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 59764.338157 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 8bf0c37c9..9e6dda47f 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025431 # Number of seconds simulated -sim_ticks 25431292500 # Number of ticks simulated -final_tick 25431292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023896 # Number of seconds simulated +sim_ticks 23896420500 # Number of ticks simulated +final_tick 23896420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123125 # Simulator instruction rate (inst/s) -host_op_rate 174730 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44159257 # Simulator tick rate (ticks/s) -host_mem_usage 270444 # Number of bytes of host memory used -host_seconds 575.90 # Real time elapsed on the host +host_inst_rate 105740 # Simulator instruction rate (inst/s) +host_op_rate 135229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35635051 # Simulator tick rate (ticks/s) +host_mem_usage 262840 # Number of bytes of host memory used +host_seconds 670.59 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated -sim_ops 100626876 # Number of ops (including micro ops) simulated +sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 300416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942976 # Number of bytes read from this memory -system.physmem.bytes_read::total 8243392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 300416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 300416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372352 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124109 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128803 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83943 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11812848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312330803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 324143651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11812848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11812848 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 211249664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 211249664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 211249664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11812848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312330803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 535393315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128804 # Number of read requests accepted -system.physmem.writeReqs 83943 # Number of write requests accepted -system.physmem.readBursts 128804 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83943 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8243072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8243456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372352 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 299392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7936704 # Number of bytes read from this memory +system.physmem.bytes_read::total 8236096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 299392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 299392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4678 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124011 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128689 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 12528738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 332129408 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 344658147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 12528738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 12528738 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 224837021 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 224837021 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 224837021 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 12528738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 332129408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 569495168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128689 # Number of read requests accepted +system.physmem.writeReqs 83950 # Number of write requests accepted +system.physmem.readBursts 128689 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8235648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371072 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8236096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 342 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8140 # Per bank write bursts -system.physmem.perBankRdBursts::1 8383 # Per bank write bursts -system.physmem.perBankRdBursts::2 8248 # Per bank write bursts -system.physmem.perBankRdBursts::3 8172 # Per bank write bursts -system.physmem.perBankRdBursts::4 8304 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8104 # Per bank write bursts -system.physmem.perBankRdBursts::7 7960 # Per bank write bursts -system.physmem.perBankRdBursts::8 8081 # Per bank write bursts -system.physmem.perBankRdBursts::9 7608 # Per bank write bursts -system.physmem.perBankRdBursts::10 7787 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 380 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8141 # Per bank write bursts +system.physmem.perBankRdBursts::1 8384 # Per bank write bursts +system.physmem.perBankRdBursts::2 8239 # Per bank write bursts +system.physmem.perBankRdBursts::3 8150 # Per bank write bursts +system.physmem.perBankRdBursts::4 8295 # Per bank write bursts +system.physmem.perBankRdBursts::5 8428 # Per bank write bursts +system.physmem.perBankRdBursts::6 8074 # Per bank write bursts +system.physmem.perBankRdBursts::7 7958 # Per bank write bursts +system.physmem.perBankRdBursts::8 8067 # Per bank write bursts +system.physmem.perBankRdBursts::9 7598 # Per bank write bursts +system.physmem.perBankRdBursts::10 7783 # Per bank write bursts system.physmem.perBankRdBursts::11 7813 # Per bank write bursts -system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7882 # Per bank write bursts -system.physmem.perBankRdBursts::14 7972 # Per bank write bursts -system.physmem.perBankRdBursts::15 8012 # Per bank write bursts -system.physmem.perBankWrBursts::0 5177 # Per bank write bursts +system.physmem.perBankRdBursts::12 7877 # Per bank write bursts +system.physmem.perBankRdBursts::13 7881 # Per bank write bursts +system.physmem.perBankRdBursts::14 7983 # Per bank write bursts +system.physmem.perBankRdBursts::15 8011 # Per bank write bursts +system.physmem.perBankWrBursts::0 5183 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts -system.physmem.perBankWrBursts::2 5291 # Per bank write bursts -system.physmem.perBankWrBursts::3 5156 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::2 5289 # Per bank write bursts +system.physmem.perBankWrBursts::3 5157 # Per bank write bursts +system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5200 # Per bank write bursts -system.physmem.perBankWrBursts::7 5050 # Per bank write bursts -system.physmem.perBankWrBursts::8 5030 # Per bank write bursts -system.physmem.perBankWrBursts::9 5089 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5142 # Per bank write bursts +system.physmem.perBankWrBursts::6 5198 # Per bank write bursts +system.physmem.perBankWrBursts::7 5051 # Per bank write bursts +system.physmem.perBankWrBursts::8 5029 # Per bank write bursts +system.physmem.perBankWrBursts::9 5090 # Per bank write bursts +system.physmem.perBankWrBursts::10 5246 # Per bank write bursts +system.physmem.perBankWrBursts::11 5140 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5451 # Per bank write bursts +system.physmem.perBankWrBursts::14 5452 # Per bank write bursts system.physmem.perBankWrBursts::15 5223 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25431274000 # Total gap between requests +system.physmem.totGap 23896016500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128804 # Read request sizes (log2) +system.physmem.readPktSize::6 128689 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83943 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 74268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 52779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83950 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 68784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,97 +193,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.466900 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.757090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.203142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11986 31.74% 31.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7964 21.09% 52.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3753 9.94% 62.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2738 7.25% 70.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2422 6.41% 76.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 4.14% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1215 3.22% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1119 2.96% 86.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5002 13.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 361.810089 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 217.183531 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.455844 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 11970 31.83% 31.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7877 20.95% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3759 10.00% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2606 6.93% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2473 6.58% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1554 4.13% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1216 3.23% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1043 2.77% 86.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5109 13.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 37607 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5143 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.040249 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.430137 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5140 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.009139 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 391.762417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5141 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 5143 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 5143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.318102 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.295777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.900493 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4492 87.34% 87.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 9 0.17% 87.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 404 7.86% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 175 3.40% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 41 0.80% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 14 0.27% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 4 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.317908 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.294258 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.943897 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4493 87.36% 87.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.25% 87.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 424 8.24% 95.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 146 2.84% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 43 0.84% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 15 0.29% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 3 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.04% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5143 # Writes before turning the bus around for reads -system.physmem.totQLat 2477042500 # Total ticks spent queuing -system.physmem.totMemAccLat 4892005000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643990000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19232.00 # Average queueing delay per DRAM burst +system.physmem.totQLat 2744774250 # Total ticks spent queuing +system.physmem.totMemAccLat 5157561750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643410000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21329.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37982.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 324.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 211.20 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 324.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 211.25 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40079.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 344.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 224.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 344.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 224.84 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.18 # Data bus utilization in percentage -system.physmem.busUtilRead 2.53 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.65 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.78 # Average write queue length when enqueuing -system.physmem.readRowHits 112907 # Number of row buffer hits during reads -system.physmem.writeRowHits 62042 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.91 # Row buffer hit rate for writes -system.physmem.avgGap 119537.64 # Average gap between requests -system.physmem.pageHitRate 82.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 10352020250 # Time in different power states -system.physmem.memoryStateTime::REF 849160000 # Time in different power states +system.physmem.busUtil 4.45 # Data bus utilization in percentage +system.physmem.busUtilRead 2.69 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.76 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing +system.physmem.readRowHits 112874 # Number of row buffer hits during reads +system.physmem.writeRowHits 62123 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 112378.33 # Average gap between requests +system.physmem.pageHitRate 82.30 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 9567571500 # Time in different power states +system.physmem.memoryStateTime::REF 797940000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 14228986000 # Time in different power states +system.physmem.memoryStateTime::ACT 13530763500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 535393315 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26553 # Transaction distribution -system.membus.trans_dist::ReadResp 26552 # Transaction distribution -system.membus.trans_dist::Writeback 83943 # Transaction distribution -system.membus.trans_dist::UpgradeReq 342 # Transaction distribution -system.membus.trans_dist::UpgradeResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 102251 # Transaction distribution -system.membus.trans_dist::ReadExResp 102251 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342234 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13615744 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13615744 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13615744 # Total data (bytes) +system.membus.throughput 569495168 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26431 # Transaction distribution +system.membus.trans_dist::ReadResp 26431 # Transaction distribution +system.membus.trans_dist::Writeback 83950 # Transaction distribution +system.membus.trans_dist::UpgradeReq 380 # Transaction distribution +system.membus.trans_dist::UpgradeResp 380 # Transaction distribution +system.membus.trans_dist::ReadExReq 102258 # Transaction distribution +system.membus.trans_dist::ReadExResp 102258 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342088 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342088 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13608896 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13608896 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13608896 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 901934500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1187807158 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 898146000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 1183170872 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 17001662 # Number of BP lookups -system.cpu.branchPred.condPredicted 13020210 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 614898 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10708539 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7958691 # Number of BTB hits +system.cpu.branchPred.lookups 17877019 # Number of BP lookups +system.cpu.branchPred.condPredicted 11927811 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 593439 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11204319 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8313088 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.320979 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1855518 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113838 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 74.195388 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1978187 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104069 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -369,521 +371,521 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 50862586 # number of cpu cycles simulated +system.cpu.numCycles 47792842 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12841579 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87379296 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17001662 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9814209 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21679126 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2704202 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6435967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11938705 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 201875 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43012606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.839331 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.389146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13399730 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 91818563 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17877019 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 10291275 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 33374868 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1293258 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 460 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3119 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 70 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12485707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 222370 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47424876 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.444936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.221090 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21356489 49.65% 49.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2172665 5.05% 54.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2009321 4.67% 59.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2081413 4.84% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1500240 3.49% 67.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1419840 3.30% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 985272 2.29% 73.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1219233 2.83% 76.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10268133 23.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25840907 54.49% 54.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2398343 5.06% 59.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2102611 4.43% 63.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2392037 5.04% 69.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1862029 3.93% 72.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1496992 3.16% 76.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1004992 2.12% 78.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1407650 2.97% 81.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8919315 18.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43012606 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.334267 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.717948 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13769056 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5959303 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20895341 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 441693 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1947213 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3430949 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 110387 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 119589480 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 395300 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1947213 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14636498 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 284865 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1020852 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20468957 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4654221 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117623188 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 544 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 181856 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2734092 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1628680 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 1673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117928367 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541896046 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 487330730 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3427 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18795695 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20563 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20550 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5392644 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30100241 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22927452 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5590192 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5698921 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113818479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36102 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108240105 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 379531 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 13068972 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 32214297 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2316 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43012606 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.516474 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.084237 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47424876 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374052 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.921178 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9991238 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18372924 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 15962018 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2553700 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 544996 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3514191 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104008 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 110994138 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 375319 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 544996 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 11354333 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2895918 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1063087 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17104266 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14462276 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 108881212 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1310 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1983947 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2643349 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 9691184 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 114456313 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 501643948 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 126478316 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2998 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 20827087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 24787 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25137 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12915604 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25719384 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 23405570 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6651489 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7812944 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105238243 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 38026 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99646497 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 159437 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 14433434 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 35646535 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4240 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47424876 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.101144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.177334 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9996470 23.24% 23.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6251950 14.54% 37.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6474591 15.05% 52.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6613067 15.37% 68.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5424130 12.61% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4356381 10.13% 90.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2112627 4.91% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1221535 2.84% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 561855 1.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16924239 35.69% 35.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6535440 13.78% 49.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6148782 12.97% 62.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5092843 10.74% 73.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5223877 11.02% 84.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3271997 6.90% 91.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2206801 4.65% 95.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1128511 2.38% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 892386 1.88% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43012606 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47424876 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 131486 5.24% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1416079 56.44% 61.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 961652 38.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 215167 9.06% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1190055 50.09% 59.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 970810 40.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57280619 52.92% 52.92% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91502 0.08% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 249 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29070055 26.86% 79.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21797673 20.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 51976863 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 92995 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 147 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25513927 25.60% 77.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22062558 22.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108240105 # Type of FU issued -system.cpu.iq.rate 2.128089 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2509218 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023182 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262380760 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 126960554 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106504533 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 805 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1416 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110748938 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 385 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2726538 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99646497 # Type of FU issued +system.cpu.iq.rate 2.084967 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2376032 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023845 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 249252729 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 119771582 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 97191472 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 610 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 940 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 210 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 102022220 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 309 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2232705 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2793133 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5994 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 39986 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2371714 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2853122 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4762 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 65666 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2849832 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 777 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 726205 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 82286 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1947213 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 83242 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 154560 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113864521 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 271261 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30100241 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22927452 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20182 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11127 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 139253 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 39986 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 397706 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 183440 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 581146 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107196907 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28742416 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1043198 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 544996 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1714516 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 834399 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 105286702 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 183365 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25719384 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 23405570 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22106 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17305 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 806226 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 65666 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 396732 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 182672 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 579404 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98631248 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25214590 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1015249 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9940 # number of nop insts executed -system.cpu.iew.exec_refs 50252614 # number of memory reference insts executed -system.cpu.iew.exec_branches 14716112 # Number of branches executed -system.cpu.iew.exec_stores 21510198 # Number of stores executed -system.cpu.iew.exec_rate 2.107579 # Inst execution rate -system.cpu.iew.wb_sent 106740577 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106504731 # cumulative count of insts written-back -system.cpu.iew.wb_producers 57038202 # num instructions producing a value -system.cpu.iew.wb_consumers 114479064 # num instructions consuming a value +system.cpu.iew.exec_nop 10433 # number of nop insts executed +system.cpu.iew.exec_refs 46968385 # number of memory reference insts executed +system.cpu.iew.exec_branches 14905400 # Number of branches executed +system.cpu.iew.exec_stores 21753795 # Number of stores executed +system.cpu.iew.exec_rate 2.063724 # Inst execution rate +system.cpu.iew.wb_sent 97441036 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97191682 # cumulative count of insts written-back +system.cpu.iew.wb_producers 50912103 # num instructions producing a value +system.cpu.iew.wb_consumers 98942269 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.093970 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.498241 # average fanout of values written-back +system.cpu.iew.wb_rate 2.033603 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514564 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 13236328 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14604340 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 506712 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 41065393 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.450541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.921831 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 491808 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45293214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.002246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.787973 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14078032 34.28% 34.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 10319124 25.13% 59.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2761047 6.72% 66.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2619650 6.38% 72.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1508272 3.67% 76.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1822351 4.44% 80.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 663911 1.62% 82.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 540097 1.32% 83.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6752909 16.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20766641 45.85% 45.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9214809 20.34% 66.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2670756 5.90% 72.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2400198 5.30% 77.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2023573 4.47% 81.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 972100 2.15% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 768345 1.70% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 447977 0.99% 86.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6028815 13.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 41065393 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 45293214 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed -system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed +system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47862846 # Number of memory references committed -system.cpu.commit.loads 27307108 # Number of loads committed +system.cpu.commit.refs 43422000 # Number of memory references committed +system.cpu.commit.loads 22866262 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed system.cpu.commit.branches 13741485 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. +system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 52689456 52.36% 52.36% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 80119 0.08% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.44% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 27307108 27.14% 79.57% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20555738 20.43% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47186010 52.03% 52.03% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 100632428 # Class of committed instruction -system.cpu.commit.bw_lim_events 6752909 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction +system.cpu.commit.bw_lim_events 6028815 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 148155941 # The number of ROB reads -system.cpu.rob.rob_writes 229697127 # The number of ROB writes -system.cpu.timesIdled 83826 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7849980 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 144531576 # The number of ROB reads +system.cpu.rob.rob_writes 212728591 # The number of ROB writes +system.cpu.timesIdled 10876 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 367966 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated -system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.717308 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.717308 # CPI: Total CPI of All Threads -system.cpu.ipc 1.394102 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.394102 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 515806241 # number of integer regfile reads -system.cpu.int_regfile_writes 104262317 # number of integer regfile writes -system.cpu.fp_regfile_reads 1054 # number of floating regfile reads -system.cpu.fp_regfile_writes 938 # number of floating regfile writes -system.cpu.misc_regfile_reads 49641533 # number of misc regfile reads +system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.674016 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.674016 # CPI: Total CPI of All Threads +system.cpu.ipc 1.483645 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.483645 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 106842718 # number of integer regfile reads +system.cpu.int_regfile_writes 59180200 # number of integer regfile writes +system.cpu.fp_regfile_reads 1084 # number of floating regfile reads +system.cpu.fp_regfile_writes 924 # number of floating regfile writes +system.cpu.cc_regfile_reads 361896749 # number of cc regfile reads +system.cpu.cc_regfile_writes 40174850 # number of cc regfile writes +system.cpu.misc_regfile_reads 45647350 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 820945141 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 90021 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 90020 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129157 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68737 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454707 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 523444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2182208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20843008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20843008 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 34688 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 292444997 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 52710982 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 869793867 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 88682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 88681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129104 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 425 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 106980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 106980 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66417 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454340 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 520757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2108672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18643008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20751680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20751680 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33280 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291703993 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 50946473 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 261104274 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 32259 # number of replacements -system.cpu.icache.tags.tagsinuse 1808.767041 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11900174 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 34296 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 346.984313 # Average number of references to valid blocks. +system.cpu.toL2Bus.respLayer1.occupancy 259533576 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.icache.tags.replacements 31122 # number of replacements +system.cpu.icache.tags.tagsinuse 1801.454521 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12448339 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 33152 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 375.492851 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1808.767041 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.883187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.883187 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2037 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1801.454521 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.879616 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.879616 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2030 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 674 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.994629 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23912047 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23912047 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11900181 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11900181 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11900181 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11900181 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11900181 # number of overall hits -system.cpu.icache.overall_hits::total 11900181 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38523 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38523 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38523 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38523 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38523 # number of overall misses -system.cpu.icache.overall_misses::total 38523 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 840683730 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 840683730 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 840683730 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 840683730 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 840683730 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 840683730 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11938704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11938704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11938704 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11938704 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11938704 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11938704 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003227 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003227 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003227 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003227 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003227 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003227 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21822.903979 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21822.903979 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21822.903979 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21822.903979 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21822.903979 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21822.903979 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1168 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 672 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.991211 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 25004882 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25004882 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 12448346 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12448346 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12448346 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12448346 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12448346 # number of overall hits +system.cpu.icache.overall_hits::total 12448346 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 37361 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 37361 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 37361 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 37361 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 37361 # number of overall misses +system.cpu.icache.overall_misses::total 37361 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 833057215 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 833057215 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 833057215 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 833057215 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 833057215 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 833057215 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12485707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12485707 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12485707 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12485707 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12485707 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12485707 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002992 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002992 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002992 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002992 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002992 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002992 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22297.508498 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22297.508498 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22297.508498 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22297.508498 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22297.508498 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1054 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 29 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.275862 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3883 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3883 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3883 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3883 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3883 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3883 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34640 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 34640 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 34640 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 34640 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 34640 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 34640 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 683348518 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 683348518 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 683348518 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1534 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91492426 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91492426 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 25658218 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 25658218 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266460 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266460 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 16005 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 16005 # 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number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5184955254 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5184955254 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 125206065525 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 125206065525 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 993000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 993000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 130391020779 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 130391020779 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 130391020779 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 130391020779 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 25783136 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 25783136 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40138332 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40138332 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40221813 # number of overall hits +system.cpu.dcache.overall_hits::total 40221813 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 172724 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 172724 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1586243 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1586243 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 47266 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 47266 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1758967 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1758967 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1806233 # number of overall misses +system.cpu.dcache.overall_misses::total 1806233 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5001907368 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5001907368 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128651444042 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128651444042 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1064000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1064000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 133653351410 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 133653351410 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 133653351410 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 133653351410 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22047398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22047398 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16048 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16048 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 130747 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 130747 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16021 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16021 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 45633037 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 45633037 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 45633037 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 45633037 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004845 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004845 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079771 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079771 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002679 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002679 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037437 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037437 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037437 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037437 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41506.870539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41506.870539 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79072.138163 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79072.138163 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 23093.023256 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 23093.023256 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76325.304447 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76325.304447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76325.304447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76325.304447 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4253 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1744 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.597122 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 79.272727 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41897299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41897299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42028046 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42028046 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007834 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007834 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079912 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079912 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.361507 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.361507 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002372 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.041983 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.041983 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042977 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042977 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.959774 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.959774 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81104.499148 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81104.499148 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75984.001638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75984.001638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73995.631466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73995.631466 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 911565 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1622 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13218 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 68.963913 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 108.133333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129157 # number of writebacks -system.cpu.dcache.writebacks::total 129157 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69501 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69501 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1476084 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1476084 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545585 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545585 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545585 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545585 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107357 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107357 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162774 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162774 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162774 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162774 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2210443817 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2210443817 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8528691900 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8528691900 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 11000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 11000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10739135717 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10739135717 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10739135717 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10739135717 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.000062 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.000062 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003567 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003567 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39887.468051 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39887.468051 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79442.345632 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79442.345632 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65975.743774 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65975.743774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65975.743774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65975.743774 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129104 # number of writebacks +system.cpu.dcache.writebacks::total 129104 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 141550 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 141550 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1478910 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1478910 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1620460 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1620460 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1620460 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1620460 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 31174 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 31174 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107333 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107333 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24111 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 24111 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138507 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138507 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162618 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162618 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 566566801 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 566566801 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8639740111 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8639740111 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1848458500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1848458500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9206306912 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9206306912 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11054765412 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11054765412 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001414 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.184410 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.184410 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003306 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003306 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003869 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003869 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18174.337621 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18174.337621 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80494.723067 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80494.723067 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76664.530712 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76664.530712 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66468.170648 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66468.170648 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67979.961702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67979.961702 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index d5f8b245c..cf7a88b7a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.053932 # Number of seconds simulated -sim_ticks 53932157000 # Number of ticks simulated -final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.048960 # Number of seconds simulated +sim_ticks 48960011000 # Number of ticks simulated +final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1371353 # Simulator instruction rate (inst/s) -host_op_rate 1946078 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1042965622 # Simulator tick rate (ticks/s) -host_mem_usage 308436 # Number of bytes of host memory used -host_seconds 51.71 # Real time elapsed on the host +host_inst_rate 1457592 # Simulator instruction rate (inst/s) +host_op_rate 1864058 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1006352889 # Simulator tick rate (ticks/s) +host_mem_usage 314048 # Number of bytes of host memory used +host_seconds 48.65 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated -sim_ops 100632428 # Number of ops (including micro ops) simulated +sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory @@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 312580272 # Nu system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27156252 # Number of read requests responded to by this memory -system.physmem.num_reads::total 105301320 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory +system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5795805126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1976063093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7771868220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5795805126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5795805126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1458502967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1458502967 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9230371187 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10167763810 # Throughput (bytes/s) system.membus.data_through_bus 497813828 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 107864315 # number of cpu cycles simulated +system.cpu.numCycles 97920023 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70913181 # Number of instructions committed -system.cpu.committedOps 100632428 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses +system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472780 # number of integer instructions +system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528488 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 452305352 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written +system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862847 # number of memory refs -system.cpu.num_load_insts 27307108 # Number of load instructions +system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_mem_refs 43422001 # number of memory refs +system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 107864315 # Number of busy cycles +system.cpu.num_busy_cycles 97920023 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13741485 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 100634375 # Class of executed instruction +system.cpu.op_class::total 90690083 # Class of executed instruction ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 247ca051b..a71c9e67b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132689 # Number of seconds simulated -sim_ticks 132689045000 # Number of ticks simulated -final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.127294 # Number of seconds simulated +sim_ticks 127293983000 # Number of ticks simulated +final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 682193 # Simulator instruction rate (inst/s) -host_op_rate 967367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1286269606 # Simulator tick rate (ticks/s) -host_mem_usage 318200 # Number of bytes of host memory used -host_seconds 103.16 # Real time elapsed on the host +host_inst_rate 875914 # Simulator instruction rate (inst/s) +host_op_rate 1118296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1584379759 # Simulator tick rate (ticks/s) +host_mem_usage 323804 # Number of bytes of host memory used +host_seconds 80.34 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated -sim_ops 99791654 # Number of ops (including micro ops) simulated +sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory @@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 123820 # Nu system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 102119538 # Throughput (bytes/s) +system.physmem.bw_read::cpu.inst 2007071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62253375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64260445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2007071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2007071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42187194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42187194 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42187194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 106447639 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 25532 # Transaction distribution system.membus.trans_dist::ReadResp 25532 # Transaction distribution system.membus.trans_dist::Writeback 83909 # Transaction distribution @@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 13550144 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -138,78 +138,80 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 265378090 # number of cpu cycles simulated +system.cpu.numCycles 254587966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed -system.cpu.committedOps 99791654 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses +system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls -system.cpu.num_int_insts 91472780 # number of integer instructions +system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls +system.cpu.num_int_insts 81528488 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 533671029 # number of times the integer registers were read -system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written +system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read +system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_mem_refs 47862847 # number of memory refs -system.cpu.num_load_insts 27307108 # Number of load instructions +system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read +system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written +system.cpu.num_mem_refs 43422001 # number of memory refs +system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 265378090 # Number of busy cycles +system.cpu.num_busy_cycles 254587966 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13741485 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction -system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction +system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction +system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 100634375 # Class of executed instruction +system.cpu.op_class::total 90690083 # Class of executed instruction system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.675052 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.846521 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.846521 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1755 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses @@ -225,12 +227,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 414091500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 414091500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 414091500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 414091500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 414091500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 414091500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -243,12 +245,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21900.333192 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21900.333192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21900.333192 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -263,44 +265,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 376275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 376275500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 376275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 376275500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 376275500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 376275500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19900.333192 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19900.333192 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30351.010864 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27796.806295 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.765897 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.438673 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.042799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19788 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 616 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15086 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13934 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses @@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total 127812 # nu system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses system.cpu.l2cache.overall_misses::total 127812 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207838000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1126741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1334579000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5318574000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5318574000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 207838000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6445315000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6653153000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 207838000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6445315000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6653153000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208207500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1130236000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1338443500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321243500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5321243500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 208207500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6451479500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6659687000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 208207500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6451479500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6659687000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) @@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.714409 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52063.627255 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.238626 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52270.836597 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.136879 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.136879 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52156.187375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52471.494893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52422.195676 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.236801 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.236801 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52105.334397 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52105.334397 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total 127812 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159943500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868345500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028289000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091943000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091943000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159943500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4960288500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5120232000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159943500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4960288500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5120232000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses @@ -417,90 +419,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.007014 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40313.161560 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40274.518252 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.264372 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.264372 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 443 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3604 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 94204142 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 94204142 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits -system.cpu.dcache.overall_hits::total 46830236 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits +system.cpu.dcache.overall_hits::total 42576328 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses -system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses +system.cpu.dcache.overall_misses::total 177384 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,40 +521,54 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 148145463 # Throughput (bytes/s) +system.cpu.toL2Bus.throughput 154424267 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution |