diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref')
12 files changed, 2730 insertions, 2651 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini index 4117f093b..46094eb94 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini @@ -149,7 +149,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -583,7 +583,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -643,7 +643,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -760,6 +760,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -771,7 +772,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -779,29 +780,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -821,6 +829,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -852,9 +861,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout index dcc24233a..a86af0918 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4306 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:45 +gem5 executing on e108600-lin, pid 28063 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 60000593000 because target called exit() +Exiting @ tick 61709224000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 58628a22b..4a990b700 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060094 # Number of seconds simulated -sim_ticks 60093931000 # Number of ticks simulated -final_tick 60093931000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061709 # Number of seconds simulated +sim_ticks 61709224000 # Number of ticks simulated +final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 276952 # Simulator instruction rate (inst/s) -host_op_rate 276952 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 188189933 # Simulator tick rate (ticks/s) -host_mem_usage 264524 # Number of bytes of host memory used -host_seconds 319.33 # Real time elapsed on the host +host_inst_rate 242211 # Simulator instruction rate (inst/s) +host_op_rate 242211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 169006859 # Simulator tick rate (ticks/s) +host_mem_usage 262168 # Number of bytes of host memory used +host_seconds 365.13 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 438272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10168832 # Number of bytes read from this memory -system.physmem.bytes_read::total 10607104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7376000 # Number of bytes written to this memory -system.physmem.bytes_written::total 7376000 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158888 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165736 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115250 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115250 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7293116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169215623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 176508739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7293116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7293116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122741180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122741180 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122741180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7293116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169215623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 299249919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165736 # Number of read requests accepted -system.physmem.writeReqs 115250 # Number of write requests accepted -system.physmem.readBursts 165736 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115250 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10606464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 7374720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10607104 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7376000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory +system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory +system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165740 # Number of read requests accepted +system.physmem.writeReqs 115251 # Number of write requests accepted +system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue +system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10345 # Per bank write bursts -system.physmem.perBankRdBursts::1 10388 # Per bank write bursts +system.physmem.perBankRdBursts::1 10387 # Per bank write bursts system.physmem.perBankRdBursts::2 10224 # Per bank write bursts -system.physmem.perBankRdBursts::3 10067 # Per bank write bursts +system.physmem.perBankRdBursts::3 10068 # Per bank write bursts system.physmem.perBankRdBursts::4 10353 # Per bank write bursts system.physmem.perBankRdBursts::5 10360 # Per bank write bursts system.physmem.perBankRdBursts::6 9794 # Per bank write bursts -system.physmem.perBankRdBursts::7 10229 # Per bank write bursts +system.physmem.perBankRdBursts::7 10230 # Per bank write bursts system.physmem.perBankRdBursts::8 10568 # Per bank write bursts system.physmem.perBankRdBursts::9 10626 # Per bank write bursts -system.physmem.perBankRdBursts::10 10567 # Per bank write bursts +system.physmem.perBankRdBursts::10 10568 # Per bank write bursts system.physmem.perBankRdBursts::11 10241 # Per bank write bursts -system.physmem.perBankRdBursts::12 10307 # Per bank write bursts -system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::12 10306 # Per bank write bursts +system.physmem.perBankRdBursts::13 10592 # Per bank write bursts system.physmem.perBankRdBursts::14 10494 # Per bank write bursts system.physmem.perBankRdBursts::15 10573 # Per bank write bursts system.physmem.perBankWrBursts::0 7166 # Per bank write bursts -system.physmem.perBankWrBursts::1 7280 # Per bank write bursts +system.physmem.perBankWrBursts::1 7281 # Per bank write bursts system.physmem.perBankWrBursts::2 7303 # Per bank write bursts -system.physmem.perBankWrBursts::3 7011 # Per bank write bursts -system.physmem.perBankWrBursts::4 7144 # Per bank write bursts -system.physmem.perBankWrBursts::5 7304 # Per bank write bursts +system.physmem.perBankWrBursts::3 7012 # Per bank write bursts +system.physmem.perBankWrBursts::4 7145 # Per bank write bursts +system.physmem.perBankWrBursts::5 7305 # Per bank write bursts system.physmem.perBankWrBursts::6 6890 # Per bank write bursts -system.physmem.perBankWrBursts::7 7170 # Per bank write bursts -system.physmem.perBankWrBursts::8 7244 # Per bank write bursts -system.physmem.perBankWrBursts::9 7072 # Per bank write bursts -system.physmem.perBankWrBursts::10 7215 # Per bank write bursts +system.physmem.perBankWrBursts::7 7164 # Per bank write bursts +system.physmem.perBankWrBursts::8 7246 # Per bank write bursts +system.physmem.perBankWrBursts::9 7071 # Per bank write bursts +system.physmem.perBankWrBursts::10 7213 # Per bank write bursts system.physmem.perBankWrBursts::11 7126 # Per bank write bursts system.physmem.perBankWrBursts::12 7072 # Per bank write bursts system.physmem.perBankWrBursts::13 7397 # Per bank write bursts -system.physmem.perBankWrBursts::14 7353 # Per bank write bursts +system.physmem.perBankWrBursts::14 7351 # Per bank write bursts system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60093907500 # Total gap between requests +system.physmem.totGap 61709200500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165736 # Read request sizes (log2) +system.physmem.readPktSize::6 165740 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115250 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115251 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6962 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7141 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,124 +194,134 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 381.637629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.425229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.616158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14360 30.48% 30.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9586 20.35% 50.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5012 10.64% 61.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3327 7.06% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 5.24% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1960 4.16% 77.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1618 3.43% 81.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1472 3.12% 84.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7307 15.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47112 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.226489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.911576 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 310.890099 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7133 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.149965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.141117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.557028 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6628 92.89% 92.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 11 0.15% 93.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 441 6.18% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 47 0.66% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 7 0.10% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads -system.physmem.totQLat 1892978500 # Total ticks spent queuing -system.physmem.totMemAccLat 5000341000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 828630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11422.34 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads +system.physmem.totQLat 3617300750 # Total ticks spent queuing +system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30172.34 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 176.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.72 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 176.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.74 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.34 # Data bus utilization in percentage -system.physmem.busUtilRead 1.38 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.81 # Average write queue length when enqueuing -system.physmem.readRowHits 144145 # Number of row buffer hits during reads -system.physmem.writeRowHits 89685 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.82 # Row buffer hit rate for writes -system.physmem.avgGap 213867.98 # Average gap between requests -system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 171128160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 93373500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 637486200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 370921680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12045269070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25486025250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42728761380 # Total energy per rank (pJ) -system.physmem_0.averagePower 711.117850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 42256937250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2006420000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15823407750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 184781520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 100823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654677400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 375431760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3924557520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12738285900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24878115750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42856673100 # Total energy per rank (pJ) -system.physmem_1.averagePower 713.246634 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41240527500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2006420000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16840206000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14696108 # Number of BP lookups -system.cpu.branchPred.condPredicted 9501028 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386035 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10214286 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368013 # Number of BTB hits +system.physmem.busUtil 2.28 # Data bus utilization in percentage +system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing +system.physmem.readRowHits 144262 # Number of row buffer hits during reads +system.physmem.writeRowHits 89468 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes +system.physmem.avgGap 219612.73 # Average gap between requests +system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ) +system.physmem_0.averagePower 393.299410 # Core power per rank (mW) +system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states +system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ) +system.physmem_1.averagePower 400.858918 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14696527 # Number of BP lookups +system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.344181 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712199 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84611 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37560 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31792 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5768 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7597 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20579333 # DTB read hits -system.cpu.dtb.read_misses 95423 # DTB read misses +system.cpu.dtb.read_hits 20579387 # DTB read hits +system.cpu.dtb.read_misses 95377 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674756 # DTB read accesses -system.cpu.dtb.write_hits 14666035 # DTB write hits +system.cpu.dtb.read_accesses 20674764 # DTB read accesses +system.cpu.dtb.write_hits 14666029 # DTB write hits system.cpu.dtb.write_misses 8840 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674875 # DTB write accesses -system.cpu.dtb.data_hits 35245368 # DTB hits -system.cpu.dtb.data_misses 104263 # DTB misses +system.cpu.dtb.write_accesses 14674869 # DTB write accesses +system.cpu.dtb.data_hits 35245416 # DTB hits +system.cpu.dtb.data_misses 104217 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35349631 # DTB accesses -system.cpu.itb.fetch_hits 25649355 # ITB hits -system.cpu.itb.fetch_misses 5175 # ITB misses +system.cpu.dtb.data_accesses 35349633 # DTB accesses +system.cpu.itb.fetch_hits 25650137 # ITB hits +system.cpu.itb.fetch_misses 5179 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25654530 # ITB accesses +system.cpu.itb.fetch_accesses 25655316 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,16 +335,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120187862 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 123418448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1085816 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359006 # CPI: cycles per instruction -system.cpu.ipc 0.735832 # IPC: instructions per cycle +system.cpu.cpi 1.395535 # CPI: cycles per instruction +system.cpu.ipc 0.716571 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction @@ -370,106 +380,106 @@ system.cpu.op_class_0::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 91997493 # Number of cycles that the object actually ticked -system.cpu.idleCycles 28190369 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200806 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.595144 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34648172 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204902 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.096309 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 696470500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.595144 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993798 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993798 # Average percentage of cache occupancy +system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked +system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 200809 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3399 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70184522 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70184522 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314904 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314904 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333268 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34648172 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34648172 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34648172 # number of overall hits -system.cpu.dcache.overall_hits::total 34648172 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61529 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61529 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341638 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341638 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341638 # number of overall misses -system.cpu.dcache.overall_misses::total 341638 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2787384000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2787384000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21745232000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21745232000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24532616000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24532616000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24532616000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24532616000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20376433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20376433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits +system.cpu.dcache.overall_hits::total 34647996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses +system.cpu.dcache.overall_misses::total 341611 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989810 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989810 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989810 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009764 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009764 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009764 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009764 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45301.955176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45301.955176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77631.322092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77631.322092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71808.803470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71808.803470 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71808.803470 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168116 # number of writebacks -system.cpu.dcache.writebacks::total 168116 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 194 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 194 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136542 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136542 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136736 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136736 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136736 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -478,338 +488,338 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 44391.652401 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 44391.652401 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76579.203438 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76579.203438 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66944.239197 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66944.239197 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1033 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 801 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51454674 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51454674 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25493390 # 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number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6849 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6849 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27980 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27980 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6849 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158888 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165737 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6849 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158888 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165737 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9336833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9336833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 494657000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 494657000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2000469500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2000469500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 494657000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11337303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11831960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 494657000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11337303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11831960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6850 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6850 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27983 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27983 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6850 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158891 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165741 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6850 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158891 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165741 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10524814500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10524814500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 665637500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 665637500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2366330500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2366330500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 665637500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12891145000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13556782500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 665637500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12891145000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13556782500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043914 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456183 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459274 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043914 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775434 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459274 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71323.628044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71323.628044 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72223.244269 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72223.244269 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71496.408149 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71496.408149 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72223.244269 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71354.054428 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71389.973271 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715589 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354722 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153916 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52715 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61335 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610610 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19832320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43705472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135276 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7376064 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 496143 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008584 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.092253 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 135280 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 491884 99.14% 99.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 496143 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679826500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233946499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307357491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296869 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 131133 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60093931000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34828 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115250 # Transaction distribution -system.membus.trans_dist::CleanEvict 15883 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34832 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution +system.membus.trans_dist::CleanEvict 15886 # Transaction distribution system.membus.trans_dist::ReadExReq 130908 # Transaction distribution system.membus.trans_dist::ReadExResp 130908 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34828 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462605 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462605 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983104 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165736 # Request fanout histogram +system.membus.snoop_fanout::samples 165740 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165736 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165736 # Request fanout histogram -system.membus.reqLayer0.occupancy 829286500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 875094750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +system.membus.snoop_fanout::total 165740 # Request fanout histogram +system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index d19d770e5..42d282c4a 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -173,7 +173,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -531,7 +531,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -591,7 +591,7 @@ size=48 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -708,6 +708,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -719,7 +720,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -727,29 +728,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -769,6 +777,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -800,9 +809,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index e4880ad37..03964c60a 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4308 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:19:44 +gem5 executing on e108600-lin, pid 28054 command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 22275010500 because target called exit() +Exiting @ tick 22819771500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 4f7e5b26f..6ed69f426 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022294 # Number of seconds simulated -sim_ticks 22293541500 # Number of ticks simulated -final_tick 22293541500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022820 # Number of seconds simulated +sim_ticks 22819771500 # Number of ticks simulated +final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 223643 # Simulator instruction rate (inst/s) -host_op_rate 223643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62642230 # Simulator tick rate (ticks/s) -host_mem_usage 265292 # Number of bytes of host memory used -host_seconds 355.89 # Real time elapsed on the host +host_inst_rate 186519 # Simulator instruction rate (inst/s) +host_op_rate 186519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53476835 # Simulator tick rate (ticks/s) +host_mem_usage 263708 # Number of bytes of host memory used +host_seconds 426.72 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 413888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10171008 # Number of bytes read from this memory -system.physmem.bytes_read::total 10584896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 413888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 413888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 7372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158922 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165389 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115200 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18565377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 456231147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 474796523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18565377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18565377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 330714615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 330714615 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 330714615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18565377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 456231147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 805511139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165389 # Number of read requests accepted -system.physmem.writeReqs 115200 # Number of write requests accepted -system.physmem.readBursts 165389 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115200 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10584320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7371392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10584896 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7372800 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 414016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10170944 # Number of bytes read from this memory +system.physmem.bytes_read::total 10584960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 414016 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 414016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7372608 # Number of bytes written to this memory +system.physmem.bytes_written::total 7372608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6469 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158921 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165390 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115197 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 18142864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 445707530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 463850394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 18142864 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 18142864 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 323079835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 323079835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 323079835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 18142864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 445707530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 786930228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165390 # Number of read requests accepted +system.physmem.writeReqs 115197 # Number of write requests accepted +system.physmem.readBursts 165390 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115197 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10584512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7370752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10584960 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7372608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10310 # Per bank write bursts -system.physmem.perBankRdBursts::1 10350 # Per bank write bursts +system.physmem.perBankRdBursts::1 10353 # Per bank write bursts system.physmem.perBankRdBursts::2 10221 # Per bank write bursts -system.physmem.perBankRdBursts::3 10037 # Per bank write bursts +system.physmem.perBankRdBursts::3 10036 # Per bank write bursts system.physmem.perBankRdBursts::4 10349 # Per bank write bursts -system.physmem.perBankRdBursts::5 10325 # Per bank write bursts +system.physmem.perBankRdBursts::5 10326 # Per bank write bursts system.physmem.perBankRdBursts::6 9802 # Per bank write bursts -system.physmem.perBankRdBursts::7 10210 # Per bank write bursts -system.physmem.perBankRdBursts::8 10556 # Per bank write bursts -system.physmem.perBankRdBursts::9 10619 # Per bank write bursts +system.physmem.perBankRdBursts::7 10209 # Per bank write bursts +system.physmem.perBankRdBursts::8 10557 # Per bank write bursts +system.physmem.perBankRdBursts::9 10617 # Per bank write bursts system.physmem.perBankRdBursts::10 10516 # Per bank write bursts -system.physmem.perBankRdBursts::11 10224 # Per bank write bursts -system.physmem.perBankRdBursts::12 10277 # Per bank write bursts -system.physmem.perBankRdBursts::13 10556 # Per bank write bursts +system.physmem.perBankRdBursts::11 10223 # Per bank write bursts +system.physmem.perBankRdBursts::12 10279 # Per bank write bursts +system.physmem.perBankRdBursts::13 10557 # Per bank write bursts system.physmem.perBankRdBursts::14 10475 # Per bank write bursts system.physmem.perBankRdBursts::15 10553 # Per bank write bursts system.physmem.perBankWrBursts::0 7167 # Per bank write bursts -system.physmem.perBankWrBursts::1 7278 # Per bank write bursts +system.physmem.perBankWrBursts::1 7277 # Per bank write bursts system.physmem.perBankWrBursts::2 7300 # Per bank write bursts system.physmem.perBankWrBursts::3 7008 # Per bank write bursts -system.physmem.perBankWrBursts::4 7143 # Per bank write bursts -system.physmem.perBankWrBursts::5 7301 # Per bank write bursts +system.physmem.perBankWrBursts::4 7142 # Per bank write bursts +system.physmem.perBankWrBursts::5 7300 # Per bank write bursts system.physmem.perBankWrBursts::6 6892 # Per bank write bursts -system.physmem.perBankWrBursts::7 7161 # Per bank write bursts -system.physmem.perBankWrBursts::8 7241 # Per bank write bursts -system.physmem.perBankWrBursts::9 7068 # Per bank write bursts +system.physmem.perBankWrBursts::7 7158 # Per bank write bursts +system.physmem.perBankWrBursts::8 7240 # Per bank write bursts +system.physmem.perBankWrBursts::9 7069 # Per bank write bursts system.physmem.perBankWrBursts::10 7202 # Per bank write bursts -system.physmem.perBankWrBursts::11 7125 # Per bank write bursts +system.physmem.perBankWrBursts::11 7121 # Per bank write bursts system.physmem.perBankWrBursts::12 7069 # Per bank write bursts system.physmem.perBankWrBursts::13 7390 # Per bank write bursts system.physmem.perBankWrBursts::14 7350 # Per bank write bursts system.physmem.perBankWrBursts::15 7483 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22293510500 # Total gap between requests +system.physmem.totGap 22819740500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165389 # Read request sizes (log2) +system.physmem.readPktSize::6 165390 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115200 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 42842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37971 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115197 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 51469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -145,34 +145,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -194,125 +194,136 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 44806 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 400.727760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 239.628821 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.162466 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13215 29.49% 29.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8315 18.56% 48.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5340 11.92% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2750 6.14% 66.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2605 5.81% 71.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1593 3.56% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1654 3.69% 79.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1106 2.47% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8228 18.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 44806 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7098 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.298957 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.933264 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 317.077516 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7097 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 44648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 402.130084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 240.586732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 367.720381 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13091 29.32% 29.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8315 18.62% 47.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5360 12.01% 59.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2692 6.03% 65.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2549 5.71% 71.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1575 3.53% 75.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1705 3.82% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1125 2.52% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8236 18.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 44648 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7096 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.304961 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.955367 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 317.126574 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7095 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7098 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7098 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.226824 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.209944 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.780993 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6477 91.25% 91.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 22 0.31% 91.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 336 4.73% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 168 2.37% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 66 0.93% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 27 0.38% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7098 # Writes before turning the bus around for reads -system.physmem.totQLat 5599085250 # Total ticks spent queuing -system.physmem.totMemAccLat 8699960250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826900000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33855.88 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7096 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.229989 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.211978 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.816035 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6480 91.32% 91.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 18 0.25% 91.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 334 4.71% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 161 2.27% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 74 1.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 24 0.34% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7096 # Writes before turning the bus around for reads +system.physmem.totQLat 7131716500 # Total ticks spent queuing +system.physmem.totMemAccLat 10232647750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 826915000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43122.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52605.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 474.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 330.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 474.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 330.71 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 61872.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 463.83 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 323.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 463.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 323.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.29 # Data bus utilization in percentage -system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.58 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.72 # Average write queue length when enqueuing -system.physmem.readRowHits 145830 # Number of row buffer hits during reads -system.physmem.writeRowHits 89913 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.05 # Row buffer hit rate for writes -system.physmem.avgGap 79452.55 # Average gap between requests -system.physmem.pageHitRate 84.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 163424520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 89170125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 636441000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 370882800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6110627715 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8015176500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16841729940 # Total energy per rank (pJ) -system.physmem_0.averagePower 755.495604 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 13256940500 # Time in different power states -system.physmem_0.memoryStateTime::REF 744380000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8290987000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 175218120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 95605125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 653343600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 375366960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1456007280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6480752940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7690505250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16926799275 # Total energy per rank (pJ) -system.physmem_1.averagePower 759.311692 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12714890500 # Time in different power states -system.physmem_1.memoryStateTime::REF 744380000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8833037000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16464676 # Number of BP lookups -system.cpu.branchPred.condPredicted 10658312 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 322373 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8884191 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7232535 # Number of BTB hits +system.physmem.busUtil 6.15 # Data bus utilization in percentage +system.physmem.busUtilRead 3.62 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 145971 # Number of row buffer hits during reads +system.physmem.writeRowHits 89923 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes +system.physmem.avgGap 81328.57 # Average gap between requests +system.physmem.pageHitRate 84.07 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153103020 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 81361005 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 582666840 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 298813680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1398920640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1820142240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 87895200 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 2523555300 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1884269760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 2191410645 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11023267740 # Total energy per rank (pJ) +system.physmem_0.averagePower 483.057740 # Core power per rank (mW) +system.physmem_0.totalIdleTime 18596850000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 135529000 # Time in different power states +system.physmem_0.memoryStateTime::REF 594334000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 8155766000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 4906976500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3493009750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 5534156250 # Time in different power states +system.physmem_1.actEnergy 165747960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 88078155 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 598167780 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 302363280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1429652640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1911531480 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 82258560 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 2724848520 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1880202720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 2026371015 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11210189940 # Total energy per rank (pJ) +system.physmem_1.averagePower 491.248979 # Core power per rank (mW) +system.physmem_1.totalIdleTime 18411251500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 119903000 # Time in different power states +system.physmem_1.memoryStateTime::REF 607208000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 7539541250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 4896374750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3681289750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 5975454750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 16458678 # Number of BP lookups +system.cpu.branchPred.condPredicted 10655092 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 320474 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8794743 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7227596 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.409044 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1975403 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3321 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39323 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31540 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7783 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2655 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 82.180866 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1974394 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3324 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 39317 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 31522 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7795 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2656 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22505585 # DTB read hits -system.cpu.dtb.read_misses 226699 # DTB read misses +system.cpu.dtb.read_hits 22495361 # DTB read hits +system.cpu.dtb.read_misses 227004 # DTB read misses system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22732284 # DTB read accesses -system.cpu.dtb.write_hits 15808846 # DTB write hits -system.cpu.dtb.write_misses 44546 # DTB write misses +system.cpu.dtb.read_accesses 22722365 # DTB read accesses +system.cpu.dtb.write_hits 15803250 # DTB write hits +system.cpu.dtb.write_misses 44602 # DTB write misses system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15853392 # DTB write accesses -system.cpu.dtb.data_hits 38314431 # DTB hits -system.cpu.dtb.data_misses 271245 # DTB misses +system.cpu.dtb.write_accesses 15847852 # DTB write accesses +system.cpu.dtb.data_hits 38298611 # DTB hits +system.cpu.dtb.data_misses 271606 # DTB misses system.cpu.dtb.data_acv 22 # DTB access violations -system.cpu.dtb.data_accesses 38585676 # DTB accesses -system.cpu.itb.fetch_hits 13724143 # ITB hits -system.cpu.itb.fetch_misses 29345 # ITB misses +system.cpu.dtb.data_accesses 38570217 # DTB accesses +system.cpu.itb.fetch_hits 13713928 # ITB hits +system.cpu.itb.fetch_misses 29641 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13753488 # ITB accesses +system.cpu.itb.fetch_accesses 13743569 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,101 +337,101 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44587088 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 45639548 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15537600 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105003279 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16464676 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9239478 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27573681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 883330 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4700 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 330450 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 85 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13724143 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187041 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15527632 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104958165 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16458678 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9233512 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 28526394 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 879432 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1335 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 342280 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 91 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13713928 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 186437 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43888428 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.392505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.127693 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 44842161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.340613 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.113400 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24387762 55.57% 55.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1515251 3.45% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1377134 3.14% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1500310 3.42% 65.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4190997 9.55% 75.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1825571 4.16% 79.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669926 1.53% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050385 2.39% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7371092 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25352844 56.54% 56.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1513864 3.38% 59.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1375551 3.07% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1499198 3.34% 66.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4186922 9.34% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1824752 4.07% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 669001 1.49% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1050081 2.34% 83.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7369948 16.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43888428 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369270 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.355015 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14897050 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9776190 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18280655 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 589828 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 344705 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3701787 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98635 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103032848 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312916 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 344705 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15240775 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4552016 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97125 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18511621 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5142186 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102032260 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5895 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 92509 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 354670 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4626637 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61342957 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123044735 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122725402 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319332 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44842161 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.360623 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.299720 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14899514 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10738608 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18272960 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 588305 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 342774 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3699945 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98528 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 102994976 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312859 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 342774 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15240271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5029380 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 97820 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18506228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5625688 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102003977 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6871 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 88609 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 422499 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5043111 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61324692 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123005722 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122686459 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 319262 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8796076 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5684 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5736 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2358572 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23134576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16358313 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246652 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 504576 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90719727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5556 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88603709 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 68043 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11133526 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4439018 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 973 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43888428 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018840 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.245634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8777811 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5683 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5735 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2339310 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23131891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16353716 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1249387 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 502474 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90699211 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88573949 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67838 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11113012 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4439512 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 975 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44842161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.975238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.240795 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17434377 39.72% 39.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5720394 13.03% 52.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5103914 11.63% 64.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4383916 9.99% 74.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4317842 9.84% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2637316 6.01% 90.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1940633 4.42% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1378295 3.14% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 971741 2.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18402096 41.04% 41.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5711089 12.74% 53.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5105714 11.39% 65.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4382501 9.77% 74.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4313150 9.62% 84.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2637224 5.88% 90.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1940283 4.33% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1377321 3.07% 97.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 972783 2.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43888428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44842161 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 241284 9.57% 9.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 241463 9.57% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available @@ -449,19 +460,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1166228 46.24% 55.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1114848 44.20% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1168337 46.29% 55.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1114013 44.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49379489 55.73% 55.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44005 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49366935 55.74% 55.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43991 0.05% 55.78% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121171 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 92 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120707 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 62 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39092 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued @@ -483,82 +494,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22899221 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15999870 18.06% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22887844 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15994084 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88603709 # Type of FU issued -system.cpu.iq.rate 1.987206 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2522360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028468 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223074890 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101458980 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86835527 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611359 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420488 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299878 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90820238 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305831 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1672227 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued +system.cpu.iq.rate 1.940728 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2523813 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028494 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223970382 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611328 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90791946 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305816 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2857938 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5878 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20874 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1744936 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5856 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20836 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740339 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3021 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 200758 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3017 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 190756 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 344705 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1315985 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2729229 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100214269 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 118431 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23134576 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16358313 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5556 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3898 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2727794 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20874 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 113179 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 152389 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 265568 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87909421 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22732927 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 694288 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 342774 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1435868 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3107979 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100192818 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 116708 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23131891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16353716 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5558 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3773 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3106841 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20836 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 111267 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 152585 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 263852 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87883972 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22722991 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 689977 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9488986 # number of nop insts executed -system.cpu.iew.exec_refs 38586655 # number of memory reference insts executed -system.cpu.iew.exec_branches 15119960 # Number of branches executed -system.cpu.iew.exec_stores 15853728 # Number of stores executed -system.cpu.iew.exec_rate 1.971634 # Inst execution rate -system.cpu.iew.wb_sent 87537444 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87135405 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33842966 # num instructions producing a value -system.cpu.iew.wb_consumers 44247648 # num instructions consuming a value -system.cpu.iew.wb_rate 1.954274 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764853 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8653815 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9488049 # number of nop insts executed +system.cpu.iew.exec_refs 38571182 # number of memory reference insts executed +system.cpu.iew.exec_branches 15118040 # Number of branches executed +system.cpu.iew.exec_stores 15848191 # Number of stores executed +system.cpu.iew.exec_rate 1.925610 # Inst execution rate +system.cpu.iew.wb_sent 87519959 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87118018 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33843453 # num instructions producing a value +system.cpu.iew.wb_consumers 44250497 # num instructions consuming a value +system.cpu.iew.wb_rate 1.908827 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764815 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8632074 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 225413 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42617548 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.072871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.885939 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 223532 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43575084 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.027321 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.870724 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21149374 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6281932 14.74% 64.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2908445 6.82% 71.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1738602 4.08% 75.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1681485 3.95% 79.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1121192 2.63% 81.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1200701 2.82% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 796598 1.87% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5739219 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22117259 50.76% 50.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6277727 14.41% 65.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2900957 6.66% 71.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1737731 3.99% 75.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1677521 3.85% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1124025 2.58% 82.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1202727 2.76% 85.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 795829 1.83% 86.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5741308 13.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42617548 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43575084 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -604,471 +615,471 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5739219 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 132555474 # The number of ROB reads -system.cpu.rob.rob_writes 195263120 # The number of ROB writes -system.cpu.timesIdled 45271 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 698660 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5741308 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 133489180 # The number of ROB reads +system.cpu.rob.rob_writes 195215826 # The number of ROB writes +system.cpu.timesIdled 45373 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 797387 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.560197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.560197 # CPI: Total CPI of All Threads -system.cpu.ipc 1.785085 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.785085 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116363135 # number of integer regfile reads -system.cpu.int_regfile_writes 57669565 # number of integer regfile writes -system.cpu.fp_regfile_reads 255561 # number of floating regfile reads -system.cpu.fp_regfile_writes 240404 # number of floating regfile writes -system.cpu.misc_regfile_reads 38263 # number of misc regfile reads +system.cpu.cpi 0.573421 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.573421 # CPI: Total CPI of All Threads +system.cpu.ipc 1.743921 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.743921 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116327818 # number of integer regfile reads +system.cpu.int_regfile_writes 57658172 # number of integer regfile writes +system.cpu.fp_regfile_reads 255578 # number of floating regfile reads +system.cpu.fp_regfile_writes 240399 # number of floating regfile writes +system.cpu.misc_regfile_reads 38260 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201400 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.443451 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33984025 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205496 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.375603 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 232048500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.443451 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993761 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993761 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 201413 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.948439 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33978122 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205509 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.336418 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244590500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.948439 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993640 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2679 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1341 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2488 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1533 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70817108 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70817108 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20422994 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20422994 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13560978 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13560978 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 53 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 53 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33983972 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33983972 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33983972 # number of overall hits -system.cpu.dcache.overall_hits::total 33983972 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269382 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269382 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052399 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052399 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1321781 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321781 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321781 # number of overall misses -system.cpu.dcache.overall_misses::total 1321781 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18043068500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18043068500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88421559159 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88421559159 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106464627659 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106464627659 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106464627659 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106464627659 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20692376 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20692376 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70808789 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70808789 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 20418812 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20418812 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13559258 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13559258 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33978070 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33978070 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33978070 # number of overall hits +system.cpu.dcache.overall_hits::total 33978070 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269399 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269399 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1054119 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1054119 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1323518 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1323518 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1323518 # number of overall misses +system.cpu.dcache.overall_misses::total 1323518 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19371317500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19371317500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 94432641988 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 94432641988 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113803959488 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113803959488 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113803959488 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113803959488 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20688211 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20688211 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 53 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35305753 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35305753 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35305753 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35305753 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013018 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013018 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072016 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072016 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037438 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037438 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037438 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037438 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66979.488236 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66979.488236 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84019.045209 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84019.045209 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80546.344409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80546.344409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80546.344409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6874865 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 279 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 86609 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35301588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35301588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35301588 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35301588 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.013022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072134 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072134 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037492 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037492 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037492 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037492 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71905.677081 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71905.677081 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89584.422620 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89584.422620 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 85985.955225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 85985.955225 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7415690 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 299 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 82797 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.378182 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 139.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168502 # number of writebacks -system.cpu.dcache.writebacks::total 168502 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207279 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207279 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 909006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 909006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1116285 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1116285 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1116285 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1116285 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143393 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143393 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205496 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205496 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205496 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205496 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3336459000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3336459000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14128429272 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14128429272 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17464888272 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17464888272 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17464888272 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17464888272 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009812 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005820 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005820 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005820 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53724.602676 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53724.602676 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98529.421046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98529.421046 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84988.945147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84988.945147 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90436 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.490065 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13619166 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92484 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.259699 # 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Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 13608920 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13608920 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13608920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13608920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13608920 # number of overall hits +system.cpu.icache.overall_hits::total 13608920 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105006 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105006 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105006 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105006 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105006 # number of overall misses +system.cpu.icache.overall_misses::total 105006 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2088801499 # 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number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007657 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007657 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007657 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007657 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007657 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007657 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19892.210912 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19892.210912 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19892.210912 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19892.210912 # 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Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 422062 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 167642 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.517639 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4859656000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 722.364840 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1777.470792 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29364.139876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.022045 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.054244 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.896122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.972411 # 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number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 92506 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 92506 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1693618500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1693618500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1693618500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1693618500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1693618500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1693618500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006745 # 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number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2881682000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2881682000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 582406000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16506565000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17088971000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 582406000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16506565000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17088971000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912242 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069936 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452666 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452666 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069936 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773358 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95321.035693 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95321.035693 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74855.828695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74855.828695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 92517.395326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 92517.395326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74855.828695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94825.112319 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94044.162283 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589817 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291836 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912264 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912264 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069941 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452498 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452498 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.554975 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.554975 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 104153.827925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 104153.827925 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90016.383308 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90016.383308 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102529.068526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102529.068526 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 589885 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 291870 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4239 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 4237 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4237 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52571 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92485 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887797 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11706880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23935872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35642752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134874 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7372864 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 432855 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009793 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098475 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 154618 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 283708 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 90457 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 52577 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 92506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62113 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275468 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612431 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 887899 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11709568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23937216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 35646784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134872 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 7372672 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 432887 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009788 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098448 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 428616 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4239 0.98% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 428650 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4237 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432855 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553846500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138734483 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 432887 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 553909500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 138764985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308248491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308272981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130746 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_single_requests 130745 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22293541500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34578 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115200 # Transaction distribution -system.membus.trans_dist::CleanEvict 15546 # Transaction distribution -system.membus.trans_dist::ReadExReq 130811 # Transaction distribution -system.membus.trans_dist::ReadExResp 130811 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34578 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461524 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 461524 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17957696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 34575 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115197 # Transaction distribution +system.membus.trans_dist::CleanEvict 15548 # Transaction distribution +system.membus.trans_dist::ReadExReq 130815 # Transaction distribution +system.membus.trans_dist::ReadExResp 130815 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461525 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 461525 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17957568 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165389 # Request fanout histogram +system.membus.snoop_fanout::samples 165390 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 165390 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165389 # Request fanout histogram -system.membus.reqLayer0.occupancy 780841500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 854544750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.8 # Layer utilization (%) +system.membus.snoop_fanout::total 165390 # Request fanout histogram +system.membus.reqLayer0.occupancy 779827500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 851966000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini index 7debe9727..3119a9994 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -151,7 +151,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -631,7 +631,7 @@ opClass=InstPrefetch [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -691,7 +691,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -763,7 +763,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -880,6 +880,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -891,7 +892,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -899,29 +900,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -941,6 +949,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -950,7 +959,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -972,9 +981,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout index 9e5ee29fe..9fd7ec0be 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 15:05:27 -gem5 executing on e108600-lin, pid 24209 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:42:59 +gem5 executing on e108600-lin, pid 17323 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 58768125500 because target called exit() +Exiting @ tick 60130734500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 7abf225fd..feef465f0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058750 # Number of seconds simulated -sim_ticks 58750410500 # Number of ticks simulated -final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060131 # Number of seconds simulated +sim_ticks 60130734500 # Number of ticks simulated +final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179920 # Simulator instruction rate (inst/s) -host_op_rate 230092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 149057017 # Simulator tick rate (ticks/s) -host_mem_usage 281832 # Number of bytes of host memory used -host_seconds 394.15 # Real time elapsed on the host +host_inst_rate 142105 # Simulator instruction rate (inst/s) +host_op_rate 181732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 120494644 # Simulator tick rate (ticks/s) +host_mem_usage 279144 # Number of bytes of host memory used +host_seconds 499.03 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory @@ -26,27 +26,27 @@ system.physmem.num_reads::cpu.data 124041 # Nu system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 128515 # Number of read requests accepted system.physmem.writeReqs 86552 # Number of write requests accepted system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8086 # Per bank write bursts @@ -57,24 +57,24 @@ system.physmem.perBankRdBursts::4 8301 # Pe system.physmem.perBankRdBursts::5 8413 # Per bank write bursts system.physmem.perBankRdBursts::6 8070 # Per bank write bursts system.physmem.perBankRdBursts::7 7917 # Per bank write bursts -system.physmem.perBankRdBursts::8 8053 # Per bank write bursts -system.physmem.perBankRdBursts::9 7612 # Per bank write bursts +system.physmem.perBankRdBursts::8 8054 # Per bank write bursts +system.physmem.perBankRdBursts::9 7613 # Per bank write bursts system.physmem.perBankRdBursts::10 7771 # Per bank write bursts system.physmem.perBankRdBursts::11 7825 # Per bank write bursts system.physmem.perBankRdBursts::12 7888 # Per bank write bursts system.physmem.perBankRdBursts::13 7870 # Per bank write bursts system.physmem.perBankRdBursts::14 7981 # Per bank write bursts system.physmem.perBankRdBursts::15 7974 # Per bank write bursts -system.physmem.perBankWrBursts::0 5399 # Per bank write bursts +system.physmem.perBankWrBursts::0 5400 # Per bank write bursts system.physmem.perBankWrBursts::1 5549 # Per bank write bursts -system.physmem.perBankWrBursts::2 5476 # Per bank write bursts -system.physmem.perBankWrBursts::3 5348 # Per bank write bursts +system.physmem.perBankWrBursts::2 5475 # Per bank write bursts +system.physmem.perBankWrBursts::3 5349 # Per bank write bursts system.physmem.perBankWrBursts::4 5387 # Per bank write bursts -system.physmem.perBankWrBursts::5 5588 # Per bank write bursts +system.physmem.perBankWrBursts::5 5586 # Per bank write bursts system.physmem.perBankWrBursts::6 5325 # Per bank write bursts system.physmem.perBankWrBursts::7 5260 # Per bank write bursts system.physmem.perBankWrBursts::8 5187 # Per bank write bursts -system.physmem.perBankWrBursts::9 5136 # Per bank write bursts +system.physmem.perBankWrBursts::9 5135 # Per bank write bursts system.physmem.perBankWrBursts::10 5306 # Per bank write bursts system.physmem.perBankWrBursts::11 5279 # Per bank write bursts system.physmem.perBankWrBursts::12 5541 # Per bank write bursts @@ -83,7 +83,7 @@ system.physmem.perBankWrBursts::14 5706 # Pe system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58750379000 # Total gap between requests +system.physmem.totGap 60130703000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -98,11 +98,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86552 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,104 +194,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads -system.physmem.totQLat 1552277750 # Total ticks spent queuing -system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads +system.physmem.totQLat 3048956750 # Total ticks spent queuing +system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.83 # Data bus utilization in percentage -system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.79 # Data bus utilization in percentage +system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing -system.physmem.readRowHits 112029 # Number of row buffer hits during reads -system.physmem.writeRowHits 70027 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes -system.physmem.avgGap 273172.45 # Average gap between requests -system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ) -system.physmem_0.averagePower 705.717335 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ) -system.physmem_1.averagePower 704.382975 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827613 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits +system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing +system.physmem.readRowHits 112228 # Number of row buffer hits during reads +system.physmem.writeRowHits 69923 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes +system.physmem.avgGap 279590.56 # Average gap between requests +system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ) +system.physmem_0.averagePower 386.883743 # Core power per rank (mW) +system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states +system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ) +system.physmem_1.averagePower 383.200220 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14827796 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits. +system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -321,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -412,16 +423,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117500821 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120261469 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.656921 # CPI: cycles per instruction -system.cpu.ipc 0.603529 # IPC: instructions per cycle +system.cpu.cpi 1.695850 # CPI: cycles per instruction +system.cpu.ipc 0.589675 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -457,106 +468,106 @@ system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked -system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked +system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 156451 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits -system.cpu.dcache.overall_hits::total 42605646 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses -system.cpu.dcache.overall_misses::total 299891 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits +system.cpu.dcache.overall_hits::total 42605457 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses +system.cpu.dcache.overall_misses::total 299788 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks system.cpu.dcache.writebacks::total 128145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses @@ -567,92 +578,92 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136566 system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 43545 # number of replacements -system.cpu.icache.tags.tagsinuse 1854.190293 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25047618 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 549.446509 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1854.190293 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.905366 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.905366 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits -system.cpu.icache.overall_hits::total 25047618 # number of overall hits +system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits +system.cpu.icache.overall_hits::total 25048343 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses system.cpu.icache.overall_misses::total 45588 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 918433000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 918433000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 918433000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 918433000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 918433000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 918433000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20146.376239 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20146.376239 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20146.376239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20146.376239 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -667,88 +678,88 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 45588 system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 97176 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31328.460689 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 268173 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.063758 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 10596662000 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.954966 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13615 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17003 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12834 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17840 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) @@ -767,28 +778,28 @@ system.cpu.l2cache.overall_accesses::cpu.data 160547 system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098447 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098447 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098425 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098425 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098447 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098425 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.623810 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098447 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.623805 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # 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number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses @@ -821,18 +832,18 @@ system.cpu.l2cache.demand_mshr_misses::total 128516 system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7167902500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7167902500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 323146000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 323146000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1736095500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1736095500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 323146000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8903998000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9227144000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 323146000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8903998000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9227144000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses @@ -847,25 +858,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution @@ -895,7 +906,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 2 # system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) @@ -905,7 +916,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 26198 # Transaction distribution system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution system.membus.trans_dist::CleanEvict 7237 # Transaction distribution @@ -928,9 +939,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 128515 # Request fanout histogram -system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 8b084cbe5..e2ac8f237 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -172,7 +172,7 @@ useIndirect=true [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -534,7 +534,7 @@ pipelined=true [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -666,7 +666,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -813,6 +813,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -824,7 +825,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -832,29 +833,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -874,6 +882,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -883,7 +892,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -905,9 +914,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 1832c357f..77b319c20 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:10:34 -gem5 executing on e108600-lin, pid 12236 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:59:48 +gem5 executing on e108600-lin, pid 17544 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 33524756000 because target called exit() +Exiting @ tick 37982056000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 7d5e42cd5..6270a4a24 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.037283 # Number of seconds simulated -sim_ticks 37283333000 # Number of ticks simulated -final_tick 37283333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037982 # Number of seconds simulated +sim_ticks 37982056000 # Number of ticks simulated +final_tick 37982056000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125888 # Simulator instruction rate (inst/s) -host_op_rate 160996 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66191855 # Simulator tick rate (ticks/s) -host_mem_usage 284264 # Number of bytes of host memory used -host_seconds 563.26 # Real time elapsed on the host +host_inst_rate 105525 # Simulator instruction rate (inst/s) +host_op_rate 134954 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56525025 # Simulator tick rate (ticks/s) +host_mem_usage 282344 # Number of bytes of host memory used +host_seconds 671.95 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2379328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5690752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6174592 # Number of bytes read from this memory -system.physmem.bytes_read::total 14244672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2379328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2379328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6224768 # Number of bytes written to this memory -system.physmem.bytes_written::total 6224768 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 37177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 88918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96478 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222573 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97262 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97262 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 63817470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 152635281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 165612661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 382065412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 63817470 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 63817470 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166958464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166958464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166958464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 63817470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 152635281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 165612661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 549023876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222574 # Number of read requests accepted -system.physmem.writeReqs 97262 # Number of write requests accepted -system.physmem.readBursts 222574 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97262 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14235136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 6223360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14244736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6224768 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2372544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5696640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6178368 # Number of bytes read from this memory +system.physmem.bytes_read::total 14247552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2372544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2372544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6227072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6227072 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 37071 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 89010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222618 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97298 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 62464865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 149982402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 162665444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 375112711 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 62464865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 62464865 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 163947734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 163947734 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 163947734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 62464865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 149982402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 162665444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 539060445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222619 # Number of read requests accepted +system.physmem.writeReqs 97298 # Number of write requests accepted +system.physmem.readBursts 222619 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97298 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14237568 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue +system.physmem.bytesWritten 6225984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14247616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6227072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9684 # Per bank write bursts -system.physmem.perBankRdBursts::1 9951 # Per bank write bursts -system.physmem.perBankRdBursts::2 12571 # Per bank write bursts -system.physmem.perBankRdBursts::3 25345 # Per bank write bursts -system.physmem.perBankRdBursts::4 17391 # Per bank write bursts -system.physmem.perBankRdBursts::5 22070 # Per bank write bursts -system.physmem.perBankRdBursts::6 11722 # Per bank write bursts -system.physmem.perBankRdBursts::7 14054 # Per bank write bursts -system.physmem.perBankRdBursts::8 11726 # Per bank write bursts -system.physmem.perBankRdBursts::9 15447 # Per bank write bursts -system.physmem.perBankRdBursts::10 11755 # Per bank write bursts -system.physmem.perBankRdBursts::11 11322 # Per bank write bursts -system.physmem.perBankRdBursts::12 9441 # Per bank write bursts -system.physmem.perBankRdBursts::13 9563 # Per bank write bursts -system.physmem.perBankRdBursts::14 9879 # Per bank write bursts -system.physmem.perBankRdBursts::15 20503 # Per bank write bursts -system.physmem.perBankWrBursts::0 5981 # Per bank write bursts -system.physmem.perBankWrBursts::1 6205 # Per bank write bursts -system.physmem.perBankWrBursts::2 6090 # Per bank write bursts -system.physmem.perBankWrBursts::3 6159 # Per bank write bursts -system.physmem.perBankWrBursts::4 6110 # Per bank write bursts -system.physmem.perBankWrBursts::5 6252 # Per bank write bursts -system.physmem.perBankWrBursts::6 5998 # Per bank write bursts -system.physmem.perBankWrBursts::7 5984 # Per bank write bursts -system.physmem.perBankWrBursts::8 5961 # Per bank write bursts -system.physmem.perBankWrBursts::9 6093 # Per bank write bursts -system.physmem.perBankWrBursts::10 6222 # Per bank write bursts -system.physmem.perBankWrBursts::11 5895 # Per bank write bursts -system.physmem.perBankWrBursts::12 6037 # Per bank write bursts -system.physmem.perBankWrBursts::13 6052 # Per bank write bursts -system.physmem.perBankWrBursts::14 6175 # Per bank write bursts -system.physmem.perBankWrBursts::15 6026 # Per bank write bursts +system.physmem.perBankRdBursts::0 9655 # Per bank write bursts +system.physmem.perBankRdBursts::1 9974 # Per bank write bursts +system.physmem.perBankRdBursts::2 12579 # Per bank write bursts +system.physmem.perBankRdBursts::3 25363 # Per bank write bursts +system.physmem.perBankRdBursts::4 17343 # Per bank write bursts +system.physmem.perBankRdBursts::5 22132 # Per bank write bursts +system.physmem.perBankRdBursts::6 11760 # Per bank write bursts +system.physmem.perBankRdBursts::7 14137 # Per bank write bursts +system.physmem.perBankRdBursts::8 11660 # Per bank write bursts +system.physmem.perBankRdBursts::9 15453 # Per bank write bursts +system.physmem.perBankRdBursts::10 11698 # Per bank write bursts +system.physmem.perBankRdBursts::11 11338 # Per bank write bursts +system.physmem.perBankRdBursts::12 9437 # Per bank write bursts +system.physmem.perBankRdBursts::13 9564 # Per bank write bursts +system.physmem.perBankRdBursts::14 9858 # Per bank write bursts +system.physmem.perBankRdBursts::15 20511 # Per bank write bursts +system.physmem.perBankWrBursts::0 5992 # Per bank write bursts +system.physmem.perBankWrBursts::1 6239 # Per bank write bursts +system.physmem.perBankWrBursts::2 6121 # Per bank write bursts +system.physmem.perBankWrBursts::3 6129 # Per bank write bursts +system.physmem.perBankWrBursts::4 6098 # Per bank write bursts +system.physmem.perBankWrBursts::5 6229 # Per bank write bursts +system.physmem.perBankWrBursts::6 6018 # Per bank write bursts +system.physmem.perBankWrBursts::7 5980 # Per bank write bursts +system.physmem.perBankWrBursts::8 5938 # Per bank write bursts +system.physmem.perBankWrBursts::9 6095 # Per bank write bursts +system.physmem.perBankWrBursts::10 6202 # Per bank write bursts +system.physmem.perBankWrBursts::11 5916 # Per bank write bursts +system.physmem.perBankWrBursts::12 6046 # Per bank write bursts +system.physmem.perBankWrBursts::13 6090 # Per bank write bursts +system.physmem.perBankWrBursts::14 6173 # Per bank write bursts +system.physmem.perBankWrBursts::15 6015 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37283321500 # Total gap between requests +system.physmem.totGap 37982044500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222574 # Read request sizes (log2) +system.physmem.readPktSize::6 222619 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97262 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 113358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61350 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5097 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97298 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 111989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15764 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -149,34 +149,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -198,109 +198,120 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132565 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 154.319345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.621145 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 210.186270 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82651 62.35% 62.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32256 24.33% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6354 4.79% 91.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2721 2.05% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1163 0.88% 94.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1002 0.76% 95.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 846 0.64% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 812 0.61% 96.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4760 3.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132565 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.864488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 211.288279 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5866 99.86% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 7 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 132891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 153.980270 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.520664 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 209.589027 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82855 62.35% 62.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32511 24.46% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6209 4.67% 91.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2728 2.05% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1195 0.90% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 994 0.75% 95.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 885 0.67% 95.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 776 0.58% 96.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4738 3.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132891 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.813870 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.295819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5876 99.88% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5874 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.554307 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512747 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.243213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4672 79.54% 79.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 38 0.65% 80.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 729 12.41% 92.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 209 3.56% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 107 1.82% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 58 0.99% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 31 0.53% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 16 0.27% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 11 0.19% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5874 # Writes before turning the bus around for reads -system.physmem.totQLat 7261518854 # Total ticks spent queuing -system.physmem.totMemAccLat 11431968854 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1112120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32647.19 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.535951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.496117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.216118 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4707 80.01% 80.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 47 0.80% 80.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 703 11.95% 92.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 205 3.48% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 109 1.85% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 61 1.04% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 33 0.56% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.19% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads +system.physmem.totQLat 8417974819 # Total ticks spent queuing +system.physmem.totMemAccLat 12589137319 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1112310000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37840.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51397.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 166.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 382.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 166.96 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56590.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 163.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 375.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 163.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.29 # Data bus utilization in percentage -system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing -system.physmem.readRowHits 157163 # Number of row buffer hits during reads -system.physmem.writeRowHits 29925 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.77 # Row buffer hit rate for writes -system.physmem.avgGap 116570.12 # Average gap between requests -system.physmem.pageHitRate 58.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 537077520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 293048250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 957496800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 315958320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 23206024395 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2012333250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 29756923815 # Total energy per rank (pJ) -system.physmem_0.averagePower 798.183082 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3201879547 # Time in different power states -system.physmem_0.memoryStateTime::REF 1244880000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32834079203 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 464871960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 253650375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 777051600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313949520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2434985280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 21592790730 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3427453500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 29264752965 # Total energy per rank (pJ) -system.physmem_1.averagePower 784.981262 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 5568954615 # Time in different power states -system.physmem_1.memoryStateTime::REF 1244880000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30467009135 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17068882 # Number of BP lookups -system.cpu.branchPred.condPredicted 11456187 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 597693 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9279962 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7373647 # Number of BTB hits +system.physmem.busUtil 4.21 # Data bus utilization in percentage +system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing +system.physmem.readRowHits 157076 # Number of row buffer hits during reads +system.physmem.writeRowHits 29766 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes +system.physmem.avgGap 118724.68 # Average gap between requests +system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 508332300 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 270162255 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 877813020 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254767320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3007433520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2937544590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74566560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 13007568150 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1007588640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 71626485 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 22017862440 # Total energy per rank (pJ) +system.physmem_0.averagePower 579.691165 # Core power per rank (mW) +system.physmem_0.totalIdleTime 31344656336 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 41004063 # Time in different power states +system.physmem_0.memoryStateTime::REF 1272480000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 195565250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2624595348 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5323818601 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28524592738 # Time in different power states +system.physmem_1.actEnergy 440580840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 234159090 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 710558520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 253039500 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2889422640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2771748120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 73304160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11932439280 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1384694400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 508589940 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 21198847170 # Total energy per rank (pJ) +system.physmem_1.averagePower 558.127949 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31712588164 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 50452548 # Time in different power states +system.physmem_1.memoryStateTime::REF 1222746000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1938473750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3605935527 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4996269288 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26168178887 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17071043 # Number of BP lookups +system.cpu.branchPred.condPredicted 11458506 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 598065 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9277652 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7374059 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.457728 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1854916 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101589 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 233217 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195584 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37633 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22185 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 79.481953 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1854771 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101571 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 233347 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 194967 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 38380 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22266 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +341,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +371,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +401,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,96 +432,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 74566667 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 75964113 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5541341 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87099155 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17068882 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9424147 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 65038748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1222021 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 11659 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30739 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22432357 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69340 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 71233545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.545306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.327706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5537723 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87105546 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17071043 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9423797 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 66074321 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1222765 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 12043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 60 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 33616 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22433583 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69302 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 72269145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.523281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.330897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 26059108 36.58% 36.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8166381 11.46% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9112889 12.79% 60.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27895167 39.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27092588 37.49% 37.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8164913 11.30% 48.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9113637 12.61% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27898007 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 71233545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.228908 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.168071 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8928507 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 25221623 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30949867 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5689167 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 444381 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3134053 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168503 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100299686 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2798262 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 444381 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13572247 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10675080 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 842433 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31772787 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13926617 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98328841 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 859440 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4124148 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 69439 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4596367 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5265270 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103255092 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453545884 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114277398 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 716 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 72269145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224725 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.146667 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8914938 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26268747 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30971085 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5669704 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 444671 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3134143 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168562 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100303161 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2799230 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 444671 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13550474 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11467047 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 876029 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31784130 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14146794 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98330583 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 860090 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4210253 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 70388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4670257 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5435231 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103259286 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453553071 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114279094 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9625723 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18974 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19002 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12839389 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24155878 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21759886 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1433320 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2321800 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97398916 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34841 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94478155 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 593843 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6751150 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17960313 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1055 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 71233545 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.326316 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.168839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9629917 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18998 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19022 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12803731 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24155645 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21760500 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1435489 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2293932 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97400499 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34856 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94484787 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 595355 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6752748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17957034 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1070 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 72269145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.307401 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.171287 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23112455 32.45% 32.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17441476 24.48% 56.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17040128 23.92% 80.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11602976 16.29% 97.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2035055 2.86% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1455 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24146655 33.41% 33.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17449315 24.14% 57.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17027031 23.56% 81.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11604628 16.06% 97.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2040054 2.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1462 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 71233545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72269145 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6731709 22.63% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 38 0.00% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6736684 22.63% 22.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 37 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.63% # attempts to use FU when none available @@ -538,13 +549,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11081856 37.26% 59.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11930481 40.11% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11088474 37.25% 59.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11940322 40.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49303920 52.19% 52.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86563 0.09% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49305598 52.18% 52.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86530 0.09% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued @@ -565,89 +576,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 11 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 18 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23954982 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21132627 22.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23958877 25.36% 77.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21133721 22.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94478155 # Type of FU issued -system.cpu.iq.rate 1.267029 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29744084 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314825 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 290527434 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104196109 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93201296 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 348 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 616 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124222040 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1368179 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94484787 # Type of FU issued +system.cpu.iq.rate 1.243808 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29765517 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315030 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 291599265 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 104199326 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93203450 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 326 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124250121 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 183 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368397 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1289616 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2048 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1289383 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2091 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11973 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1204148 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1204762 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 144864 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185613 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 147075 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 188044 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 444381 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 624509 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1115710 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97447803 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 444671 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 622988 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1195662 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97449431 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24155878 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21759886 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18921 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1617 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1111435 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 24155645 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21760500 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18936 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1589 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1191442 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 11973 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 249911 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221890 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 471801 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93685311 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23691817 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 792844 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 249986 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 222081 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 472067 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93691189 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23695668 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 793598 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 14046 # number of nop insts executed -system.cpu.iew.exec_refs 44616394 # number of memory reference insts executed -system.cpu.iew.exec_branches 14207133 # Number of branches executed -system.cpu.iew.exec_stores 20924577 # Number of stores executed -system.cpu.iew.exec_rate 1.256397 # Inst execution rate -system.cpu.iew.wb_sent 93308677 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93201392 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44951021 # num instructions producing a value -system.cpu.iew.wb_consumers 76633881 # num instructions consuming a value -system.cpu.iew.wb_rate 1.249907 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586569 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5894305 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 14076 # number of nop insts executed +system.cpu.iew.exec_refs 44621004 # number of memory reference insts executed +system.cpu.iew.exec_branches 14207535 # Number of branches executed +system.cpu.iew.exec_stores 20925336 # Number of stores executed +system.cpu.iew.exec_rate 1.233361 # Inst execution rate +system.cpu.iew.wb_sent 93310594 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93203542 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44951761 # num instructions producing a value +system.cpu.iew.wb_consumers 76639550 # num instructions consuming a value +system.cpu.iew.wb_rate 1.226942 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586535 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5895620 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 431064 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 70277782 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.290424 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.118209 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 431354 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 71312758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.271696 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.107515 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 36842990 52.42% 52.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16674938 23.73% 76.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4291723 6.11% 82.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4149088 5.90% 88.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947878 2.77% 90.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1240751 1.77% 92.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 737656 1.05% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580756 0.83% 94.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3812002 5.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 37859507 53.09% 53.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16683603 23.39% 76.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4297164 6.03% 82.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4156384 5.83% 88.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1956005 2.74% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1240140 1.74% 92.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 732437 1.03% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 578410 0.81% 94.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3809108 5.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 70277782 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71312758 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -693,552 +704,552 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3812002 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 163022945 # The number of ROB reads -system.cpu.rob.rob_writes 194122181 # The number of ROB writes -system.cpu.timesIdled 54257 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3333122 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3809108 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 164062130 # The number of ROB reads +system.cpu.rob.rob_writes 194125448 # The number of ROB writes +system.cpu.timesIdled 54252 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3694968 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.051603 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.051603 # CPI: Total CPI of All Threads -system.cpu.ipc 0.950930 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.950930 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101976703 # number of integer regfile reads -system.cpu.int_regfile_writes 56611271 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.fp_regfile_writes 48 # number of floating regfile writes -system.cpu.cc_regfile_reads 345090037 # number of cc regfile reads -system.cpu.cc_regfile_writes 38758670 # number of cc regfile writes -system.cpu.misc_regfile_reads 44101489 # number of misc regfile reads +system.cpu.cpi 1.071311 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.071311 # CPI: Total CPI of All Threads +system.cpu.ipc 0.933436 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.933436 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101982930 # number of integer regfile reads +system.cpu.int_regfile_writes 56612163 # number of integer regfile writes +system.cpu.fp_regfile_reads 58 # number of floating regfile reads +system.cpu.fp_regfile_writes 45 # number of floating regfile writes +system.cpu.cc_regfile_reads 345107562 # number of cc regfile reads +system.cpu.cc_regfile_writes 38759661 # number of cc regfile writes +system.cpu.misc_regfile_reads 44102170 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484862 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.874566 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40338135 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485374 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.107325 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 151605500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.874566 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997802 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997802 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484814 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.868965 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40339815 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485326 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.119007 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 154595500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.868965 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84467396 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84467396 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21414103 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21414103 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18832546 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18832546 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60212 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60212 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15310 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15310 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84466838 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84466838 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21417711 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21417711 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18830642 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18830642 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15309 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15309 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40246649 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40246649 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40306861 # number of overall hits -system.cpu.dcache.overall_hits::total 40306861 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 566310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 566310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1017355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1017355 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68643 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68643 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 613 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 613 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1583665 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1583665 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1652308 # number of overall misses -system.cpu.dcache.overall_misses::total 1652308 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13581553500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13581553500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13903205430 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13903205430 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5738500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5738500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27484758930 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27484758930 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27484758930 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27484758930 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21980413 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21980413 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40248353 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40248353 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40308541 # number of overall hits +system.cpu.dcache.overall_hits::total 40308541 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 562442 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 562442 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1019259 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1019259 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68672 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68672 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 614 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 614 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1581701 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1581701 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1650373 # number of overall misses +system.cpu.dcache.overall_misses::total 1650373 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14412910000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14412910000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14258561428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14258561428 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5705500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5705500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28671471428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28671471428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28671471428 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28671471428 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21980153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21980153 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128860 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128860 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41830314 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41830314 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41959169 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41959169 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051252 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051252 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532715 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532715 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038498 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038498 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037859 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037859 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039379 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039379 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23982.542247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23982.542247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13666.031454 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13666.031454 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9361.337684 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9361.337684 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17355.159664 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17355.159664 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16634.161990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16634.161990 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2820837 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 130956 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 21.540342 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484862 # number of writebacks -system.cpu.dcache.writebacks::total 484862 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267183 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 267183 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868792 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 868792 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 613 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 613 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135975 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135975 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135975 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135975 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299127 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299127 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148563 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148563 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37696 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37696 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447690 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447690 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485386 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485386 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6671017500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6671017500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2276896471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2276896471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1910092000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1910092000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947913971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8947913971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10858005971 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10858005971 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013609 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013609 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41830054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41830054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41958914 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41958914 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025589 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025589 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051348 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051348 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532919 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532919 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038561 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038561 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037813 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037813 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.593395 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.593395 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13989.144494 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13989.144494 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9292.345277 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9292.345277 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18126.985712 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18126.985712 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17372.722062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17372.722062 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2956958 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131265 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.526629 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484814 # number of writebacks +system.cpu.dcache.writebacks::total 484814 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263368 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 263368 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870698 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870698 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 614 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 614 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1134066 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1134066 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1134066 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1134066 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299074 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299074 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148561 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148561 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37704 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37704 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447635 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447635 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485339 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485339 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7124794500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7124794500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2343478471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2343478471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1981400500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1981400500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9468272971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9468272971 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11449673471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11449673471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013607 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013607 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292546 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292546 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010703 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010703 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011568 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011568 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22301.622722 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22301.622722 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15326.134172 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15326.134172 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50670.946520 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50670.946520 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19986.852445 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19986.852445 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22369.837554 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22369.837554 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 325915 # number of replacements -system.cpu.icache.tags.tagsinuse 510.404253 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22094458 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 326427 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.685755 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1157973500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.404253 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996883 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996883 # Average percentage of cache occupancy +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292597 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292597 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010701 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010701 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011567 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011567 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23822.848191 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23822.848191 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15774.520036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15774.520036 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52551.466688 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52551.466688 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21151.770909 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21151.770909 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23591.084728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23591.084728 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 325639 # number of replacements +system.cpu.icache.tags.tagsinuse 510.373274 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22095836 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 326151 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.747258 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1176670500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.373274 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996823 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996823 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 328 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45190725 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45190725 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22094458 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22094458 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22094458 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22094458 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22094458 # number of overall hits -system.cpu.icache.overall_hits::total 22094458 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 337685 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 337685 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 337685 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 337685 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 337685 # number of overall misses -system.cpu.icache.overall_misses::total 337685 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5566889382 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5566889382 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5566889382 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5566889382 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5566889382 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5566889382 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22432143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22432143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22432143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22432143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22432143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22432143 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015054 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015054 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015054 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015054 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015054 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015054 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16485.450589 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16485.450589 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16485.450589 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16485.450589 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16485.450589 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 546680 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 53 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25668 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45192862 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45192862 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 22095836 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22095836 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22095836 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22095836 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22095836 # number of overall hits +system.cpu.icache.overall_hits::total 22095836 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 337513 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 337513 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 337513 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 337513 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 337513 # number of overall misses +system.cpu.icache.overall_misses::total 337513 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5817859355 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5817859355 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5817859355 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5817859355 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5817859355 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5817859355 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22433349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22433349 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22433349 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22433349 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22433349 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22433349 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015045 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015045 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015045 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015045 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015045 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015045 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17237.437832 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17237.437832 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17237.437832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17237.437832 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17237.437832 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 562602 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 26054 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.298114 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 26.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325915 # number of writebacks -system.cpu.icache.writebacks::total 325915 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11245 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11245 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 11245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 11245 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 11245 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326440 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 326440 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 326440 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 326440 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 326440 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 326440 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5156036946 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5156036946 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5156036946 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5156036946 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5156036946 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5156036946 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014552 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014552 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014552 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014552 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15794.746189 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15794.746189 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15794.746189 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15794.746189 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822007 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825699 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 3235 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.593690 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 325639 # number of writebacks +system.cpu.icache.writebacks::total 325639 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11348 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 11348 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 11348 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 11348 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 11348 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 11348 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 326165 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 326165 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 326165 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 326165 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 326165 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 326165 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5383419413 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5383419413 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5383419413 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5383419413 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5383419413 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5383419413 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014539 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014539 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014539 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014539 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16505.202621 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16505.202621 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16505.202621 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16505.202621 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 823055 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826389 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 2921 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78661 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 125486 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15697.579441 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 682126 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 141813 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.810039 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78691 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 125520 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15698.936659 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 681800 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 141835 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.806994 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15632.148504 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 65.430937 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.954111 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003994 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958104 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 23 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16304 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 15629.036475 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 69.900184 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.953921 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004266 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958187 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 27 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16288 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 12 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2745 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12082 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 548 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25510486 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25510486 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 254711 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 254711 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 37072 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 37072 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 80670 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 80670 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 37072 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 89010 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 126082 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 37072 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 89010 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 115310 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 241392 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10321796922 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 201500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 201500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 722790000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 722790000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2931479000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2931479000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6418843000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6418843000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2931479000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7141633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10073112000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2931479000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7141633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10321796922 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20394908922 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113894 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239093 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239093 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.155329 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113894 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183195 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056125 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113665 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239570 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239570 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.155373 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113665 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183402 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.297300 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 86371.461875 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15458.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15458.333333 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81003.512741 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81003.512741 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72666.402173 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72666.402173 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73193.293592 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73193.293592 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73558.106522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72666.402173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73930.941991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 86371.461875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79676.925949 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1622603 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810817 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79904 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18775 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18774 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297472 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89513.458694 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86665.467626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86665.467626 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79075.285930 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79075.285930 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79569.145903 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79569.145903 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79893.339255 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79075.285930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80234.052354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89513.458694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84488.752411 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1621957 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810494 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18773 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18772 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 663212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 351973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 556066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 144126 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148601 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148601 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 326440 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336773 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 978779 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455634 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2434413 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41749696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62095104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103844800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 269627 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6225728 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1081438 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.288019 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 662893 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 354931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 552820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28222 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 146565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 326165 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336729 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455492 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2433446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41714496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62088960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103803456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 272099 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6227968 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1083589 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091107 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.287765 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 982719 90.87% 90.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98718 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 984867 90.89% 90.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98721 9.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1081438 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1622078500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489794228 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1083589 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1621431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 489373744 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728148836 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 348072 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.respLayer1.occupancy 728066857 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 348152 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205320 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 37283333000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214175 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97262 # Transaction distribution -system.membus.trans_dist::CleanEvict 28224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 12 # Transaction distribution -system.membus.trans_dist::ReadExReq 8398 # Transaction distribution -system.membus.trans_dist::ReadExResp 8398 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570645 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20469440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20469440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 37982056000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214278 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97298 # Transaction distribution +system.membus.trans_dist::CleanEvict 28222 # Transaction distribution +system.membus.trans_dist::UpgradeReq 13 # Transaction distribution +system.membus.trans_dist::ReadExReq 8340 # Transaction distribution +system.membus.trans_dist::ReadExResp 8340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214279 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570770 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570770 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20474624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20474624 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222586 # Request fanout histogram +system.membus.snoop_fanout::samples 222632 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222586 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222632 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222586 # Request fanout histogram -system.membus.reqLayer0.occupancy 837454269 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222632 # Request fanout histogram +system.membus.reqLayer0.occupancy 835899979 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1175863136 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1175524166 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |