diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref')
6 files changed, 2522 insertions, 2516 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 14d4b21df..e532ddba3 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046394 # Number of seconds simulated -sim_ticks 46393648500 # Number of ticks simulated -final_tick 46393648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043596 # Number of seconds simulated +sim_ticks 43595903500 # Number of ticks simulated +final_tick 43595903500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96549 # Simulator instruction rate (inst/s) -host_op_rate 96549 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50704548 # Simulator tick rate (ticks/s) -host_mem_usage 252684 # Number of bytes of host memory used -host_seconds 914.98 # Real time elapsed on the host +host_inst_rate 146921 # Simulator instruction rate (inst/s) +host_op_rate 146921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72505010 # Simulator tick rate (ticks/s) +host_mem_usage 252940 # Number of bytes of host memory used +host_seconds 601.28 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 514944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10272704 # Number of bytes read from this memory -system.physmem.bytes_read::total 10787648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 514944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 514944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory -system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8046 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160511 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168557 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11099450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 221424793 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 232524243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11099450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11099450 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 159987417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 159987417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 159987417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11099450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 221424793 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 392511660 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168557 # Total number of read requests seen -system.physmem.writeReqs 115975 # Total number of write requests seen -system.physmem.cpureqs 284532 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10787648 # Total number of bytes read from memory -system.physmem.bytesWritten 7422400 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10787648 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7422400 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 454912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10138304 # Number of bytes read from this memory +system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory +system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158411 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory +system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 10434742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 232551758 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242986500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10434742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10434742 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 167350770 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 167350770 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 167350770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10434742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 232551758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 410337269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165519 # Total number of read requests seen +system.physmem.writeReqs 113997 # Total number of write requests seen +system.physmem.cpureqs 279516 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10593216 # Total number of bytes read from memory +system.physmem.bytesWritten 7295808 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10544 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10882 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10471 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10499 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10074 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10523 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10531 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10030 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10827 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10322 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7019 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7391 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7077 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7201 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6971 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7254 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7052 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7484 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7300 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10695 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10371 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10332 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10345 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9920 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10624 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10240 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6899 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7300 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6879 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7379 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7080 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7193 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 46393600000 # Total gap between requests +system.physmem.totGap 43595883500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 168557 # Categorize read packet sizes +system.physmem.readPktSize::6 165519 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 115975 # categorize write packet sizes +system.physmem.writePktSize::6 113997 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 162958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1045 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1271098054 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4666794054 # Sum of mem lat for all requests -system.physmem.totBusLat 674180000 # Total cycles spent in databus access -system.physmem.totBankLat 2721516000 # Total cycles spent in bank access -system.physmem.avgQLat 7541.59 # Average queueing delay per request -system.physmem.avgBankLat 16147.12 # Average bank access latency per request +system.physmem.totQLat 9323896604 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11720942604 # Sum of mem lat for all requests +system.physmem.totBusLat 662068000 # Total cycles spent in databus access +system.physmem.totBankLat 1734978000 # Total cycles spent in bank access +system.physmem.avgQLat 56331.96 # Average queueing delay per request +system.physmem.avgBankLat 10482.17 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27688.71 # Average memory access latency -system.physmem.avgRdBW 232.52 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 159.99 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 232.52 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 159.99 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70814.13 # Average memory access latency +system.physmem.avgRdBW 242.99 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 167.35 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 242.99 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 167.35 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.45 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.10 # Average read queue length over time -system.physmem.avgWrQLen 10.39 # Average write queue length over time -system.physmem.readRowHits 152922 # Number of row buffer hits during reads -system.physmem.writeRowHits 84722 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.05 # Row buffer hit rate for writes -system.physmem.avgGap 163052.31 # Average gap between requests +system.physmem.busUtil 2.56 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.27 # Average read queue length over time +system.physmem.avgWrQLen 10.36 # Average write queue length over time +system.physmem.readRowHits 151893 # Number of row buffer hits during reads +system.physmem.writeRowHits 41557 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.45 # Row buffer hit rate for writes +system.physmem.avgGap 155969.19 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277224 # DTB read hits +system.cpu.dtb.read_hits 20277538 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367372 # DTB read accesses -system.cpu.dtb.write_hits 14736801 # DTB write hits +system.cpu.dtb.read_accesses 20367686 # DTB read accesses +system.cpu.dtb.write_hits 14728672 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744053 # DTB write accesses -system.cpu.dtb.data_hits 35014025 # DTB hits +system.cpu.dtb.write_accesses 14735924 # DTB write accesses +system.cpu.dtb.data_hits 35006210 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111425 # DTB accesses -system.cpu.itb.fetch_hits 12475425 # ITB hits -system.cpu.itb.fetch_misses 12954 # ITB misses +system.cpu.dtb.data_accesses 35103610 # DTB accesses +system.cpu.itb.fetch_hits 12476759 # ITB hits +system.cpu.itb.fetch_misses 12943 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12488379 # ITB accesses +system.cpu.itb.fetch_accesses 12489702 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 92787298 # number of cpu cycles simulated +system.cpu.numCycles 87191808 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18828887 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12440846 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5023695 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16217673 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5047073 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660946 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.120821 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8474385 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10354502 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74331965 # Number of Reads from Int. Register File +system.cpu.branch_predictor.lookups 18827150 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12439421 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5024981 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16201522 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5047120 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660945 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions. +system.cpu.branch_predictor.BTBHitPct 31.152135 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8476186 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10350964 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74333119 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126651215 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65206 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126652369 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65259 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292836 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14119774 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064022 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4679410 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 233785 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4913195 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8859107 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.674465 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44776036 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292889 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14121677 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064639 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4680318 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 234163 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4914481 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8857790 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.683882 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44776328 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78069956 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77836216 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 311324 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 22508104 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70279194 # Number of cycles cpu stages are processed. -system.cpu.activity 75.742257 # Percentage of cycles cpu is active +system.cpu.timesIdled 230753 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16919077 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70272731 # Number of cycles cpu stages are processed. +system.cpu.activity 80.595566 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -272,144 +272,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.050335 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.986995 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.050335 # CPI: Total CPI of All Threads -system.cpu.ipc 0.952077 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.986995 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013176 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.952077 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 39364116 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53423182 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 57.575965 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 50132225 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42655073 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.970811 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 49662532 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43124766 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 46.477015 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 70666607 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120691 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.840215 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46683402 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46103896 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.687723 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85246 # number of replacements -system.cpu.icache.tagsinuse 1892.367381 # Cycle average of tags in use -system.cpu.icache.total_refs 12357191 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87292 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.561552 # Average number of references to valid blocks. +system.cpu.ipc_total 1.013176 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 33768817 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53422991 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 61.270654 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44539685 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42652123 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.917581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44072021 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43119787 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.453943 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65076368 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22115440 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.364126 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41085926 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46105882 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.878686 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85196 # number of replacements +system.cpu.icache.tagsinuse 1908.917223 # Cycle average of tags in use +system.cpu.icache.total_refs 12358549 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87242 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.658249 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1892.367381 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.924008 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.924008 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12357191 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12357191 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12357191 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12357191 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12357191 # number of overall hits -system.cpu.icache.overall_hits::total 12357191 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118187 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118187 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118187 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118187 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118187 # number of overall misses -system.cpu.icache.overall_misses::total 118187 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1883931500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1883931500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1883931500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1883931500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1883931500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1883931500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12475378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12475378 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12475378 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12475378 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12475378 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12475378 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1908.917223 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.932088 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.932088 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12358549 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12358549 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12358549 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12358549 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12358549 # number of overall hits +system.cpu.icache.overall_hits::total 12358549 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118203 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118203 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118203 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118203 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118203 # number of overall misses +system.cpu.icache.overall_misses::total 118203 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1846898500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1846898500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1846898500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1846898500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1846898500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1846898500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12476752 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12476752 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12476752 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12476752 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12476752 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12476752 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15940.259927 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15940.259927 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15940.259927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15940.259927 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1882 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 108 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17.425926 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15624.802247 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15624.802247 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15624.802247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15624.802247 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15624.802247 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 6.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30895 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30895 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30895 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30895 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30895 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30895 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87292 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87292 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87292 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87292 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87292 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87292 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1323717000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1323717000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1323717000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1323717000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1323717000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1323717000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006997 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006997 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006997 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15164.241855 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15164.241855 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15164.241855 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15164.241855 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15164.241855 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15164.241855 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30961 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30961 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30961 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30961 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30961 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30961 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87242 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87242 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87242 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87242 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87242 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87242 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1292347500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1292347500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1292347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1292347500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1292347500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1292347500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006992 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006992 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006992 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006992 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14813.363976 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14813.363976 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14813.363976 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14813.363976 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4074.773035 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126001 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4078.664341 # Cycle average of tags in use +system.cpu.dcache.total_refs 33754987 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000254 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 420616000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4074.773035 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994818 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994818 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180529 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180529 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945472 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945472 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126001 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126001 # 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number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180268 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574719 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574719 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754987 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754987 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754987 # number of overall hits +system.cpu.dcache.overall_hits::total 33754987 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96370 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96370 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038658 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038658 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135028 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135028 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135028 # number of overall misses +system.cpu.dcache.overall_misses::total 1135028 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3954988500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3954988500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 91520281000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 91520281000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 95475269500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 95475269500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 95475269500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 95475269500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -418,40 +418,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045705 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045705 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38064.099096 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38064.099096 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49228.758581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 49228.758581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47824.302303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47824.302303 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11803841 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124100 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 271 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 95.115560 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071076 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071076 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032532 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032532 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032532 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032532 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.623327 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.623327 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88113.971105 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 88113.971105 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84117.105041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84117.105041 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84117.105041 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6175044 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 397 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116295 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.098104 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 397 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165814 # number of writebacks -system.cpu.dcache.writebacks::total 165814 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35342 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35342 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524325 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559667 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559667 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 168353 # number of writebacks +system.cpu.dcache.writebacks::total 168353 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35603 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35603 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895078 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895078 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930681 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930681 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930681 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930681 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -460,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1847026500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1847026500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6899064500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6899064500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8746091000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8746091000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8746091000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8746091000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1939972500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1939972500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14546837500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14546837500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16486810000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16486810000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16486810000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16486810000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -476,152 +476,152 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30395.222736 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30395.222736 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48050.316897 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48050.316897 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42800.192809 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 42800.192809 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42800.192809 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 42800.192809 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31924.770023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31924.770023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101315.207550 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101315.207550 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80680.460198 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80680.460198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80680.460198 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80680.460198 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 136129 # number of replacements -system.cpu.l2cache.tagsinuse 28923.934972 # Cycle average of tags in use -system.cpu.l2cache.total_refs 146431 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 166993 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.876869 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 131596 # number of replacements +system.cpu.l2cache.tagsinuse 30981.821005 # Cycle average of tags in use +system.cpu.l2cache.total_refs 152256 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 163654 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.930353 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25485.883483 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1737.517114 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1700.534375 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.777767 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.053025 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.051896 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.882688 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 79246 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31114 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 110360 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 165814 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 165814 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12722 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12722 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 79246 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 43836 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 123082 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 79246 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 43836 # number of overall hits -system.cpu.l2cache.overall_hits::total 123082 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8046 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43331.775254 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 43408.673386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96667.511326 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96667.511326 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43706.399409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87401.744071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85525.303844 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index ce6ab2ad0..04dfac9bb 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021820 # Number of seconds simulated -sim_ticks 21820020000 # Number of ticks simulated -final_tick 21820020000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024767 # Number of seconds simulated +sim_ticks 24766869000 # Number of ticks simulated +final_tick 24766869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158943 # Simulator instruction rate (inst/s) -host_op_rate 158943 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43574235 # Simulator tick rate (ticks/s) -host_mem_usage 253708 # Number of bytes of host memory used -host_seconds 500.76 # Real time elapsed on the host +host_inst_rate 162319 # Simulator instruction rate (inst/s) +host_op_rate 162319 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50509376 # Simulator tick rate (ticks/s) +host_mem_usage 253968 # Number of bytes of host memory used +host_seconds 490.34 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10296000 # Number of bytes read from this memory -system.physmem.bytes_read::total 10855680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160875 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169620 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116046 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 25649839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 471860246 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 497510085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 25649839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 25649839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 340372924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 340372924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 340372924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 25649839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 471860246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 837883008 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 169621 # Total number of read requests seen -system.physmem.writeReqs 116046 # Total number of write requests seen -system.physmem.cpureqs 285667 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10855680 # Total number of bytes read from memory -system.physmem.bytesWritten 7426944 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10855680 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7426944 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 491520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory +system.physmem.bytes_read::total 10646272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 491520 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 491520 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7680 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166348 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19845867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 410013555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 429859422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19845867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19845867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 294625857 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 294625857 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 294625857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19845867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 410013555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 724485279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166348 # Total number of read requests seen +system.physmem.writeReqs 114015 # Total number of write requests seen +system.physmem.cpureqs 280363 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10646272 # Total number of bytes read from memory +system.physmem.bytesWritten 7296960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10646272 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 11095 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10512 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10822 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10358 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10136 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10838 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10589 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10582 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10059 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10352 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7516 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 7083 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7440 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7204 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 7178 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7257 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7051 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7488 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 7299 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10314 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10372 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10586 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10283 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10016 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10446 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10273 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10691 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10255 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7408 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7249 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7298 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7207 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6885 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7381 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7081 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6935 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7191 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 21820003000 # Total gap between requests +system.physmem.totGap 24766835500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 169621 # Categorize read packet sizes +system.physmem.readPktSize::6 166348 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 116046 # categorize write packet sizes +system.physmem.writePktSize::6 114015 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -105,16 +105,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 66903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 55166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 70675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 64436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -138,80 +138,80 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5024 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2790 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 5060410122 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7401532122 # Sum of mem lat for all requests -system.physmem.totBusLat 678440000 # Total cycles spent in databus access -system.physmem.totBankLat 1662682000 # Total cycles spent in bank access -system.physmem.avgQLat 29835.56 # Average queueing delay per request -system.physmem.avgBankLat 9802.97 # Average bank access latency per request +system.physmem.totQLat 9402171924 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11754135924 # Sum of mem lat for all requests +system.physmem.totBusLat 665384000 # Total cycles spent in databus access +system.physmem.totBankLat 1686580000 # Total cycles spent in bank access +system.physmem.avgQLat 56521.78 # Average queueing delay per request +system.physmem.avgBankLat 10138.99 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43638.54 # Average memory access latency -system.physmem.avgRdBW 497.51 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 340.37 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 497.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 340.37 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 70660.77 # Average memory access latency +system.physmem.avgRdBW 429.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 294.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 429.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 294.63 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.24 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.34 # Average read queue length over time -system.physmem.avgWrQLen 10.53 # Average write queue length over time -system.physmem.readRowHits 153635 # Number of row buffer hits during reads -system.physmem.writeRowHits 84286 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.63 # Row buffer hit rate for writes -system.physmem.avgGap 76382.65 # Average gap between requests +system.physmem.busUtil 4.53 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.47 # Average read queue length over time +system.physmem.avgWrQLen 9.66 # Average write queue length over time +system.physmem.readRowHits 152267 # Number of row buffer hits during reads +system.physmem.writeRowHits 40679 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 35.68 # Row buffer hit rate for writes +system.physmem.avgGap 88338.46 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22500738 # DTB read hits -system.cpu.dtb.read_misses 216644 # DTB read misses -system.cpu.dtb.read_acv 44 # DTB read access violations -system.cpu.dtb.read_accesses 22717382 # DTB read accesses -system.cpu.dtb.write_hits 15795905 # DTB write hits -system.cpu.dtb.write_misses 41245 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 15837150 # DTB write accesses -system.cpu.dtb.data_hits 38296643 # DTB hits -system.cpu.dtb.data_misses 257889 # DTB misses -system.cpu.dtb.data_acv 44 # DTB access violations -system.cpu.dtb.data_accesses 38554532 # DTB accesses -system.cpu.itb.fetch_hits 14148494 # ITB hits -system.cpu.itb.fetch_misses 39336 # ITB misses +system.cpu.dtb.read_hits 22524754 # DTB read hits +system.cpu.dtb.read_misses 221109 # DTB read misses +system.cpu.dtb.read_acv 49 # DTB read access violations +system.cpu.dtb.read_accesses 22745863 # DTB read accesses +system.cpu.dtb.write_hits 15800982 # DTB write hits +system.cpu.dtb.write_misses 41722 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15842704 # DTB write accesses +system.cpu.dtb.data_hits 38325736 # DTB hits +system.cpu.dtb.data_misses 262831 # DTB misses +system.cpu.dtb.data_acv 50 # DTB access violations +system.cpu.dtb.data_accesses 38588567 # DTB accesses +system.cpu.itb.fetch_hits 14187534 # ITB hits +system.cpu.itb.fetch_misses 37797 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14187830 # ITB accesses +system.cpu.itb.fetch_accesses 14225331 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,245 +225,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 43640043 # number of cpu cycles simulated +system.cpu.numCycles 49533742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16741832 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10806668 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477582 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12162476 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7482577 # Number of BTB hits +system.cpu.BPredUnit.lookups 16746521 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10800034 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477053 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12193904 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7496910 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1995510 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 45710 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15036393 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106856108 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16741832 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9478087 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19828359 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2147542 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 4492220 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 323266 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14148494 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 220972 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 41243035 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.590889 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.177319 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 2006546 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45028 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 16102899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106919359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16746521 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9503456 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19851092 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2196928 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6491501 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8361 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314458 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14187534 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 227935 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44359313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.410302 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.133631 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21414676 51.92% 51.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1548321 3.75% 55.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1410779 3.42% 59.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1521748 3.69% 62.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4201075 10.19% 72.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1864766 4.52% 77.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 686260 1.66% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1087985 2.64% 81.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7507425 18.20% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24508221 55.25% 55.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1552927 3.50% 58.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1407762 3.17% 61.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1534147 3.46% 65.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4200830 9.47% 74.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1874236 4.23% 79.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 688640 1.55% 80.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1098273 2.48% 83.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7494277 16.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 41243035 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.383635 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.448579 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16096491 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4096982 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18769266 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 833511 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1446785 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3807119 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 110554 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104936406 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 308694 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1446785 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16548633 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1976361 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 82879 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19114757 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2073620 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103469028 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 341 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14640 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1956889 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62372396 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124769861 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124309039 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 460822 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44359313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.338083 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.158516 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17202144 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6044851 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18844952 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 783382 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1483984 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3808507 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 109388 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 105012446 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304839 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1483984 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17687031 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3815602 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84566 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19093119 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2195011 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103566225 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2071816 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62457346 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124882897 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124424416 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 458481 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9825515 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5546 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5543 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4207574 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23385563 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16393614 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1121004 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 386917 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91482649 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5403 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89074963 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123031 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11309425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4934372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 820 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 41243035 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.159758 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.116316 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9910465 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5561 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5559 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4548155 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23430190 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16410014 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1178549 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 390985 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91582200 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5227 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89129103 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 121099 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11405338 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5024468 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44359313 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.009253 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109781 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12823282 31.09% 31.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6988742 16.95% 48.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5560534 13.48% 61.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4799338 11.64% 73.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4679683 11.35% 84.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2682377 6.50% 91.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1950315 4.73% 95.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1335480 3.24% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 423284 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15871640 35.78% 35.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6995929 15.77% 51.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5623158 12.68% 64.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4788485 10.79% 75.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4723434 10.65% 85.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2673880 6.03% 91.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1944632 4.38% 96.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1314765 2.96% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 423390 0.95% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 41243035 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44359313 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 129257 6.79% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 803786 42.23% 49.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 970116 50.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 127127 6.74% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.74% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 794266 42.09% 48.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 965741 51.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49746538 55.85% 55.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43785 0.05% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121262 0.14% 56.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 122235 0.14% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38920 0.04% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22991531 25.81% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16010548 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49762830 55.83% 55.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43850 0.05% 55.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121597 0.14% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121881 0.14% 56.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 60 0.00% 56.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38947 0.04% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23025644 25.83% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16014206 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89074963 # Type of FU issued -system.cpu.iq.rate 2.041129 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1903159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021366 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 220805862 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102391842 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87007224 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 613289 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 421743 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 298831 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90671357 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 306765 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1448727 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89129103 # Type of FU issued +system.cpu.iq.rate 1.799361 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1887134 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021173 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224014583 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102585406 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87044839 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 611169 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 425269 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 296604 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90710574 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 305663 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1465776 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3108925 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5719 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17139 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1780237 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3153552 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5566 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18132 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1796637 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2546 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 373 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2518 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 82425 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1446785 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1296877 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 55540 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101030605 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 244499 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23385563 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16393614 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5403 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48652 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 428 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17139 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 253350 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 173638 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 426988 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88093519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22720865 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 981444 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1483984 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2836184 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 76819 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101124099 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 260669 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23430190 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16410014 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5227 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60088 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 531 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18132 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 252052 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 171036 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423088 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88146777 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22749364 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 982326 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9542553 # number of nop insts executed -system.cpu.iew.exec_refs 38558406 # number of memory reference insts executed -system.cpu.iew.exec_branches 15140678 # Number of branches executed -system.cpu.iew.exec_stores 15837541 # Number of stores executed -system.cpu.iew.exec_rate 2.018640 # Inst execution rate -system.cpu.iew.wb_sent 87722588 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87306055 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33473930 # num instructions producing a value -system.cpu.iew.wb_consumers 43902488 # num instructions consuming a value +system.cpu.iew.exec_nop 9536672 # number of nop insts executed +system.cpu.iew.exec_refs 38592395 # number of memory reference insts executed +system.cpu.iew.exec_branches 15153499 # Number of branches executed +system.cpu.iew.exec_stores 15843031 # Number of stores executed +system.cpu.iew.exec_rate 1.779530 # Inst execution rate +system.cpu.iew.wb_sent 87753741 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87341443 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33435183 # num instructions producing a value +system.cpu.iew.wb_consumers 43872218 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.000595 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762461 # average fanout of values written-back +system.cpu.iew.wb_rate 1.763272 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762104 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9547814 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9751269 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369802 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39796250 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.219824 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.827061 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 370067 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42875329 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.060408 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.788298 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16770955 42.14% 42.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7067067 17.76% 59.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3514313 8.83% 68.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2098075 5.27% 74.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2085843 5.24% 79.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1169184 2.94% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108409 2.79% 84.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 748224 1.88% 86.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5234180 13.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19913451 46.45% 46.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7068985 16.49% 62.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3438952 8.02% 70.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2090019 4.87% 75.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2085052 4.86% 80.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1168150 2.72% 83.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1107868 2.58% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 727256 1.70% 87.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5275596 12.30% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39796250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42875329 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -474,358 +475,358 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5234180 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5275596 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131133214 # The number of ROB reads -system.cpu.rob.rob_writes 197227324 # The number of ROB writes -system.cpu.timesIdled 14215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2397008 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 134374332 # The number of ROB reads +system.cpu.rob.rob_writes 197671452 # The number of ROB writes +system.cpu.timesIdled 69954 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5174429 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.548299 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.548299 # CPI: Total CPI of All Threads -system.cpu.ipc 1.823824 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.823824 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116640350 # number of integer regfile reads -system.cpu.int_regfile_writes 57883705 # number of integer regfile writes -system.cpu.fp_regfile_reads 253852 # number of floating regfile reads -system.cpu.fp_regfile_writes 241497 # number of floating regfile writes -system.cpu.misc_regfile_reads 38324 # number of misc regfile reads +system.cpu.cpi 0.622348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.622348 # CPI: Total CPI of All Threads +system.cpu.ipc 1.606819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.606819 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116696990 # number of integer regfile reads +system.cpu.int_regfile_writes 57893587 # number of integer regfile writes +system.cpu.fp_regfile_reads 251486 # number of floating regfile reads +system.cpu.fp_regfile_writes 240711 # number of floating regfile writes +system.cpu.misc_regfile_reads 38028 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 93950 # number of replacements -system.cpu.icache.tagsinuse 1932.033344 # Cycle average of tags in use -system.cpu.icache.total_refs 14048966 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 95998 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 146.346445 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18344988000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1932.033344 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.943376 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.943376 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14048966 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14048966 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14048966 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14048966 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14048966 # number of overall hits -system.cpu.icache.overall_hits::total 14048966 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 99528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 99528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 99528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 99528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 99528 # number of overall misses -system.cpu.icache.overall_misses::total 99528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 808544500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 808544500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 808544500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 808544500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 808544500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 808544500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14148494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14148494 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14148494 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14148494 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14148494 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14148494 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007035 # 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Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 20259707000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1931.186939 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.942962 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.942962 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14080520 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14080520 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14080520 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14080520 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14080520 # number of overall hits +system.cpu.icache.overall_hits::total 14080520 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 107014 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 107014 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 107014 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 107014 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 107014 # number of overall misses +system.cpu.icache.overall_misses::total 107014 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1801616999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1801616999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1801616999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1801616999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1801616999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1801616999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14187534 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14187534 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14187534 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14187534 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14187534 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14187534 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007543 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007543 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007543 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007543 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007543 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007543 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16835.339292 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16835.339292 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16835.339292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16835.339292 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16835.339292 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 434 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48.222222 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 95999 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 95999 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 95999 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 523730500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 523730500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 523730500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 523730500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 523730500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 523730500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006785 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006785 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006785 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5455.582871 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5455.582871 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5455.582871 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5455.582871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5455.582871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5455.582871 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12665 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12665 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12665 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12665 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12665 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12665 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94349 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 94349 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 94349 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 94349 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 94349 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 94349 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1400064000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1400064000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1400064000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1400064000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1400064000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1400064000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006650 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006650 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006650 # 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Cycle average of tags in use -system.cpu.dcache.total_refs 34377845 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205683 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.139944 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 145380000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4077.730467 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995540 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995540 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20796650 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20796650 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13581134 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13581134 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # 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Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205682 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.913089 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 177489000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4077.128651 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995393 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995393 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20756846 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20756846 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574115 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574115 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 57 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12393965000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 93492268598 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 93492268598 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 105886233598 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 105886233598 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 105886233598 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 105886233598 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21023638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21023638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # 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average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1971 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 36 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35637015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35637015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35637015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35637015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012690 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012690 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071117 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071117 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036649 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036649 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036649 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036649 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46455.534649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46455.534649 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89960.249290 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89960.249290 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81073.396351 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81073.396351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81073.396351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81073.396351 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5474703 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 114 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112304 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.750000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.748958 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 114 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166289 # number of writebacks -system.cpu.dcache.writebacks::total 166289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 190140 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 190140 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 888824 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 888824 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1078964 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1078964 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1078964 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1078964 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62264 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62264 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 169009 # number of writebacks +system.cpu.dcache.writebacks::total 169009 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204529 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204529 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895843 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895843 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100372 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100372 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100372 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100372 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62263 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62263 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143419 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143419 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205683 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205683 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205683 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205683 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1130234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1130234500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8280369500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8280369500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9410604000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9410604000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9410604000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9410604000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 205682 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205682 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205682 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205682 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2025118000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2025118000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14654502991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14654502991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16679620991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16679620991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16679620991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16679620991 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002962 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002962 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45752.949928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45752.949928 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45752.949928 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005772 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005772 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005772 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005772 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32525.223648 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32525.223648 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102179.648380 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102179.648380 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81094.218215 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81094.218215 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81094.218215 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81094.218215 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 137215 # number of replacements -system.cpu.l2cache.tagsinuse 29193.790344 # Cycle average of tags in use -system.cpu.l2cache.total_refs 156193 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 168097 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.929184 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 132442 # number of replacements +system.cpu.l2cache.tagsinuse 30854.003971 # Cycle average of tags in use +system.cpu.l2cache.total_refs 160847 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 164507 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.977752 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25457.491350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1903.606524 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1832.692470 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.776901 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.058093 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.055929 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.890924 # 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average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34552.014040 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35513.010527 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62001.592089 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62001.592089 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38800.022868 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56897.292929 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 55964.161277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38800.022868 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56897.292929 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 55964.161277 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 1668 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143423 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 94349 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205682 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 300031 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 94349 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205682 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 300031 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081411 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.447582 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.226981 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912002 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912002 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081411 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771424 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.554439 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081411 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771424 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.554439 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57040.164041 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58022.949114 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 57810.588798 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109961.422608 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109961.422608 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57040.164041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100839.750296 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 98817.347865 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57040.164041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100839.750296 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 98817.347865 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 49.058824 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 116046 # number of writebacks -system.cpu.l2cache.writebacks::total 116046 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8746 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29915 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 38661 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130960 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130960 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 160875 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 169621 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8746 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160875 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 169621 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 306935647 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 916786687 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223722334 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7694631450 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7694631450 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 306935647 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8611418137 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8918353784 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 306935647 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8611418137 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8918353784 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480462 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.244285 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782150 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.562251 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782150 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.562251 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35094.402813 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30646.387665 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31652.630144 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58755.585293 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58755.585293 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35094.402813 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53528.628668 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52578.122898 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35094.402813 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53528.628668 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52578.122898 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114015 # number of writebacks +system.cpu.l2cache.writebacks::total 114015 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7681 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27866 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35547 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130802 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130802 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7681 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158668 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7681 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158668 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166349 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 340900477 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1256603152 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1597503629 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12762940575 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12762940575 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 340900477 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14019543727 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14360444204 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 340900477 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14019543727 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14360444204 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.447582 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.226981 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912002 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912002 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771424 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.554439 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081411 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771424 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.554439 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44382.303997 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45094.493361 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 44940.603398 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97574.506315 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97574.506315 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44382.303997 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88357.726366 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86327.204876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44382.303997 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88357.726366 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86327.204876 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 456c7f9d2..43727f4ad 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133756 # Number of seconds simulated -sim_ticks 133756135000 # Number of ticks simulated -final_tick 133756135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133635 # Number of seconds simulated +sim_ticks 133634727000 # Number of ticks simulated +final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1270571 # Simulator instruction rate (inst/s) -host_op_rate 1270570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1923763163 # Simulator tick rate (ticks/s) -host_mem_usage 227600 # Number of bytes of host memory used -host_seconds 69.53 # Real time elapsed on the host +host_inst_rate 783809 # Simulator instruction rate (inst/s) +host_op_rate 783809 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1185683886 # Simulator tick rate (ticks/s) +host_mem_usage 225136 # Number of bytes of host memory used +host_seconds 112.71 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 485312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10270528 # Number of bytes read from this memory -system.physmem.bytes_read::total 10755840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 485312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 485312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7421120 # Number of bytes written to this memory -system.physmem.bytes_written::total 7421120 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7583 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160477 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168060 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115955 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115955 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3628335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 76785472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 80413807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3628335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3628335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 55482464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 55482464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 55482464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3628335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 76785472 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 135896271 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory +system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory +system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -67,7 +67,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267512270 # number of cpu cycles simulated +system.cpu.numCycles 267269454 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -86,18 +86,18 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267512270 # Number of busy cycles +system.cpu.num_busy_cycles 267269454 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.674409 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1871.686406 # Cycle average of tags in use system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.674409 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913904 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913904 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -110,12 +110,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1312229000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1312229000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1312229000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1312229000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1312229000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1312229000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1278112000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1278112000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1278112000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1278112000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1278112000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1278112000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -128,12 +128,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17167.682767 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17167.682767 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17167.682767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17167.682767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17167.682767 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16721.335496 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16721.335496 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16721.335496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16721.335496 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -148,34 +148,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1159357000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1159357000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1159357000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1159357000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1159357000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1159357000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1125240000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1125240000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1125240000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1125240000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1125240000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1125240000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15167.682767 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15167.682767 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15167.682767 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15167.682767 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14721.335496 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14721.335496 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.879185 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.879185 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995820 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995820 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits @@ -192,14 +192,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2026896000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2026896000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7369702000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7369702000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9396598000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9396598000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9396598000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9396598000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -216,14 +216,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33355.758154 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33355.758154 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51328.908329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51328.908329 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45984.212896 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45984.212896 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45984.212896 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -232,8 +232,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165828 # number of writebacks -system.cpu.dcache.writebacks::total 165828 # number of writebacks +system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks +system.cpu.dcache.writebacks::total 168375 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -242,14 +242,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1905364000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1905364000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7082546000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7082546000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8987910000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8987910000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8987910000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -258,68 +258,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31355.758154 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31355.758154 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49328.908329 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49328.908329 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43984.212896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43984.212896 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 135625 # number of replacements -system.cpu.l2cache.tagsinuse 29005.267541 # Cycle average of tags in use -system.cpu.l2cache.total_refs 136279 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 166491 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.818537 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 131235 # number of replacements +system.cpu.l2cache.tagsinuse 30728.810101 # Cycle average of tags in use +system.cpu.l2cache.total_refs 142024 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 163291 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.869760 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25782.627688 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1648.153103 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1574.486750 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.786823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.050298 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.048050 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.885171 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 68853 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31317 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 100170 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 165828 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 165828 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12550 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12550 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 68853 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 43867 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 112720 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 68853 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 43867 # number of overall hits -system.cpu.l2cache.overall_hits::total 112720 # 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number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158389 # number of overall misses +system.cpu.l2cache.overall_misses::total 165153 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 352084000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1430874000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1782958000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6805851000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6805851000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 352084000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8236725000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8588809000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 352084000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8236725000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8588809000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 165828 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 165828 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168375 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168375 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses @@ -328,28 +328,28 @@ system.cpu.l2cache.demand_accesses::total 280780 # n system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.099207 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.484630 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.269909 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912591 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912591 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.099207 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.785328 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.598547 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.099207 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.785328 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.598547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52009.890545 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.716561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52004.185569 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.091583 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.091583 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52009.890545 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.573291 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.993693 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52009.890545 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.573291 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.993693 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088492 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.452687 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.249792 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911567 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911567 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088492 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775110 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.588194 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52052.631579 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52016.649702 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52023.751167 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.297981 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.297981 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52005.164908 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52005.164908 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -358,52 +358,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 115955 # number of writebacks -system.cpu.l2cache.writebacks::total 115955 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7583 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29449 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37032 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131028 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131028 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7583 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 160477 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168060 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7583 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160477 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168060 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303395000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1178040000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1481435000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5241132000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5241132000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303395000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6419172000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6722567000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303395000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6419172000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6722567000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.484630 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269909 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912591 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912591 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.598547 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.099207 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785328 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.598547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40009.890545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.716561 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40004.185569 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.091583 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.091583 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40009.890545 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.573291 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.993693 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 113982 # number of writebacks +system.cpu.l2cache.writebacks::total 113982 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 6764 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27508 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165153 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 270916000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1100778000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1371694000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235279000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index c4dd2ec41..bbe40238a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024118 # Number of seconds simulated -sim_ticks 24118236000 # Number of ticks simulated -final_tick 24118236000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026781 # Number of seconds simulated +sim_ticks 26780535000 # Number of ticks simulated +final_tick 26780535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96109 # Simulator instruction rate (inst/s) -host_op_rate 136382 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32682486 # Simulator tick rate (ticks/s) -host_mem_usage 260548 # Number of bytes of host memory used -host_seconds 737.96 # Real time elapsed on the host -sim_insts 70924474 # Number of instructions simulated -sim_ops 100643721 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 326720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory -system.physmem.bytes_read::total 8354752 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 326720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 326720 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417408 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417408 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130543 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84647 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84647 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13546596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 332861491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 346408087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13546596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13546596 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 224618749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 224618749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 224618749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13546596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 332861491 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 571026836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 130544 # Total number of read requests seen -system.physmem.writeReqs 84647 # Total number of write requests seen -system.physmem.cpureqs 215212 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8354752 # Total number of bytes read from memory -system.physmem.bytesWritten 5417408 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8354752 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5417408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 21 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8120 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8253 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 7969 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 7982 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8186 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8104 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8313 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8235 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 8061 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8038 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5294 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5079 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5269 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5220 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5401 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5186 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5326 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5458 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5400 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5357 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5265 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5255 # Track writes on a per bank basis +host_inst_rate 149394 # Simulator instruction rate (inst/s) +host_op_rate 211994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56410244 # Simulator tick rate (ticks/s) +host_mem_usage 261852 # Number of bytes of host memory used +host_seconds 474.75 # Real time elapsed on the host +sim_insts 70924159 # Number of instructions simulated +sim_ops 100643406 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 300160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7944448 # Number of bytes read from this memory +system.physmem.bytes_read::total 8244608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 300160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 300160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372672 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372672 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124132 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128822 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83948 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83948 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11208141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296650086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307858226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11208141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11208141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200618546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200618546 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200618546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11208141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296650086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508476772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128823 # Total number of read requests seen +system.physmem.writeReqs 83948 # Total number of write requests seen +system.physmem.cpureqs 213079 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8244608 # Total number of bytes read from memory +system.physmem.bytesWritten 5372672 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8244608 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372672 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 308 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7891 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8032 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7950 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7992 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8193 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7981 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5174 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5126 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5148 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24118216500 # Total gap between requests +system.physmem.totGap 26780515500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 130544 # Categorize read packet sizes +system.physmem.readPktSize::6 128823 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -93,7 +93,7 @@ system.physmem.writePktSize::2 0 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 84647 # categorize write packet sizes +system.physmem.writePktSize::6 83948 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -102,16 +102,16 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 21 # categorize neither packet sizes +system.physmem.neitherpktsize::6 308 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 69205 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 57726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 71083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2364 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -138,31 +138,31 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -171,27 +171,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2308860118 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4224446118 # Sum of mem lat for all requests -system.physmem.totBusLat 522152000 # Total cycles spent in databus access -system.physmem.totBankLat 1393434000 # Total cycles spent in bank access -system.physmem.avgQLat 17687.26 # Average queueing delay per request -system.physmem.avgBankLat 10674.55 # Average bank access latency per request +system.physmem.totQLat 4847041699 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6735959699 # Sum of mem lat for all requests +system.physmem.totBusLat 515280000 # Total cycles spent in databus access +system.physmem.totBankLat 1373638000 # Total cycles spent in bank access +system.physmem.avgQLat 37626.47 # Average queueing delay per request +system.physmem.avgBankLat 10663.24 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32361.81 # Average memory access latency -system.physmem.avgRdBW 346.41 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 224.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 346.41 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 224.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 52289.70 # Average memory access latency +system.physmem.avgRdBW 307.86 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 200.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 307.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 200.62 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.57 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.22 # Average write queue length over time -system.physmem.readRowHits 119025 # Number of row buffer hits during reads -system.physmem.writeRowHits 63519 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes -system.physmem.avgGap 112078.18 # Average gap between requests +system.physmem.busUtil 3.18 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.25 # Average read queue length over time +system.physmem.avgWrQLen 9.64 # Average write queue length over time +system.physmem.readRowHits 118946 # Number of row buffer hits during reads +system.physmem.writeRowHits 27105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.29 # Row buffer hit rate for writes +system.physmem.avgGap 125865.44 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -235,576 +235,581 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48236473 # number of cpu cycles simulated +system.cpu.numCycles 53561071 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16941730 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12971297 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 673506 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11955063 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7993850 # Number of BTB hits +system.cpu.BPredUnit.lookups 16989438 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12991194 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 680202 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11755292 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8009849 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1846956 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114386 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12578866 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 86846522 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16941730 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9840806 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21621241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2621679 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 9822158 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 11935876 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 192083 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45946369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.646136 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.346825 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1851785 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114363 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12914479 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87008149 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16989438 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9861634 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21655288 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2666634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10515039 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 571 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11971869 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 198806 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47045662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.589318 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332778 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24346810 52.99% 52.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2176798 4.74% 57.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2018114 4.39% 62.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2096656 4.56% 66.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1493050 3.25% 69.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1410144 3.07% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 982338 2.14% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1219252 2.65% 77.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10203207 22.21% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25412140 54.02% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2169507 4.61% 58.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2024864 4.30% 62.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2094897 4.45% 67.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1497374 3.18% 70.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1417625 3.01% 73.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 986770 2.10% 75.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1225872 2.61% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10216613 21.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45946369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351222 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.800433 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14667970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8208523 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19889635 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1362773 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1817468 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3410064 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108805 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118869438 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 371525 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1817468 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16391147 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2180805 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 744758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19482609 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5329582 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116713190 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 108 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4505903 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 207 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117071318 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 537479367 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537472531 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6836 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159624 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17911694 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25668 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25645 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12679365 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29945230 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22644975 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3554453 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4308488 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112817859 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41708 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108131794 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 320520 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12061302 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28451439 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4553 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45946369 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.353435 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.992555 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47045662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.317198 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.624466 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15025286 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8880734 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19918391 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1367786 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1853465 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3434521 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108932 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 119105730 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 372945 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1853465 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16780714 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2530019 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 932679 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19483180 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5465605 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116933277 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 184 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14375 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4623545 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 215 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117254635 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 538431443 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 538426294 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5149 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 18095515 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25625 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25611 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12984960 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29963650 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22702028 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3806099 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4346835 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 113028204 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41641 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108286515 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 316116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12256138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28707838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4549 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47045662 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.301732 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.993875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10567306 23.00% 23.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8020118 17.46% 40.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7429171 16.17% 56.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7172224 15.61% 72.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5474021 11.91% 84.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3920572 8.53% 92.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1887629 4.11% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 890680 1.94% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 584648 1.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11469393 24.38% 24.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8159881 17.34% 41.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7486298 15.91% 57.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7193710 15.29% 72.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5478307 11.64% 84.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3936871 8.37% 92.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1856294 3.95% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881703 1.87% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 583205 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45946369 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47045662 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112571 4.42% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1415190 55.57% 59.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1018757 40.01% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112009 4.47% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1372514 54.80% 59.28% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1019865 40.72% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57176824 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91588 0.08% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 236 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29115499 26.93% 79.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21747640 20.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57275495 52.89% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91732 0.08% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 181 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29138143 26.91% 79.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21780957 20.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108131794 # Type of FU issued -system.cpu.iq.rate 2.241702 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2546520 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023550 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 265076321 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124946354 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106228285 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1064 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 184 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110677977 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2176777 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108286515 # Type of FU issued +system.cpu.iq.rate 2.021739 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2504390 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023127 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266438684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125354112 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106381358 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 514 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110790645 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2168801 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2634753 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7333 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27466 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2085868 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2653236 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7465 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30261 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2142984 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 473 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1817468 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 825568 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 31883 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112869381 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 345659 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29945230 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22644975 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 25238 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1097 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3023 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27466 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 452017 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 199338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 651355 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106955311 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28765738 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1176483 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1853465 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1042007 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 44975 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 113079657 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 348290 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29963650 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22702028 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 25073 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6129 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5511 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30261 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 453510 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 204690 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 658200 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107104018 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28789803 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1182497 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9814 # number of nop insts executed -system.cpu.iew.exec_refs 50205955 # number of memory reference insts executed -system.cpu.iew.exec_branches 14704580 # Number of branches executed -system.cpu.iew.exec_stores 21440217 # Number of stores executed -system.cpu.iew.exec_rate 2.217312 # Inst execution rate -system.cpu.iew.wb_sent 106472209 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106228469 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53599142 # num instructions producing a value -system.cpu.iew.wb_consumers 104275439 # num instructions consuming a value +system.cpu.iew.exec_nop 9812 # number of nop insts executed +system.cpu.iew.exec_refs 50259028 # number of memory reference insts executed +system.cpu.iew.exec_branches 14733119 # Number of branches executed +system.cpu.iew.exec_stores 21469225 # Number of stores executed +system.cpu.iew.exec_rate 1.999662 # Inst execution rate +system.cpu.iew.wb_sent 106622925 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106381514 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53628948 # num instructions producing a value +system.cpu.iew.wb_consumers 104196549 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.202244 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514015 # average fanout of values written-back +system.cpu.iew.wb_rate 1.986172 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514690 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12220612 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37155 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 567157 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44128902 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.280802 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.756042 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12431579 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 573556 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45192198 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.227131 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.747743 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14889585 33.74% 33.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11723135 26.57% 60.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3525477 7.99% 68.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2911105 6.60% 74.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1898953 4.30% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1983472 4.49% 83.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685141 1.55% 85.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 578421 1.31% 86.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5933613 13.45% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15976760 35.35% 35.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11724717 25.94% 61.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3516948 7.78% 69.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2892652 6.40% 75.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1888504 4.18% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1974510 4.37% 84.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692586 1.53% 85.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 573861 1.27% 86.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5951660 13.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44128902 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70930026 # Number of instructions committed -system.cpu.commit.committedOps 100649273 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45192198 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929711 # Number of instructions committed +system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869584 # Number of memory references committed -system.cpu.commit.loads 27310477 # Number of loads committed +system.cpu.commit.refs 47869458 # Number of memory references committed +system.cpu.commit.loads 27310414 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744874 # Number of branches committed +system.cpu.commit.branches 13744811 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486255 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5933613 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5951660 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 151039875 # The number of ROB reads -system.cpu.rob.rob_writes 227567987 # The number of ROB writes -system.cpu.timesIdled 41986 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2290104 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924474 # Number of Instructions Simulated -system.cpu.committedOps 100643721 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924474 # Number of Instructions Simulated -system.cpu.cpi 0.680110 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.680110 # CPI: Total CPI of All Threads -system.cpu.ipc 1.470350 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.470350 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 514798749 # number of integer regfile reads -system.cpu.int_regfile_writes 104102920 # number of integer regfile writes -system.cpu.fp_regfile_reads 856 # number of floating regfile reads -system.cpu.fp_regfile_writes 720 # number of floating regfile writes -system.cpu.misc_regfile_reads 145263086 # number of misc regfile reads -system.cpu.misc_regfile_writes 38578 # number of misc regfile writes -system.cpu.icache.replacements 29552 # number of replacements -system.cpu.icache.tagsinuse 1826.273597 # Cycle average of tags in use -system.cpu.icache.total_refs 11903209 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31595 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 376.743440 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 152295776 # The number of ROB reads +system.cpu.rob.rob_writes 228025366 # The number of ROB writes +system.cpu.timesIdled 74466 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6515409 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924159 # Number of Instructions Simulated +system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated +system.cpu.cpi 0.755188 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.755188 # CPI: Total CPI of All Threads +system.cpu.ipc 1.324174 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.324174 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 515451838 # number of integer regfile reads +system.cpu.int_regfile_writes 104231541 # number of integer regfile writes +system.cpu.fp_regfile_reads 698 # number of floating regfile reads +system.cpu.fp_regfile_writes 610 # number of floating regfile writes +system.cpu.misc_regfile_reads 145512549 # number of misc regfile reads +system.cpu.misc_regfile_writes 38452 # number of misc regfile writes +system.cpu.icache.replacements 31300 # number of replacements +system.cpu.icache.tagsinuse 1822.220766 # Cycle average of tags in use +system.cpu.icache.total_refs 11934433 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 33335 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 358.015089 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1826.273597 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.891735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.891735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11903210 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11903210 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11903210 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11903210 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11903210 # number of overall hits -system.cpu.icache.overall_hits::total 11903210 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 32666 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 32666 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 32666 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 32666 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 32666 # number of overall misses -system.cpu.icache.overall_misses::total 32666 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 361659000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 361659000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 361659000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 361659000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 361659000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 361659000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11935876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11935876 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11935876 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11935876 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11935876 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11935876 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11071.419825 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 11071.419825 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11071.419825 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11071.419825 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1822.220766 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.889756 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.889756 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11934443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11934443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11934443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11934443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11934443 # number of overall hits +system.cpu.icache.overall_hits::total 11934443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 37425 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 37425 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 37425 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 37425 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 37425 # number of overall misses +system.cpu.icache.overall_misses::total 37425 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 718344999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 718344999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 718344999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 718344999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 718344999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 718344999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11971868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11971868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11971868 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11971868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11971868 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11971868 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003126 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003126 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003126 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003126 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003126 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003126 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19194.255150 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19194.255150 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19194.255150 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19194.255150 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19194.255150 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1048 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.157895 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1048 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1048 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1048 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1048 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1048 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1048 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31618 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31618 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31618 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31618 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31618 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 265572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 265572000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 265572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 265572000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 265572000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 265572000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002649 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002649 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002649 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8399.392751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8399.392751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8399.392751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8399.392751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8399.392751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8399.392751 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3774 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 589350499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 589350499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 589350499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002811 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002811 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002811 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002811 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17513.610264 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17513.610264 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17513.610264 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17513.610264 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158443 # number of replacements -system.cpu.dcache.tagsinuse 4074.275674 # Cycle average of tags in use -system.cpu.dcache.total_refs 44571484 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162539 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.220243 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 222430000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4074.275674 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994696 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994696 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26246493 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26246493 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18285066 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18285066 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 20587 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 20587 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 19288 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 19288 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44531559 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44531559 # 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number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2599655000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 60196218000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 60196218000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 448500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 448500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62795873000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62795873000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62795873000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62795873000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26351541 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26351541 # 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number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20455 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20455 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44523515 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44523515 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44523515 # number of overall hits +system.cpu.dcache.overall_hits::total 44523515 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125393 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125393 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1584834 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1584834 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1710227 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1710227 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1710227 # number of overall misses +system.cpu.dcache.overall_misses::total 1710227 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4597179000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4597179000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 120104513482 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 120104513482 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 949000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 124701692482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 124701692482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 124701692482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 124701692482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26383841 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26383841 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20624 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20624 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19288 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19288 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46201442 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46201442 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46201442 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46201442 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003986 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003986 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078833 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078833 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001794 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001794 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036144 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036144 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036144 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036144 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24747.305993 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24747.305993 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38468.092802 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38468.092802 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12121.621622 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12121.621622 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37604.953760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37604.953760 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 149 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.555556 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20499 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20499 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46233742 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46233742 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46233742 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46233742 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002146 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002146 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036991 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036991 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036991 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036991 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36662.166150 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36662.166150 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75783.655248 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75783.655248 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21568.181818 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21568.181818 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72915.286966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72915.286966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72915.286966 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2506 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 608 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 117 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.418803 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128088 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79171.241920 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57405.991077 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78400.214981 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77633.599423 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57405.991077 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78400.214981 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77633.599423 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -813,69 +818,69 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 84647 # number of writebacks -system.cpu.l2cache.writebacks::total 84647 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 83 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5106 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 23122 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 28228 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 21 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 21 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102316 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102316 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5106 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125438 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130544 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5106 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125438 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130544 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187620086 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 964824313 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1152444399 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 21021 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 21021 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3752861945 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3752861945 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187620086 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4717686258 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 4905306344 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187620086 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4717686258 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 4905306344 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.416470 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.324043 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.954545 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.954545 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956046 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771741 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.672450 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.161618 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771741 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.672450 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.022718 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41727.545757 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40826.285922 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36679.130781 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36679.130781 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.022718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37609.705655 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37575.885096 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.022718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37609.705655 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37575.885096 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83948 # number of writebacks +system.cpu.l2cache.writebacks::total 83948 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4691 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21879 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26570 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102253 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102253 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4691 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124132 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4691 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124132 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128823 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210199490 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1366008240 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1576207730 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3082308 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3082308 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6824605081 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6824605081 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210199490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8190613321 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8400812811 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210199490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8190613321 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8400812811 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.393642 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299384 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955439 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955439 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.658029 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.141432 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763405 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.658029 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44809.100405 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62434.674345 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59322.835152 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10007.493506 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10007.493506 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66742.345760 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66742.345760 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44809.100405 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65983.093167 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65212.056939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44809.100405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65983.093167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65212.056939 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 88647a82b..9156fbcd7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132746 # Number of seconds simulated -sim_ticks 132746076000 # Number of ticks simulated -final_tick 132746076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132689 # Number of seconds simulated +sim_ticks 132689045000 # Number of ticks simulated +final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 594787 # Simulator instruction rate (inst/s) -host_op_rate 843423 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1121948184 # Simulator tick rate (ticks/s) -host_mem_usage 240564 # Number of bytes of host memory used -host_seconds 118.32 # Real time elapsed on the host +host_inst_rate 796611 # Simulator instruction rate (inst/s) +host_op_rate 1129615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1502004709 # Simulator tick rate (ticks/s) +host_mem_usage 239164 # Number of bytes of host memory used +host_seconds 88.34 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8003456 # Number of bytes read from this memory -system.physmem.bytes_read::total 8277184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 273728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 273728 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5403392 # Number of bytes written to this memory -system.physmem.bytes_written::total 5403392 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125054 # Number of read requests responded to by this memory -system.physmem.num_reads::total 129331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84428 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2062042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60291470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 62353512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2062042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2062042 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40704721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40704721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40704721 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2062042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60291470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 103058233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory +system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory +system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory +system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,7 +77,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 265492152 # number of cpu cycles simulated +system.cpu.numCycles 265378090 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -96,18 +96,18 @@ system.cpu.num_mem_refs 47862847 # nu system.cpu.num_load_insts 27307108 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 265492152 # Number of busy cycles +system.cpu.num_busy_cycles 265378090 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.430287 # Cycle average of tags in use +system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.430287 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847866 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847866 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -120,12 +120,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 425522000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 425522000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 425522000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 425522000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 425522000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 425522000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -138,12 +138,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22504.865665 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22504.865665 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22504.865665 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22504.865665 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22504.865665 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -158,34 +158,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 387706000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 387706000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 387706000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 387706000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 387706000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 387706000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20504.865665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20504.865665 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20504.865665 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20504.865665 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.962537 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.962537 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995352 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995352 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits @@ -206,14 +206,14 @@ system.cpu.dcache.demand_misses::cpu.data 159998 # n system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses system.cpu.dcache.overall_misses::total 159998 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1642566000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1642566000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689754000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689754000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7332320000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7332320000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7332320000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7332320000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -234,14 +234,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31011.705622 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31011.705622 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53159.372898 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53159.372898 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45827.572845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45827.572845 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45827.572845 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -250,8 +250,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 127057 # number of writebacks -system.cpu.dcache.writebacks::total 127057 # number of writebacks +system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks +system.cpu.dcache.writebacks::total 128239 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -260,14 +260,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 159998 system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1536634000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1536634000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475690000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475690000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7012324000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7012324000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7012324000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7012324000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -276,68 +276,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29011.705622 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29011.705622 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51159.372898 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51159.372898 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43827.572845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43827.572845 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 96735 # number of replacements -system.cpu.l2cache.tagsinuse 28875.776749 # Cycle average of tags in use -system.cpu.l2cache.total_refs 71387 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 127516 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.559828 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 94693 # number of replacements +system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26451.163706 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 950.000997 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1474.612046 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.807225 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.028992 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.045002 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.881219 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14631 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 30253 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 44884 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 127057 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 127057 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4691 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4691 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14631 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 34944 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 49575 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14631 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 34944 # number of overall hits -system.cpu.l2cache.overall_hits::total 49575 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4277 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 22713 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26990 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102341 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102341 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4277 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 125054 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 129331 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4277 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 125054 # number of overall misses -system.cpu.l2cache.overall_misses::total 129331 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222488000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1181138000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1403626000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321748000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5321748000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 222488000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6502886000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6725374000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 222488000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6502886000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6725374000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 51094 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14916 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits +system.cpu.l2cache.overall_hits::total 51094 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3992 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21540 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 25532 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3992 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 127812 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses +system.cpu.l2cache.overall_misses::total 127812 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207838000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1126741000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1334579000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5318574000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5318574000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 207838000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6445315000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6653153000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 207838000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6445315000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6653153000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 127057 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 127057 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses @@ -346,28 +346,28 @@ system.cpu.l2cache.demand_accesses::total 178906 # n system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.226201 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.428822 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.375518 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.956172 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.956172 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.226201 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.781597 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.722899 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.226201 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.781597 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.722899 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52019.639935 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52002.729714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.409411 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.156340 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.156340 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.252600 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52019.639935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.623731 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.252600 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52063.627255 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.238626 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52270.836597 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.136879 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.136879 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -376,52 +376,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 84428 # number of writebacks -system.cpu.l2cache.writebacks::total 84428 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4277 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 22713 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26990 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102341 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102341 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4277 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125054 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 129331 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4277 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125054 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 129331 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171164000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908582000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1079746000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4093656000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4093656000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5002238000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5173402000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5002238000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5173402000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.428822 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.375518 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956172 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956172 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.722899 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.226201 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.781597 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.722899 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40019.639935 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40002.729714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.409411 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.156340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.156340 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40019.639935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.623731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.252600 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks +system.cpu.l2cache.writebacks::total 83909 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 1d85fdbdf..ea44c1e9f 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202343 # Number of seconds simulated -sim_ticks 202342809000 # Number of ticks simulated -final_tick 202342809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202242 # Number of seconds simulated +sim_ticks 202242260000 # Number of ticks simulated +final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1232815 # Simulator instruction rate (inst/s) -host_op_rate 1248778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1856050290 # Simulator tick rate (ticks/s) -host_mem_usage 230736 # Number of bytes of host memory used -host_seconds 109.02 # Real time elapsed on the host +host_inst_rate 1258181 # Simulator instruction rate (inst/s) +host_op_rate 1274472 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1893298806 # Simulator tick rate (ticks/s) +host_mem_usage 233128 # Number of bytes of host memory used +host_seconds 106.82 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 665664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7906112 # Number of bytes read from this memory -system.physmem.bytes_read::total 8571776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 665664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 665664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5301376 # Number of bytes written to this memory -system.physmem.bytes_written::total 5301376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10401 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 133934 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82834 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82834 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3289783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39072859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 42362642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3289783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3289783 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26199972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26199972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26199972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3289783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39072859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 68562614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory +system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory +system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory +system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory +system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404685618 # number of cpu cycles simulated +system.cpu.numCycles 404484520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -54,18 +54,18 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 404685618 # Number of busy cycles +system.cpu.num_busy_cycles 404484520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.814192 # Cycle average of tags in use +system.cpu.icache.tagsinuse 2004.815325 # Cycle average of tags in use system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 144074079000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.814192 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978913 # Average percentage of cache occupancy +system.cpu.icache.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -78,12 +78,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2868177000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2868177000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2868177000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2868177000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2868177000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2868177000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -96,12 +96,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15335.876679 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15335.876679 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15335.876679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15335.876679 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15335.876679 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,34 +116,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2494129000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2494129000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2494129000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2494129000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2494129000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2494129000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2445633000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2445633000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2445633000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2445633000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2445633000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2445633000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13335.876679 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13335.876679 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13335.876679 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13335.876679 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13076.573060 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13076.573060 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.652500 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.652500 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997962 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997962 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits @@ -164,16 +164,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1523847000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1523847000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5622992000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5622992000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7146839000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7146839000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7146839000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7146839000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -194,16 +194,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33491.878942 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33491.878942 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53468.791602 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53468.791602 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47435.926538 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47435.926538 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47435.926538 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,8 +212,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 122378 # number of writebacks -system.cpu.dcache.writebacks::total 122378 # number of writebacks +system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks +system.cpu.dcache.writebacks::total 123970 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -224,16 +224,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1432849000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1432849000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5412664000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5412664000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6845513000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6845513000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6845513000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6845513000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -244,70 +244,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31491.878942 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31491.878942 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51468.791602 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51468.791602 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45435.926538 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45435.926538 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 101560 # number of replacements -system.cpu.l2cache.tagsinuse 29290.996090 # Cycle average of tags in use -system.cpu.l2cache.total_refs 222505 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 132357 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.681097 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 98540 # number of replacements +system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use +system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129534 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 1.751918 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 24775.786415 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3266.546663 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1248.663012 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.756097 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.099687 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.038106 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.893890 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 176623 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 23301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 199924 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 122378 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 122378 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3844 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3844 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 176623 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 27145 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 203768 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 176623 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 27145 # number of overall hits -system.cpu.l2cache.overall_hits::total 203768 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 10401 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 22198 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 32599 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101335 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101335 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10401 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123533 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 133934 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10401 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123533 # number of overall misses -system.cpu.l2cache.overall_misses::total 133934 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 540875000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1154340000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1695215000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5269420000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5269420000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 540875000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6423760000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6964635000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 540875000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6423760000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6964635000 # number of overall miss cycles +system.cpu.l2cache.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.941490 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 123970 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 123970 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 3923 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 3923 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 177782 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 28387 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 206169 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 177782 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 28387 # number of overall hits +system.cpu.l2cache.overall_hits::total 206169 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 9242 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21035 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 30277 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101256 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101256 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9242 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 122291 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 131533 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses +system.cpu.l2cache.overall_misses::total 131533 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 480789000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1093974000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1574763000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5265313000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5265313000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 480789000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6359287000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6840076000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 480789000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6359287000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6840076000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 122378 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 122378 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 123970 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 123970 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses @@ -316,28 +316,28 @@ system.cpu.l2cache.demand_accesses::total 337702 # n system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.055613 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.487879 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.140197 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.963453 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.963453 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.055613 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.819848 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.396604 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.055613 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.819848 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.396604 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52002.211326 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.982161 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52002.055278 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.500246 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52002.211326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.356180 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.500246 # average overall miss latency +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.049416 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.462318 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.130211 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962702 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.962702 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.049416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.811605 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.389494 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.181346 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.321131 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.857185 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.009876 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.009876 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52002.736956 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52002.736956 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,52 +346,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 82834 # number of writebacks -system.cpu.l2cache.writebacks::total 82834 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10401 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 22198 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 32599 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 369885000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 841554000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1211439000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4050241000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4050241000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 369885000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4891795000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5261680000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 369885000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4891795000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5261680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.181346 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.321131 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.857185 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.009876 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.009876 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |