diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref')
6 files changed, 2174 insertions, 2174 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 9b354cbb8..fc992598c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043732 # Number of seconds simulated -sim_ticks 43731802500 # Number of ticks simulated -final_tick 43731802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043769 # Number of seconds simulated +sim_ticks 43769191000 # Number of ticks simulated +final_tick 43769191000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69429 # Simulator instruction rate (inst/s) -host_op_rate 69429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34369620 # Simulator tick rate (ticks/s) -host_mem_usage 233240 # Number of bytes of host memory used -host_seconds 1272.40 # Real time elapsed on the host +host_inst_rate 112888 # Simulator instruction rate (inst/s) +host_op_rate 112888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55931443 # Simulator tick rate (ticks/s) +host_mem_usage 233228 # Number of bytes of host memory used +host_seconds 782.55 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10394998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 231830554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242225552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10394998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10394998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166830718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166830718 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166830718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10394998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 231830554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 409056270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10386118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 231632520 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242018638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10386118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10386118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166688208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166688208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166688208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10386118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 231632520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 408706846 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165515 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady @@ -43,22 +43,22 @@ system.physmem.bytesConsumedRd 10592960 # by system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10376 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10439 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10013 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10351 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10256 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10015 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10350 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10362 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10273 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10480 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10188 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10237 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10593 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis @@ -77,7 +77,7 @@ system.physmem.perBankWrReqs::14 7283 # Tr system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 43731782000 # Total gap between requests +system.physmem.totGap 43769170000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -92,10 +92,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 72899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 72862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71499 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4910 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,12 +124,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4951 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see @@ -147,209 +147,209 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 366.074289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.394514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 748.149039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 19835 40.59% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7665 15.69% 56.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4199 8.59% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2953 6.04% 70.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2157 4.41% 75.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1715 3.51% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1297 2.65% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1110 2.27% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 804 1.65% 85.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 685 1.40% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 483 0.99% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 536 1.10% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 409 0.84% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 338 0.69% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 255 0.52% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 348 0.71% 91.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 228 0.47% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 211 0.43% 92.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 159 0.33% 92.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 209 0.43% 93.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 394 0.81% 94.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 305 0.62% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 602 1.23% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 201 0.41% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 151 0.31% 97.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 39 0.08% 97.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 155 0.32% 97.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 66 0.14% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 55 0.11% 97.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 29 0.06% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 79 0.16% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 48826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 366.351698 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.645495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 749.158032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 19754 40.46% 40.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7696 15.76% 56.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4247 8.70% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2897 5.93% 70.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2142 4.39% 75.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1740 3.56% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1303 2.67% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1111 2.28% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 826 1.69% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 678 1.39% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 468 0.96% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 525 1.08% 88.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 411 0.84% 89.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 341 0.70% 90.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 262 0.54% 90.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 362 0.74% 91.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 210 0.43% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 226 0.46% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 155 0.32% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 229 0.47% 93.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 390 0.80% 94.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 303 0.62% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 582 1.19% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 207 0.42% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 152 0.31% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 46 0.09% 97.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 145 0.30% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 73 0.15% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 52 0.11% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 28 0.06% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 72 0.15% 98.18% # Bytes accessed per row activation system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 46 0.09% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 24 0.05% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 45 0.09% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 30 0.06% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 23 0.05% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 17 0.03% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 14 0.03% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 23 0.05% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 11 0.02% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 12 0.02% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.02% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 10 0.02% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 6 0.01% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 12 0.02% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 5 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 7 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 6 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 6 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 42 0.09% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 23 0.05% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.10% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 25 0.05% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 11 0.02% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 23 0.05% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 7 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 13 0.03% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 21 0.04% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 13 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 14 0.03% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 8 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 9 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 5 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 3 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 8 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 3 0.01% 99.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 9 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 6 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 6 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 5 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 6 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 8 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 12 0.02% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48863 # Bytes accessed per row activation -system.physmem.totQLat 6289978250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8777494500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::total 48826 # Bytes accessed per row activation +system.physmem.totQLat 6287289000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8773086500 # Sum of mem lat for all requests system.physmem.totBusLat 827575000 # Total cycles spent in databus access -system.physmem.totBankLat 1659941250 # Total cycles spent in bank access -system.physmem.avgQLat 38002.47 # Average queueing delay per request -system.physmem.avgBankLat 10028.95 # Average bank access latency per request +system.physmem.totBankLat 1658222500 # Total cycles spent in bank access +system.physmem.avgQLat 37986.22 # Average queueing delay per request +system.physmem.avgBankLat 10018.56 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53031.41 # Average memory access latency -system.physmem.avgRdBW 242.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 166.83 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 242.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 166.83 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53004.78 # Average memory access latency +system.physmem.avgRdBW 242.02 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 166.69 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 242.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 166.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.busUtil 3.19 # Data bus utilization in percentage system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 10.42 # Average write queue length over time -system.physmem.readRowHits 153768 # Number of row buffer hits during reads -system.physmem.writeRowHits 76872 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.90 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.43 # Row buffer hit rate for writes -system.physmem.avgGap 156457.62 # Average gap between requests -system.membus.throughput 409056270 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 34624 # Transaction distribution -system.membus.trans_dist::ReadResp 34624 # Transaction distribution +system.physmem.avgWrQLen 10.49 # Average write queue length over time +system.physmem.readRowHits 153779 # Number of row buffer hits during reads +system.physmem.writeRowHits 76898 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.46 # Row buffer hit rate for writes +system.physmem.avgGap 156591.38 # Average gap between requests +system.membus.throughput 408706846 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 34625 # Transaction distribution +system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution -system.membus.trans_dist::ReadExReq 130891 # Transaction distribution -system.membus.trans_dist::ReadExResp 130891 # Transaction distribution +system.membus.trans_dist::ReadExReq 130890 # Transaction distribution +system.membus.trans_dist::ReadExResp 130890 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes) system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1215256500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1218896000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1522914250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1522799000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) -system.cpu.branchPred.lookups 18742056 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318265 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4775163 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15487144 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4660091 # Number of BTB hits +system.cpu.branchPred.lookups 18742730 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318368 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15507340 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664027 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.090061 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660966 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 30.076254 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277593 # DTB read hits +system.cpu.dtb.read_hits 20277790 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367741 # DTB read accesses -system.cpu.dtb.write_hits 14728959 # DTB write hits +system.cpu.dtb.read_accesses 20367938 # DTB read accesses +system.cpu.dtb.write_hits 14728966 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736211 # DTB write accesses -system.cpu.dtb.data_hits 35006552 # DTB hits +system.cpu.dtb.write_accesses 14736218 # DTB write accesses +system.cpu.dtb.data_hits 35006756 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103952 # DTB accesses -system.cpu.itb.fetch_hits 12367361 # ITB hits -system.cpu.itb.fetch_misses 10891 # ITB misses +system.cpu.dtb.data_accesses 35104156 # DTB accesses +system.cpu.itb.fetch_hits 12367759 # ITB hits +system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378252 # ITB accesses +system.cpu.itb.fetch_accesses 12378780 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -363,34 +363,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87463606 # number of cpu cycles simulated +system.cpu.numCycles 87538383 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8070350 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10671706 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74169774 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074238 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668492 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74161920 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126489024 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66036 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126481170 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293666 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14166320 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060384 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447706 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216957 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4664663 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9107934 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.869161 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44778070 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14174454 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060070 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77195811 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77194023 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 233969 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17892398 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69571208 # Number of cycles cpu stages are processed. -system.cpu.activity 79.543036 # Percentage of cycles cpu is active +system.cpu.timesIdled 231301 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17962893 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575490 # Number of cycles cpu stages are processed. +system.cpu.activity 79.479981 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -402,214 +402,214 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.990072 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.990918 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.990072 # CPI: Total CPI of All Threads -system.cpu.ipc 1.010028 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.990918 # CPI: Total CPI of All Threads +system.cpu.ipc 1.009165 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.010028 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34814257 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52649349 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.195722 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45010578 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42453028 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.537935 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44433795 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43029811 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.197390 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65350614 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22112992 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.282507 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41414421 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46049185 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.649539 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 84399 # number of replacements -system.cpu.icache.tagsinuse 1906.561640 # Cycle average of tags in use -system.cpu.icache.total_refs 12250118 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 86445 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.709966 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1906.561640 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.930938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.930938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12250118 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250118 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250118 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250118 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250118 # number of overall hits -system.cpu.icache.overall_hits::total 12250118 # number of overall hits +system.cpu.ipc_total 1.009165 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34882792 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655591 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.151432 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45083196 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455187 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.498939 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44507774 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030609 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.156276 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65417325 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22121058 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.270124 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41496378 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46042005 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.596362 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.tags.replacements 84371 # number of replacements +system.cpu.icache.tags.tagsinuse 1906.602529 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250515 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760475 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1906.602529 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930958 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930958 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250515 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250515 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250515 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250515 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250515 # number of overall hits +system.cpu.icache.overall_hits::total 12250515 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 117235 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 117235 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 117235 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 117235 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 117235 # number of overall misses system.cpu.icache.overall_misses::total 117235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2039550500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2039550500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2039550500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2039550500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2039550500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2039550500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12367353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12367353 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12367353 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12367353 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12367353 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12367353 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2053420481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2053420481 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2053420481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2053420481 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2053420481 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2053420481 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12367750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367750 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367750 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367750 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367750 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367750 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009479 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.009479 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.009479 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.009479 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009479 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009479 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17397.112637 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17397.112637 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17397.112637 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17397.112637 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17397.112637 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17397.112637 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 661 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 188 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17515.421854 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17515.421854 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17515.421854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17515.421854 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17515.421854 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 365 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 36.722222 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.812500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30790 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30790 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30790 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30790 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30790 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30790 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86445 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 86445 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 86445 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 86445 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 86445 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 86445 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1457986019 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1457986019 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1457986019 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1457986019 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1457986019 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1457986019 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006990 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006990 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006990 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006990 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16866.053780 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16866.053780 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16866.053780 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16866.053780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16866.053780 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16866.053780 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30818 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30818 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30818 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30818 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30818 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30818 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1462353516 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1462353516 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1462353516 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1462353516 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1462353516 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16922.058345 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16922.058345 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16922.058345 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16922.058345 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 671941569 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 147022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 147022 # Transaction distribution +system.cpu.toL2Bus.throughput 671326642 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143770 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143770 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172890 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 172834 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577046 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 749936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5532480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 749880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5530688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23852736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29385216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29385216 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size 29383424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397924000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 129676981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 131178984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 306529482 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 326782984 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.l2cache.replacements 131592 # number of replacements -system.cpu.l2cache.tagsinuse 30902.534146 # Cycle average of tags in use -system.cpu.l2cache.total_refs 151462 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163650 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.925524 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27127.756920 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2008.955025 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1765.822201 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.827873 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.061308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.053889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.943071 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 79342 # number of ReadReq hits +system.cpu.l2cache.tags.replacements 131591 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30902.226523 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27124.475533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.439767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1770.311223 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.827773 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061262 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054026 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.943061 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 112398 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 168352 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 168352 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 79342 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 45935 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125277 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082168 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569187 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082168 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86404.621938 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4076.684340 # Cycle average of tags in use -system.cpu.dcache.total_refs 33754860 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 165.184025 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 292193000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.684340 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995284 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995284 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180280 # 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number of replacements +system.cpu.dcache.tags.tagsinuse 4076.642006 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33754840 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.183927 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 293009000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.642006 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995274 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995274 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180271 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180271 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574569 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574569 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754840 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754840 # number of overall hits +system.cpu.dcache.overall_hits::total 33754840 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96367 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96367 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038808 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038808 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135175 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135175 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135175 # number of overall misses +system.cpu.dcache.overall_misses::total 1135175 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010614984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5010614984 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 87491278500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 87491278500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92501893484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92501893484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92501893484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92501893484 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -706,40 +706,40 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51581.108989 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51581.108989 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83950.870093 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83950.870093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 81203.152433 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 81203.152433 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5824366 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116607 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071086 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071086 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51995.133023 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51995.133023 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84222.761569 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84222.761569 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81486.901565 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81486.901565 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81486.901565 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5878259 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 106 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116796 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.948682 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.329284 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 106 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks system.cpu.dcache.writebacks::total 168352 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35591 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35591 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895217 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895217 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930808 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930808 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930808 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930808 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35600 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35600 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895228 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895228 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930828 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930828 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930828 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930828 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -748,14 +748,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2407208517 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2407208517 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14006251501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14006251501 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16413460018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16413460018 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16413460018 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16413460018 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2409027516 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2409027516 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14018315000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14018315000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16427342516 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16427342516 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16427342516 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16427342516 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -764,14 +764,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39613.746227 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39613.746227 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97550.156714 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97550.156714 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39643.680221 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39643.680221 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97634.176069 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97634.176069 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80389.447929 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80389.447929 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 42c254d5a..a1c1e25d4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024943 # Number of seconds simulated -sim_ticks 24942850000 # Number of ticks simulated -final_tick 24942850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024977 # Number of seconds simulated +sim_ticks 24977022500 # Number of ticks simulated +final_tick 24977022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 187895 # Simulator instruction rate (inst/s) -host_op_rate 187895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58883311 # Simulator tick rate (ticks/s) +host_inst_rate 130696 # Simulator instruction rate (inst/s) +host_op_rate 130696 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41014411 # Simulator tick rate (ticks/s) host_mem_usage 236320 # Number of bytes of host memory used -host_seconds 423.60 # Real time elapsed on the host +host_seconds 608.98 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153472 # Number of bytes read from this memory -system.physmem.bytes_read::total 10643968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296640 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296640 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158648 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114010 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114010 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19664794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 407069441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 426734234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19664794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19664794 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 292534333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 292534333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 292534333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19664794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 407069441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 719268568 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166312 # Total number of read requests seen -system.physmem.writeReqs 114010 # Total number of write requests seen -system.physmem.cpureqs 280322 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10643968 # Total number of bytes read from memory -system.physmem.bytesWritten 7296640 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10643968 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296640 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153536 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297024 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158649 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166305 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114016 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114016 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19617390 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 406515068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 426132458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19617390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19617390 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 292149475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 292149475 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 292149475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19617390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 406515068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 718281933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166305 # Total number of read requests seen +system.physmem.writeReqs 114016 # Total number of write requests seen +system.physmem.cpureqs 280321 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10643520 # Total number of bytes read from memory +system.physmem.bytesWritten 7297024 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10643520 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7297024 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10055 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 10232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10278 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10621 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10312 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10060 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10430 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10408 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9844 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10548 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10226 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10618 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10625 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7260 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7177 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6943 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6990 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6967 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24942817000 # Total gap between requests +system.physmem.totGap 24976988500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166312 # Categorize read packet sizes +system.physmem.readPktSize::6 166305 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114010 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 73936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60757 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 25960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114016 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 72274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 34114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,9 +124,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4953 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see @@ -146,208 +146,208 @@ system.physmem.wrQLenPdf::18 4957 # Wh system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 49789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 360.286489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 169.159256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 741.433360 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 20689 41.55% 41.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7785 15.64% 57.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4196 8.43% 65.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3037 6.10% 71.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2069 4.16% 75.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1703 3.42% 79.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1326 2.66% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1152 2.31% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 751 1.51% 85.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 622 1.25% 87.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 468 0.94% 87.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 538 1.08% 89.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 428 0.86% 89.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 311 0.62% 90.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 271 0.54% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 335 0.67% 91.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 282 0.57% 92.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 173 0.35% 92.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 131 0.26% 92.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 297 0.60% 93.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 411 0.83% 94.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 172 0.35% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 311 0.62% 95.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 639 1.28% 96.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 258 0.52% 97.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 81 0.16% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 48 0.10% 97.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 163 0.33% 97.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 101 0.20% 97.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 35 0.07% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 33 0.07% 98.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 83 0.17% 98.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 54 0.11% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 28 0.06% 98.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 37 0.07% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 43 0.09% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 20 0.04% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 23 0.05% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 20 0.04% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 10 0.02% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 11 0.02% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 8 0.02% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 16 0.03% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 8 0.02% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 7 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 49952 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 359.130045 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.640646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 741.801736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 20814 41.67% 41.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7820 15.66% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4185 8.38% 65.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3013 6.03% 71.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2148 4.30% 76.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1700 3.40% 79.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1301 2.60% 82.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1098 2.20% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 776 1.55% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 657 1.32% 87.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 496 0.99% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 568 1.14% 89.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 406 0.81% 90.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 302 0.60% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 268 0.54% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 357 0.71% 91.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 241 0.48% 92.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 170 0.34% 92.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 145 0.29% 93.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 323 0.65% 93.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 351 0.70% 94.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 146 0.29% 94.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 301 0.60% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 689 1.38% 96.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 236 0.47% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 76 0.15% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 36 0.07% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 184 0.37% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 89 0.18% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 34 0.07% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 40 0.08% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 93 0.19% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 64 0.13% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 19 0.04% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 44 0.09% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 19 0.04% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 19 0.04% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 36 0.07% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 21 0.04% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 12 0.02% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 20 0.04% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 10 0.02% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 10 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 17 0.03% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 15 0.03% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 9 0.02% 99.03% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 17 0.03% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 10 0.02% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 8 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 7 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 8 0.02% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 8 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 10 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 8 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 9 0.02% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 10 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.02% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 8 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 4 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 5 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 6 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 5 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 5 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 6 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 8 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 13 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 5 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 9 0.02% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 5 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 10 0.02% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 165 0.33% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 49789 # Bytes accessed per row activation -system.physmem.totQLat 6526905250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 8951626500 # Sum of mem lat for all requests -system.physmem.totBusLat 831550000 # Total cycles spent in databus access -system.physmem.totBankLat 1593171250 # Total cycles spent in bank access -system.physmem.avgQLat 39245.42 # Average queueing delay per request -system.physmem.avgBankLat 9579.53 # Average bank access latency per request +system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 11 0.02% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 7 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 169 0.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49952 # Bytes accessed per row activation +system.physmem.totQLat 6557959000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8953517750 # Sum of mem lat for all requests +system.physmem.totBusLat 831510000 # Total cycles spent in databus access +system.physmem.totBankLat 1564048750 # Total cycles spent in bank access +system.physmem.avgQLat 39434.04 # Average queueing delay per request +system.physmem.avgBankLat 9404.87 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53824.94 # Average memory access latency -system.physmem.avgRdBW 426.73 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 292.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 426.73 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 292.53 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53838.91 # Average memory access latency +system.physmem.avgRdBW 426.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 292.15 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 426.13 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 292.15 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.62 # Data bus utilization in percentage +system.physmem.busUtil 5.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.36 # Average read queue length over time -system.physmem.avgWrQLen 10.09 # Average write queue length over time -system.physmem.readRowHits 154174 # Number of row buffer hits during reads -system.physmem.writeRowHits 76335 # Number of row buffer hits during writes -system.physmem.readRowHitRate 92.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.95 # Row buffer hit rate for writes -system.physmem.avgGap 88979.16 # Average gap between requests -system.membus.throughput 719268568 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35517 # Transaction distribution -system.membus.trans_dist::ReadResp 35517 # Transaction distribution -system.membus.trans_dist::Writeback 114010 # Transaction distribution -system.membus.trans_dist::ReadExReq 130795 # Transaction distribution -system.membus.trans_dist::ReadExResp 130795 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 446634 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 446634 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940608 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 17940608 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17940608 # Total data (bytes) +system.physmem.avgWrQLen 9.86 # Average write queue length over time +system.physmem.readRowHits 154145 # Number of row buffer hits during reads +system.physmem.writeRowHits 76216 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.85 # Row buffer hit rate for writes +system.physmem.avgGap 89101.38 # Average gap between requests +system.membus.throughput 718281933 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35508 # Transaction distribution +system.membus.trans_dist::ReadResp 35508 # Transaction distribution +system.membus.trans_dist::Writeback 114016 # Transaction distribution +system.membus.trans_dist::ReadExReq 130797 # Transaction distribution +system.membus.trans_dist::ReadExResp 130797 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 446626 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 446626 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940544 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1221780000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 4.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 1527507000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.1 # Layer utilization (%) -system.cpu.branchPred.lookups 16555988 # Number of BP lookups -system.cpu.branchPred.condPredicted 10692092 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 419935 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11595461 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7351910 # Number of BTB hits +system.membus.reqLayer0.occupancy 1244155000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1541382250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +system.cpu.branchPred.lookups 16531947 # Number of BP lookups +system.cpu.branchPred.condPredicted 10672978 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 414050 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11481292 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7335496 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.403344 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990234 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41425 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.890858 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1991572 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40927 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22410816 # DTB read hits -system.cpu.dtb.read_misses 219473 # DTB read misses -system.cpu.dtb.read_acv 42 # DTB read access violations -system.cpu.dtb.read_accesses 22630289 # DTB read accesses -system.cpu.dtb.write_hits 15705108 # DTB write hits -system.cpu.dtb.write_misses 41065 # DTB write misses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15746173 # DTB write accesses -system.cpu.dtb.data_hits 38115924 # DTB hits -system.cpu.dtb.data_misses 260538 # DTB misses -system.cpu.dtb.data_acv 44 # DTB access violations -system.cpu.dtb.data_accesses 38376462 # DTB accesses -system.cpu.itb.fetch_hits 13936543 # ITB hits -system.cpu.itb.fetch_misses 35109 # ITB misses +system.cpu.dtb.read_hits 22403443 # DTB read hits +system.cpu.dtb.read_misses 219972 # DTB read misses +system.cpu.dtb.read_acv 45 # DTB read access violations +system.cpu.dtb.read_accesses 22623415 # DTB read accesses +system.cpu.dtb.write_hits 15699616 # DTB write hits +system.cpu.dtb.write_misses 41064 # DTB write misses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_accesses 15740680 # DTB write accesses +system.cpu.dtb.data_hits 38103059 # DTB hits +system.cpu.dtb.data_misses 261036 # DTB misses +system.cpu.dtb.data_acv 46 # DTB access violations +system.cpu.dtb.data_accesses 38364095 # DTB accesses +system.cpu.itb.fetch_hits 13905618 # ITB hits +system.cpu.itb.fetch_misses 35229 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13971652 # ITB accesses +system.cpu.itb.fetch_accesses 13940847 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -361,139 +361,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49885704 # number of cpu cycles simulated +system.cpu.numCycles 49954048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15828757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105472202 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16555988 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9342144 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19569330 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2015634 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7564714 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 312127 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13936543 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 209148 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44745227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.357172 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120107 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15782352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105305571 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16531947 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9327068 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19535430 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1996105 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7525610 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314470 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13905618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 207845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44615196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.360307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120920 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25175897 56.26% 56.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1533640 3.43% 59.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1372500 3.07% 62.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510966 3.38% 66.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4145174 9.26% 75.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1852523 4.14% 79.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 674526 1.51% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069811 2.39% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7410190 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25079766 56.21% 56.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1526701 3.42% 59.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1368492 3.07% 62.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1511592 3.39% 66.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137930 9.27% 75.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1849422 4.15% 79.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 676249 1.52% 81.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069566 2.40% 83.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7395478 16.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44745227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.331878 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.114277 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16915257 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7099488 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18565359 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 807394 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1357729 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3748109 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103728039 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304294 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1357729 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17378057 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4787405 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 84706 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18857243 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2280087 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102449322 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 562 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2762 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2150788 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61699088 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123470125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123020099 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 450026 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44615196 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.330943 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.108049 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16870832 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7056928 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18547803 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 794977 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1344656 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3743758 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107019 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103586885 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 307942 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1344656 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17339272 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4755583 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85639 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18836599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2253447 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102335224 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 557 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2492 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2137772 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61631332 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123302278 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122850608 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 451670 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9152207 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5534 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4701242 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23248702 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16281518 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1196604 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 458974 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90797694 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5272 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88473068 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98121 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10747304 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4709427 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 689 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44745227 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.977263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.106527 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9084451 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5532 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5530 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4823408 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23239875 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16264209 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1185310 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 465013 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90722071 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5344 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88415019 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95015 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10694229 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4666218 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 761 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44615196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.981724 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109954 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16442789 36.75% 36.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6947095 15.53% 52.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5617294 12.55% 64.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4751397 10.62% 75.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4688341 10.48% 85.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649423 5.92% 91.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1924303 4.30% 96.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1305783 2.92% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 418802 0.94% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16409410 36.78% 36.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6866152 15.39% 52.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5567351 12.48% 64.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4772569 10.70% 75.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4725060 10.59% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2625070 5.88% 91.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1917083 4.30% 96.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1291638 2.90% 99.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 440863 0.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44745227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44615196 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126164 6.77% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 785807 42.18% 48.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 951202 51.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126842 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 784071 42.12% 48.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 950643 51.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49382358 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43890 0.05% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121219 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121003 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49344695 55.81% 55.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43834 0.05% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121349 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121152 0.14% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38963 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -515,84 +515,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22865563 25.84% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15899938 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22855764 25.85% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15889119 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88473068 # Type of FU issued -system.cpu.iq.rate 1.773515 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1863173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021059 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223048793 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101154216 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86567905 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603864 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414189 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294216 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90034241 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 302000 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1467603 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88415019 # Type of FU issued +system.cpu.iq.rate 1.769927 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1861556 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021055 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222796879 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101023469 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86533748 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 604926 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 415943 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294379 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89974024 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302551 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1471412 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2972064 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5071 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18375 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1668141 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2963237 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4955 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18224 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1650832 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2922 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 100269 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2867 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 96301 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1357729 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3744152 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 78814 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100285943 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219681 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23248702 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16281518 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5272 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60147 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 593 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18375 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 199378 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160408 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 359786 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87617560 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22633363 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 855508 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1344656 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3651094 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 72855 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100203758 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 216158 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23239875 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16264209 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5344 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49772 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6561 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18224 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 192723 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161669 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 354392 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87578159 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22626447 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 836860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9482977 # number of nop insts executed -system.cpu.iew.exec_refs 38379854 # number of memory reference insts executed -system.cpu.iew.exec_branches 15087965 # Number of branches executed -system.cpu.iew.exec_stores 15746491 # Number of stores executed -system.cpu.iew.exec_rate 1.756366 # Inst execution rate -system.cpu.iew.wb_sent 87252732 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86862121 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33357056 # num instructions producing a value -system.cpu.iew.wb_consumers 43763173 # num instructions consuming a value +system.cpu.iew.exec_nop 9476343 # number of nop insts executed +system.cpu.iew.exec_refs 38367436 # number of memory reference insts executed +system.cpu.iew.exec_branches 15087087 # Number of branches executed +system.cpu.iew.exec_stores 15740989 # Number of stores executed +system.cpu.iew.exec_rate 1.753174 # Inst execution rate +system.cpu.iew.wb_sent 87216851 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86828127 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33345535 # num instructions producing a value +system.cpu.iew.wb_consumers 43468305 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.741223 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762217 # average fanout of values written-back +system.cpu.iew.wb_rate 1.738160 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767123 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8947131 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8869178 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 315269 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43387498 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.036086 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.786442 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 309326 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43270540 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.041589 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791914 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20491808 47.23% 47.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7040185 16.23% 63.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3430647 7.91% 71.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2065344 4.76% 76.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2060078 4.75% 80.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1160326 2.67% 83.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1096269 2.53% 86.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 719123 1.66% 87.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5323718 12.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20425554 47.20% 47.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7044262 16.28% 63.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3374707 7.80% 71.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2054728 4.75% 76.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2036437 4.71% 80.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1166697 2.70% 83.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1108378 2.56% 86.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 724905 1.68% 87.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5334872 12.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43387498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43270540 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,212 +603,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5323718 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5334872 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 134034241 # The number of ROB reads -system.cpu.rob.rob_writes 195936054 # The number of ROB writes -system.cpu.timesIdled 84426 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5140477 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133828176 # The number of ROB reads +system.cpu.rob.rob_writes 195767077 # The number of ROB writes +system.cpu.timesIdled 83938 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5338852 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.626770 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.626770 # CPI: Total CPI of All Threads -system.cpu.ipc 1.595482 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.595482 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115957750 # number of integer regfile reads -system.cpu.int_regfile_writes 57532597 # number of integer regfile writes -system.cpu.fp_regfile_reads 249573 # number of floating regfile reads -system.cpu.fp_regfile_writes 239887 # number of floating regfile writes -system.cpu.misc_regfile_reads 38017 # number of misc regfile reads +system.cpu.cpi 0.627628 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.627628 # CPI: Total CPI of All Threads +system.cpu.ipc 1.593299 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.593299 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115893073 # number of integer regfile reads +system.cpu.int_regfile_writes 57500612 # number of integer regfile writes +system.cpu.fp_regfile_reads 249654 # number of floating regfile reads +system.cpu.fp_regfile_writes 240130 # number of floating regfile writes +system.cpu.misc_regfile_reads 38049 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1201112463 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155760 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155759 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143412 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 187195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580089 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 767284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5990208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23968960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 29959168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29959168 # Total data (bytes) +system.cpu.toL2Bus.throughput 1198592827 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155432 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155431 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 186551 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 580061 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 766612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 5969600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23967680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29937280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29937280 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 402997500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402814500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 140404482 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141571734 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308361998 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.icache.replacements 91549 # number of replacements -system.cpu.icache.tagsinuse 1926.731072 # Cycle average of tags in use -system.cpu.icache.total_refs 13830286 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93597 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 147.764202 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 20183588000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1926.731072 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.940787 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.940787 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13830286 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13830286 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13830286 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13830286 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13830286 # number of overall hits -system.cpu.icache.overall_hits::total 13830286 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106255 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106255 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106255 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106255 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106255 # number of overall misses -system.cpu.icache.overall_misses::total 106255 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2059581499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2059581499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2059581499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2059581499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2059581499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2059581499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13936541 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13936541 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13936541 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13936541 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13936541 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13936541 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007624 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007624 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007624 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007624 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007624 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007624 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19383.384302 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19383.384302 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19383.384302 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19383.384302 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19383.384302 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19383.384302 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 622 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 327076000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.icache.tags.replacements 91227 # number of replacements +system.cpu.icache.tags.tagsinuse 1926.280031 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13799737 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93275 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.946792 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20172265250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1926.280031 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940566 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940566 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13799737 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13799737 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13799737 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13799737 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13799737 # number of overall hits +system.cpu.icache.overall_hits::total 13799737 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 105880 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 105880 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 105880 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 105880 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 105880 # number of overall misses +system.cpu.icache.overall_misses::total 105880 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2067336982 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2067336982 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2067336982 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2067336982 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2067336982 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2067336982 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13905617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13905617 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13905617 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13905617 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13905617 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13905617 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007614 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007614 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007614 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007614 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007614 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007614 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19525.283170 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19525.283170 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19525.283170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19525.283170 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19525.283170 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 44.428571 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 35.812500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12657 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12657 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12657 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12657 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12657 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12657 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93598 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93598 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93598 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93598 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93598 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93598 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1582060018 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1582060018 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1582060018 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1582060018 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1582060018 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1582060018 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006716 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006716 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006716 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006716 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16902.711789 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16902.711789 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16902.711789 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16902.711789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16902.711789 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16902.711789 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1751974750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2290253750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12463858000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12463858000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538279000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14215832750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14754111750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538279000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14215832750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14754111750 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70298.942144 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62903.014146 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64497.838576 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95291.619838 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95291.619838 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70298.942144 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70298.942144 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89605.561649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88716.653338 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201478 # number of replacements -system.cpu.dcache.tagsinuse 4074.502987 # Cycle average of tags in use -system.cpu.dcache.total_refs 34204494 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205574 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.385311 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 214402000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4074.502987 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994752 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994752 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20630348 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20630348 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574089 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574089 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34204437 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34204437 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34204437 # number of overall hits -system.cpu.dcache.overall_hits::total 34204437 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 266891 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 266891 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039288 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039288 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306179 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306179 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306179 # number of overall misses -system.cpu.dcache.overall_misses::total 1306179 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15635191500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15635191500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89961325949 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89961325949 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105596517449 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105596517449 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105596517449 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105596517449 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20897239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20897239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.replacements 201470 # number of replacements +system.cpu.dcache.tags.tagsinuse 4074.474898 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34190075 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205566 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.321644 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 215349000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4074.474898 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994745 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994745 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20615905 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20615905 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574108 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574108 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34190013 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34190013 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34190013 # number of overall hits +system.cpu.dcache.overall_hits::total 34190013 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267467 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267467 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039269 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039269 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306736 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306736 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306736 # number of overall misses +system.cpu.dcache.overall_misses::total 1306736 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15939734750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15939734750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 90566913172 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 90566913172 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106506647922 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106506647922 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106506647922 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106506647922 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20883372 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20883372 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35510616 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35510616 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35510616 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35510616 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012772 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012772 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071119 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071119 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036783 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036783 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036783 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036783 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58582.685441 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58582.685441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86560.535625 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 86560.535625 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80843.833387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80843.833387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5220473 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 159 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112927 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35496749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35496749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35496749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35496749 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012808 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012808 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071118 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071118 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036813 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036813 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036813 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036813 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59595.145382 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59595.145382 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87144.823113 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 87144.823113 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81505.864935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81505.864935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81505.864935 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5253118 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 160 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112229 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.228741 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 159 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.807135 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 160 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168941 # number of writebacks -system.cpu.dcache.writebacks::total 168941 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204728 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204728 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895877 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895877 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100605 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100605 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100605 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100605 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62163 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62163 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143411 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143411 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205574 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205574 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205574 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205574 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2517427002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2517427002 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14256184493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14256184493 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16773611495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16773611495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16773611495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16773611495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40497.192896 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40497.192896 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99407.887073 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99407.887073 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks +system.cpu.dcache.writebacks::total 168929 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205307 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205307 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895863 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895863 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101170 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101170 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101170 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101170 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62160 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62160 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143406 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2516687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2516687000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14340164994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14340164994 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16856851994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16856851994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16856851994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16856851994 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002977 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002977 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.242600 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.242600 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99996.966612 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99996.966612 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82002.140403 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82002.140403 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 9b4737e22..060f66d07 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -105,15 +105,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 267269454 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 74391 # number of replacements -system.cpu.icache.tagsinuse 1871.686406 # Cycle average of tags in use -system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 74391 # number of replacements +system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -183,19 +183,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 131235 # number of replacements -system.cpu.l2cache.tagsinuse 30728.810101 # Cycle average of tags in use -system.cpu.l2cache.total_refs 142024 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 163291 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.869760 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.937769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 131235 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits @@ -321,15 +321,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 200248 # number of replacements -system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 419a13ff5..8607c685b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026649 # Number of seconds simulated -sim_ticks 26649062500 # Number of ticks simulated -final_tick 26649062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026765 # Number of seconds simulated +sim_ticks 26765004500 # Number of ticks simulated +final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95593 # Simulator instruction rate (inst/s) -host_op_rate 135659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35926621 # Simulator tick rate (ticks/s) -host_mem_usage 255136 # Number of bytes of host memory used -host_seconds 741.76 # Real time elapsed on the host +host_inst_rate 88779 # Simulator instruction rate (inst/s) +host_op_rate 125988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33510752 # Simulator tick rate (ticks/s) +host_mem_usage 255124 # Number of bytes of host memory used +host_seconds 798.70 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128762 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11193790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 298039152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 309232942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11193790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11193790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 201613096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 201613096 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 201613096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11193790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 298039152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 510846038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128763 # Total number of read requests seen -system.physmem.writeReqs 83950 # Total number of write requests seen -system.physmem.cpureqs 213025 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8240768 # Total number of bytes read from memory -system.physmem.bytesWritten 5372800 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8240768 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 8141 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8250 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8300 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8090 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 7962 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8062 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7789 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 7813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 7880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 8005 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5180 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5268 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7944704 # Number of bytes read from this memory +system.physmem.bytes_read::total 8242496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372160 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372160 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4653 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124136 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128789 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83940 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83940 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11126170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 296831783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 307957953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11126170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11126170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 200715827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 200715827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 200715827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128790 # Total number of read requests seen +system.physmem.writeReqs 83940 # Total number of write requests seen +system.physmem.cpureqs 213051 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8242496 # Total number of bytes read from memory +system.physmem.bytesWritten 5372160 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8298 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8089 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7815 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7888 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7978 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8014 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5181 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5378 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5264 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5206 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5031 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5030 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5091 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5145 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5343 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5342 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26649044000 # Total gap between requests +system.physmem.totGap 26764988000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128763 # Categorize read packet sizes +system.physmem.readPktSize::6 128790 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83950 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 75538 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1500 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83940 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 76190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50560 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,11 +124,11 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -137,201 +137,201 @@ system.physmem.wrQLenPdf::9 3650 # Wh system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 390.104497 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.978164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 858.430673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 13421 38.47% 38.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5383 15.43% 53.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3065 8.78% 62.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2226 6.38% 69.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1625 4.66% 73.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1388 3.98% 77.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1071 3.07% 80.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 870 2.49% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 590 1.69% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 488 1.40% 86.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 448 1.28% 87.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 588 1.69% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 296 0.85% 90.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 306 0.88% 91.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 186 0.53% 91.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 205 0.59% 92.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 126 0.36% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 210 0.60% 93.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 103 0.30% 93.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 233 0.67% 94.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 114 0.33% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 336 0.96% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 140 0.40% 95.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 305 0.87% 96.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 63 0.18% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 139 0.40% 97.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 46 0.13% 97.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 83 0.24% 97.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 24 0.07% 97.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 56 0.16% 97.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 58 0.17% 98.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 11 0.03% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 27 0.08% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 19 0.05% 98.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 23 0.07% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 10 0.03% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 17 0.05% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 8 0.02% 98.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 14 0.04% 98.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 16 0.05% 98.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 16 0.05% 98.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.03% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 15 0.04% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 7 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 7 0.02% 98.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 12 0.03% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 11 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 7 0.02% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 3 0.01% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 9 0.03% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 3 0.01% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 7 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 389.285277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.799947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 855.459025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 13425 38.40% 38.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5427 15.52% 53.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3113 8.90% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2218 6.34% 69.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1684 4.82% 73.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1324 3.79% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1016 2.91% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 832 2.38% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 675 1.93% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 524 1.50% 86.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 431 1.23% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 550 1.57% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 311 0.89% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 325 0.93% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 173 0.49% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 178 0.51% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 117 0.33% 92.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 209 0.60% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 130 0.37% 93.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 238 0.68% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 111 0.32% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 314 0.90% 95.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 120 0.34% 95.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 318 0.91% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 69 0.20% 96.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 140 0.40% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 41 0.12% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 97 0.28% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 29 0.08% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 65 0.19% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 25 0.07% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 42 0.12% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 12 0.03% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 31 0.09% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.05% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 26 0.07% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 33 0.09% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 11 0.03% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 15 0.04% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 11 0.03% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 15 0.04% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 8 0.02% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 11 0.03% 98.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 15 0.04% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 9 0.03% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 11 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 6 0.02% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 5 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 3 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 7 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 3 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 4 0.01% 98.83% # Bytes accessed per row activation system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 2 0.01% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 7 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 2 0.01% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 5 0.01% 98.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 2 0.01% 98.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 4 0.01% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 1 0.00% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 3 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 4 0.01% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 3 0.01% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 3 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 4 0.01% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 4 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 6 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 3 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 9 0.03% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 3 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 3 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 4 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 4 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 4 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.00% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 5 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 2 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 3 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 2 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 2 0.01% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 2 0.01% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.01% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 3 0.01% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 3 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 3 0.01% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 3 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 2 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 6 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 2 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 4 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 238 0.68% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34891 # Bytes accessed per row activation -system.physmem.totQLat 2799338750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4801886250 # Sum of mem lat for all requests -system.physmem.totBusLat 643800000 # Total cycles spent in databus access -system.physmem.totBankLat 1358747500 # Total cycles spent in bank access -system.physmem.avgQLat 21740.58 # Average queueing delay per request -system.physmem.avgBankLat 10552.48 # Average bank access latency per request -system.physmem.avgBusLat 4999.96 # Average bus latency per request -system.physmem.avgMemAccLat 37293.02 # Average memory access latency -system.physmem.avgRdBW 309.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 201.61 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 309.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 201.61 # Average consumed write bandwidth in MB/s +system.physmem.bytesPerActivate::8128-8129 2 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 239 0.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34959 # Bytes accessed per row activation +system.physmem.totQLat 2852295000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4861110000 # Sum of mem lat for all requests +system.physmem.totBusLat 643935000 # Total cycles spent in databus access +system.physmem.totBankLat 1364880000 # Total cycles spent in bank access +system.physmem.avgQLat 22147.38 # Average queueing delay per request +system.physmem.avgBankLat 10597.96 # Average bank access latency per request +system.physmem.avgBusLat 5000.00 # Average bus latency per request +system.physmem.avgMemAccLat 37745.35 # Average memory access latency +system.physmem.avgRdBW 307.96 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 200.72 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 307.96 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 200.72 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.99 # Data bus utilization in percentage +system.physmem.busUtil 3.97 # Data bus utilization in percentage system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 10.01 # Average write queue length over time -system.physmem.readRowHits 120254 # Number of row buffer hits during reads -system.physmem.writeRowHits 57565 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.57 # Row buffer hit rate for writes -system.physmem.avgGap 125281.69 # Average gap between requests -system.membus.throughput 510846038 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26509 # Transaction distribution -system.membus.trans_dist::ReadResp 26508 # Transaction distribution -system.membus.trans_dist::Writeback 83950 # Transaction distribution -system.membus.trans_dist::UpgradeReq 312 # Transaction distribution -system.membus.trans_dist::UpgradeResp 312 # Transaction distribution -system.membus.trans_dist::ReadExReq 102254 # Transaction distribution -system.membus.trans_dist::ReadExResp 102254 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 342099 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 342099 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13613568 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 13613568 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13613568 # Total data (bytes) +system.physmem.avgWrQLen 10.24 # Average write queue length over time +system.physmem.readRowHits 120249 # Number of row buffer hits during reads +system.physmem.writeRowHits 57506 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.51 # Row buffer hit rate for writes +system.physmem.avgGap 125816.71 # Average gap between requests +system.membus.throughput 508673780 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26538 # Transaction distribution +system.membus.trans_dist::ReadResp 26537 # Transaction distribution +system.membus.trans_dist::Writeback 83940 # Transaction distribution +system.membus.trans_dist::UpgradeReq 321 # Transaction distribution +system.membus.trans_dist::UpgradeResp 321 # Transaction distribution +system.membus.trans_dist::ReadExReq 102252 # Transaction distribution +system.membus.trans_dist::ReadExResp 102252 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 342161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 342161 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13614656 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13614656 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13614656 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 926784500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1200135938 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1207011429 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) -system.cpu.branchPred.lookups 16620839 # Number of BP lookups -system.cpu.branchPred.condPredicted 12757336 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602395 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10635009 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7765773 # Number of BTB hits +system.cpu.branchPred.lookups 16635237 # Number of BP lookups +system.cpu.branchPred.condPredicted 12768503 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 604840 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10652885 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7773045 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.020841 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1824331 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113161 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.966572 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823659 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113448 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -375,99 +375,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53298126 # number of cpu cycles simulated +system.cpu.numCycles 53530010 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12535190 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85154971 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16620839 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9590104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21184086 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2355794 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10829442 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 551 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11674707 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 181091 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46276167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.576733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.331391 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12549473 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85279503 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16635237 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9596704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21206249 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2379470 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10773225 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 477 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11686664 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178212 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46277294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.580240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332526 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25111993 54.27% 54.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2139332 4.62% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1963886 4.24% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2043329 4.42% 67.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1467358 3.17% 70.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1375070 2.97% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 956833 2.07% 75.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1188482 2.57% 78.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10029884 21.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25091643 54.22% 54.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2136768 4.62% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1963962 4.24% 63.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2042989 4.41% 67.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1466847 3.17% 70.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1383026 2.99% 73.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 957932 2.07% 75.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1190240 2.57% 78.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10043887 21.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46276167 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.311847 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.597710 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14619512 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9177970 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19466340 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1388431 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1623914 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3328977 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104776 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116789336 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 361687 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1623914 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16330804 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2680643 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1000847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19093672 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5546287 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114905556 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 219 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17136 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4693151 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1312 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115218637 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529387920 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529379803 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8117 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46277294 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.310765 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.593116 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14640784 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9115289 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19504792 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1371825 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1644604 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3334519 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105037 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116943845 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 363315 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1644604 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16350397 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2675070 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1001661 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19117578 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5487984 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 115077475 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 183 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17134 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4627273 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 285 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115384718 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 530174580 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 530166885 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7695 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16085965 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20302 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20297 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13065620 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29609265 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22417131 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3885027 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4397806 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111472584 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35916 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107208843 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 271699 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10738438 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25737967 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2130 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46276167 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.316718 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.989507 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16252046 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20256 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20253 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13031784 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29643166 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22451729 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3891559 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4392801 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111618845 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35897 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107291250 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 275974 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10887740 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 26073816 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2111 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46277294 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.318443 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990403 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11020528 23.81% 23.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8094858 17.49% 41.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7429249 16.05% 57.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7154901 15.46% 72.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5386733 11.64% 84.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3906460 8.44% 92.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1842144 3.98% 96.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 871664 1.88% 98.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 569630 1.23% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11003161 23.78% 23.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8115395 17.54% 41.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7436608 16.07% 57.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7096880 15.34% 72.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5407297 11.68% 84.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3935038 8.50% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1843993 3.98% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 867713 1.88% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571209 1.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46276167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46277294 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112593 4.57% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113414 4.57% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available @@ -496,118 +496,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1348878 54.73% 59.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1003122 40.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1362149 54.91% 59.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1005332 40.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56608598 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91438 0.09% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28894537 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21614012 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56660345 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91595 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 269 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28911335 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21627699 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107208843 # Type of FU issued -system.cpu.iq.rate 2.011494 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464595 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022989 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263429476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122274650 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105524045 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 671 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1168 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 196 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109673111 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2189921 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107291250 # Type of FU issued +system.cpu.iq.rate 2.004320 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2480897 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023123 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263615967 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122570490 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105600159 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 698 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1174 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 216 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109771796 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 351 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2179165 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2302157 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6684 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29801 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1861393 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2336058 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6530 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30281 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1895991 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 27 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 724 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 805 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1623914 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1145014 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 48197 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111518283 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 295309 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29609265 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22417131 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19996 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6449 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5406 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29801 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 392238 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181031 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573269 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106181942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28595303 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1026901 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1644604 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1147402 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 47438 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111664541 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 286964 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29643166 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22451729 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19977 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6774 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4975 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30281 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393124 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181749 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 574873 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106260947 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28610039 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1030303 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9783 # number of nop insts executed -system.cpu.iew.exec_refs 49924361 # number of memory reference insts executed -system.cpu.iew.exec_branches 14597950 # Number of branches executed -system.cpu.iew.exec_stores 21329058 # Number of stores executed -system.cpu.iew.exec_rate 1.992227 # Inst execution rate -system.cpu.iew.wb_sent 105744224 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105524241 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53247487 # num instructions producing a value -system.cpu.iew.wb_consumers 103444790 # num instructions consuming a value +system.cpu.iew.exec_nop 9799 # number of nop insts executed +system.cpu.iew.exec_refs 49952901 # number of memory reference insts executed +system.cpu.iew.exec_branches 14605114 # Number of branches executed +system.cpu.iew.exec_stores 21342862 # Number of stores executed +system.cpu.iew.exec_rate 1.985072 # Inst execution rate +system.cpu.iew.wb_sent 105821179 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105600375 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53334269 # num instructions producing a value +system.cpu.iew.wb_consumers 103952809 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.979887 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514743 # average fanout of values written-back +system.cpu.iew.wb_rate 1.972732 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.513062 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10886753 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11033009 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499558 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44652253 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.253692 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.763005 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 501673 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44632690 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.254680 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.761954 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15559873 34.85% 34.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11688259 26.18% 61.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3454288 7.74% 68.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2872185 6.43% 75.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1868727 4.19% 79.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1932277 4.33% 83.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 683931 1.53% 85.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 562545 1.26% 86.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6030168 13.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15532654 34.80% 34.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11684135 26.18% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3462025 7.76% 68.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2877014 6.45% 75.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1854993 4.16% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1951437 4.37% 83.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 690877 1.55% 85.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565658 1.27% 86.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6013897 13.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44652253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44632690 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -618,226 +618,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6030168 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6013897 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150115967 # The number of ROB reads -system.cpu.rob.rob_writes 224671489 # The number of ROB writes -system.cpu.timesIdled 79206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7021959 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150258931 # The number of ROB reads +system.cpu.rob.rob_writes 224984633 # The number of ROB writes +system.cpu.timesIdled 80350 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7252716 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.751656 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.751656 # CPI: Total CPI of All Threads -system.cpu.ipc 1.330396 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.330396 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511415343 # number of integer regfile reads -system.cpu.int_regfile_writes 103300902 # number of integer regfile writes -system.cpu.fp_regfile_reads 1012 # number of floating regfile reads -system.cpu.fp_regfile_writes 876 # number of floating regfile writes -system.cpu.misc_regfile_reads 49160884 # number of misc regfile reads +system.cpu.cpi 0.754926 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.754926 # CPI: Total CPI of All Threads +system.cpu.ipc 1.324633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.324633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511766096 # number of integer regfile reads +system.cpu.int_regfile_writes 103375635 # number of integer regfile writes +system.cpu.fp_regfile_reads 1160 # number of floating regfile reads +system.cpu.fp_regfile_writes 1012 # number of floating regfile writes +system.cpu.misc_regfile_reads 49188390 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 776266857 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 87116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 87115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129077 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 62962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454559 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 517521 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1998208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18655488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 20653696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20653696 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33088 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 290859995 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 771895107 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 86668 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 86666 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 61963 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454719 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 516682 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1966784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18660992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 20627776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 47617981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 47827231 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 243817935 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.replacements 29381 # number of replacements -system.cpu.icache.tagsinuse 1810.408207 # Cycle average of tags in use -system.cpu.icache.total_refs 11639182 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 31418 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 370.462219 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1810.408207 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.883988 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.883988 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11639193 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11639193 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11639193 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11639193 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11639193 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 845054999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11674706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11674706 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11674706 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11674706 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11674706 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11674706 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003042 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003042 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003042 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003042 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003042 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23795.652268 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23795.652268 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23795.652268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23795.652268 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1082 # number of cycles access was blocked +system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.cpu.icache.tags.replacements 28871 # number of replacements +system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11651673 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11651673 # number of overall hits +system.cpu.icache.overall_hits::total 11651673 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34991 # number of overall misses +system.cpu.icache.overall_misses::total 34991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 840169228 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 840169228 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 840169228 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 840169228 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 840169228 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 840169228 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11686664 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11686664 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11686664 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11686664 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11686664 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11686664 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002994 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002994 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002994 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002994 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002994 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002994 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24011.009345 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24011.009345 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24011.009345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24011.009345 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24011.009345 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1080 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 40.074074 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.956522 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31740 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31740 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31740 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31740 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31740 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31740 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 686303518 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 686303518 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 686303518 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 686303518 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 686303518 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 686303518 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002719 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002719 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002719 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21622.669124 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21622.669124 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21622.669124 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21622.669124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3759 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3759 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3759 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3759 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3759 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3759 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31232 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31232 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31232 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31232 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31232 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31232 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 684118269 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 684118269 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 684118269 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 684118269 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 684118269 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1828.016782 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.815484 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.041906 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.055787 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.913177 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26545 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33468 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 60013 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129077 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129077 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 14 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 14 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4785 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8687985251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9019745751 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 331760500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8687985251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9019745751 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.307980 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.952381 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.952381 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955341 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764072 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.666617 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.151406 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764072 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.666617 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71300.343864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72658.704592 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72420.538473 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68911.961879 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68911.961879 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69414.584423 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69414.584423 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158319 # number of replacements -system.cpu.dcache.tagsinuse 4069.477080 # Cycle average of tags in use -system.cpu.dcache.total_refs 44347755 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162415 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.052089 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 350225000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4069.477080 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.993525 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.993525 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26048553 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26048553 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266688 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266688 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15980 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15980 # number of LoadLockedReq hits +system.cpu.dcache.tags.replacements 158372 # number of replacements +system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266800 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15987 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15987 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44315241 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44315241 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44315241 # number of overall hits -system.cpu.dcache.overall_hits::total 44315241 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125407 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125407 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583213 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583213 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708620 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708620 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708620 # number of overall misses -system.cpu.dcache.overall_misses::total 1708620 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5134620500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5134620500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 123147327479 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 123147327479 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 951500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 951500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 128281947979 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 128281947979 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 128281947979 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 128281947979 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26173960 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173960 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44341813 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44341813 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44341813 # number of overall hits +system.cpu.dcache.overall_hits::total 44341813 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125377 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125377 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583101 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583101 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708478 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708478 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708478 # number of overall misses +system.cpu.dcache.overall_misses::total 1708478 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5199394222 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5199394222 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 124981048011 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 124981048011 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 861250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 861250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 130180442233 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 130180442233 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 130180442233 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 130180442233 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26200390 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26200390 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16024 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16029 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46023861 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46023861 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46023861 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46023861 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004791 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004791 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002746 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002746 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037125 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037125 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40943.651471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40943.651471 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77783.170981 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77783.170981 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21625 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21625 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75079.273319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75079.273319 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5184 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1288 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46050291 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46050291 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46050291 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46050291 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004785 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004785 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079754 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079754 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002620 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002620 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037100 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037100 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037100 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037100 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41470.080015 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41470.080015 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78946.983175 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78946.983175 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20505.952381 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20505.952381 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76196.733135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76196.733135 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76196.733135 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9105 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1249 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 129 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.751724 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 80.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.581395 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 78.062500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129077 # number of writebacks -system.cpu.dcache.writebacks::total 129077 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69998 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69998 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475881 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475881 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545879 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545879 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545879 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545879 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55409 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55409 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162741 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162741 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162741 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162741 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243387065 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243387065 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8465944990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8465944990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10709332055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10709332055 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10709332055 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10709332055 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129110 # number of writebacks +system.cpu.dcache.writebacks::total 129110 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69907 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69907 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475766 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475766 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1545673 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1545673 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1545673 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1545673 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55470 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55470 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107335 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162805 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162805 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162805 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162805 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2262652309 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2262652309 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8543267922 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8543267922 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10805920231 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10805920231 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10805920231 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10805920231 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.773918 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.773918 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78876.243711 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78876.243711 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40790.559023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40790.559023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79594.427931 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79594.427931 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66373.392899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66373.392899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 9c1dc992d..170d172b3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -115,15 +115,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 265378090 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 16890 # number of replacements -system.cpu.icache.tagsinuse 1736.497265 # Cycle average of tags in use -system.cpu.icache.total_refs 78126161 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4131.910355 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 16890 # number of replacements +system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -193,19 +193,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 94693 # number of replacements -system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use -system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 125788 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.590637 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 94693 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits @@ -331,15 +331,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 155902 # number of replacements -system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use -system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 155902 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 4b553d931..df352064c 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -73,15 +73,15 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 404484520 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.icache.replacements 184976 # number of replacements -system.cpu.icache.tagsinuse 2004.815325 # Cycle average of tags in use -system.cpu.icache.total_refs 134366547 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 184976 # number of replacements +system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -151,19 +151,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 98540 # number of replacements -system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use -system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129534 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 1.751918 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.941490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 98540 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits @@ -289,15 +289,15 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 146582 # number of replacements -system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use -system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 146582 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits |