diff options
Diffstat (limited to 'tests/long/se/50.vortex/ref')
3 files changed, 2074 insertions, 2209 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 391c7c37b..f3edc5948 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.043690 # Number of seconds simulated -sim_ticks 43690025000 # Number of ticks simulated -final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043459 # Number of seconds simulated +sim_ticks 43458818000 # Number of ticks simulated +final_tick 43458818000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133116 # Simulator instruction rate (inst/s) -host_op_rate 133116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65834414 # Simulator tick rate (ticks/s) -host_mem_usage 238716 # Number of bytes of host memory used -host_seconds 663.64 # Real time elapsed on the host +host_inst_rate 114678 # Simulator instruction rate (inst/s) +host_op_rate 114678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56415550 # Simulator tick rate (ticks/s) +host_mem_usage 273516 # Number of bytes of host memory used +host_seconds 770.33 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,27 +25,27 @@ system.physmem.num_reads::cpu.data 158412 # Nu system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10404938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 232052236 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 242457174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10404938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10404938 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 166990245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 166990245 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 166990245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10404938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 232052236 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 409447420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 10460294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 233286787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 243747080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10460294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10460294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 167878657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 167878657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 167878657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10460294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 233286787 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 411625737 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 165515 # Number of read requests accepted system.physmem.writeReqs 113997 # Number of write requests accepted system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10592832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadDRAM 10592576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294400 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10379 # Per bank write bursts @@ -58,10 +58,10 @@ system.physmem.perBankRdBursts::6 9796 # Pe system.physmem.perBankRdBursts::7 10273 # Per bank write bursts system.physmem.perBankRdBursts::8 10509 # Per bank write bursts system.physmem.perBankRdBursts::9 10590 # Per bank write bursts -system.physmem.perBankRdBursts::10 10479 # Per bank write bursts +system.physmem.perBankRdBursts::10 10477 # Per bank write bursts system.physmem.perBankRdBursts::11 10188 # Per bank write bursts -system.physmem.perBankRdBursts::12 10237 # Per bank write bursts -system.physmem.perBankRdBursts::13 10581 # Per bank write bursts +system.physmem.perBankRdBursts::12 10236 # Per bank write bursts +system.physmem.perBankRdBursts::13 10580 # Per bank write bursts system.physmem.perBankRdBursts::14 10468 # Per bank write bursts system.physmem.perBankRdBursts::15 10593 # Per bank write bursts system.physmem.perBankWrBursts::0 7081 # Per bank write bursts @@ -69,20 +69,20 @@ system.physmem.perBankWrBursts::1 7259 # Pe system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7125 # Per bank write bursts -system.physmem.perBankWrBursts::5 7173 # Per bank write bursts +system.physmem.perBankWrBursts::5 7170 # Per bank write bursts system.physmem.perBankWrBursts::6 6769 # Per bank write bursts -system.physmem.perBankWrBursts::7 7091 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::7 7092 # Per bank write bursts +system.physmem.perBankWrBursts::8 7216 # Per bank write bursts system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts system.physmem.perBankWrBursts::13 7284 # Per bank write bursts -system.physmem.perBankWrBursts::14 7282 # Per bank write bursts +system.physmem.perBankWrBursts::14 7281 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 43690004000 # Total gap between requests +system.physmem.totGap 43458797000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,10 +97,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 113997 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 69517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10165 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -129,195 +129,147 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 51391 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.059076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.605304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 670.587406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 21918 42.65% 42.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7689 14.96% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4202 8.18% 65.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3191 6.21% 72.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2222 4.32% 76.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1690 3.29% 79.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1284 2.50% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1159 2.26% 84.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 851 1.66% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 652 1.27% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 530 1.03% 88.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 483 0.94% 89.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 404 0.79% 90.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 335 0.65% 90.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 260 0.51% 91.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 388 0.75% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 222 0.43% 92.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 237 0.46% 92.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 182 0.35% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 255 0.50% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 215 0.42% 94.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 327 0.64% 94.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 148 0.29% 95.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 683 1.33% 96.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 243 0.47% 96.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 177 0.34% 97.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 59 0.11% 97.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 192 0.37% 97.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 83 0.16% 97.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 80 0.16% 98.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 48 0.09% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 87 0.17% 98.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 58 0.11% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 48 0.09% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 40 0.08% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 31 0.06% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 31 0.06% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 14 0.03% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 34 0.07% 98.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 26 0.05% 98.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 13 0.03% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 18 0.04% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 16 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 12 0.02% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 26 0.05% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 7 0.01% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 17 0.03% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 6 0.01% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 16 0.03% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 10 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 11 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 13 0.03% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 10 0.02% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 6 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 3 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 7 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 8 0.02% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 20 0.04% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 11 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 15 0.03% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 5 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 13 0.03% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 7 0.01% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 2 0.00% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 6 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 7 0.01% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 7 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 8 0.02% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 5 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 5 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 5 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 4 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 4 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 5 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 6 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 24 0.05% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 73 0.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 51391 # Bytes accessed per row activation -system.physmem.totQLat 6031819750 # Total ticks spent queuing -system.physmem.totMemAccLat 8481513500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 827565000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1622128750 # Total ticks spent accessing banks -system.physmem.avgQLat 36443.18 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9800.61 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 41807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 385.014950 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 230.118388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.708548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12628 30.21% 30.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8632 20.65% 50.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4415 10.56% 61.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2749 6.58% 67.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2263 5.41% 73.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1680 4.02% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1442 3.45% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1629 3.90% 84.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6369 15.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41807 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.954842 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 351.043824 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6907 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.496599 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.404036 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.150839 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6289 91.03% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.19% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 61 0.88% 92.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 166 2.40% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 127 1.84% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 73 1.06% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 63 0.91% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 29 0.42% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 18 0.26% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 12 0.17% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.10% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.04% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.01% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.04% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 3 0.04% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 19 0.28% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 5 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6909 # Writes before turning the bus around for reads +system.physmem.totQLat 5306478250 # Total ticks spent queuing +system.physmem.totMemAccLat 7800537000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827545000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1666513750 # Total ticks spent accessing banks +system.physmem.avgQLat 32061.57 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10069.02 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51243.79 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 242.45 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 166.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 242.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 166.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47130.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 243.74 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 167.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 243.75 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 167.88 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.20 # Data bus utilization in percentage -system.physmem.busUtilRead 1.89 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.30 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing -system.physmem.readRowHits 151507 # Number of row buffer hits during reads -system.physmem.writeRowHits 76598 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.19 # Row buffer hit rate for writes -system.physmem.avgGap 156308.15 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 10.59 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 409447420 # Throughput (bytes/s) +system.physmem.busUtil 3.22 # Data bus utilization in percentage +system.physmem.busUtilRead 1.90 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.31 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing +system.physmem.readRowHits 144461 # Number of row buffer hits during reads +system.physmem.writeRowHits 82889 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.71 # Row buffer hit rate for writes +system.physmem.avgGap 155480.97 # Average gap between requests +system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 10.25 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 411625737 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 34625 # Transaction distribution system.membus.trans_dist::ReadResp 34625 # Transaction distribution system.membus.trans_dist::Writeback 113997 # Transaction distribution @@ -329,40 +281,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 17888768 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1218631000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1219845000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1520840750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 18742723 # Number of BP lookups -system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted +system.cpu.branchPred.lookups 18742760 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318400 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15507309 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4664026 # Number of BTB hits +system.cpu.branchPred.BTBLookups 15507492 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4664025 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076308 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.075947 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277713 # DTB read hits +system.cpu.dtb.read_hits 20277780 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367861 # DTB read accesses -system.cpu.dtb.write_hits 14728970 # DTB write hits +system.cpu.dtb.read_accesses 20367928 # DTB read accesses +system.cpu.dtb.write_hits 14729056 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736222 # DTB write accesses -system.cpu.dtb.data_hits 35006683 # DTB hits +system.cpu.dtb.write_accesses 14736308 # DTB write accesses +system.cpu.dtb.data_hits 35006836 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35104083 # DTB accesses -system.cpu.itb.fetch_hits 12367758 # ITB hits +system.cpu.dtb.data_accesses 35104236 # DTB accesses +system.cpu.itb.fetch_hits 12367757 # ITB hits system.cpu.itb.fetch_misses 11021 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12378779 # ITB accesses +system.cpu.itb.fetch_accesses 12378778 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -376,18 +328,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 87380051 # number of cpu cycles simulated +system.cpu.numCycles 86917637 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8074237 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668486 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74161830 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8074236 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668524 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74162131 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126481080 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 126481381 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14174544 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 14174243 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 35060070 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken). @@ -398,12 +350,12 @@ system.cpu.execution_unit.executions 44777932 # Nu system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77196544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77191042 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 232942 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17804423 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69575628 # Number of cycles cpu stages are processed. -system.cpu.activity 79.624156 # Percentage of cycles cpu is active +system.cpu.timesIdled 229429 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17341864 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69575773 # Number of cycles cpu stages are processed. +system.cpu.activity 80.047934 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -415,62 +367,62 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.989126 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.983891 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.989126 # CPI: Total CPI of All Threads -system.cpu.ipc 1.010994 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.983891 # CPI: Total CPI of All Threads +system.cpu.ipc 1.016372 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.010994 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34724442 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52655609 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.260447 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 44924893 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42455158 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 48.586786 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 44349560 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43030491 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.245212 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65259184 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120867 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.315695 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 41338146 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46041905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 52.691552 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.016372 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34262012 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52655625 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.581059 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 44462439 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42455198 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.845320 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 43887105 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43030532 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.507250 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 64797015 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120622 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.450096 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 40875399 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46042238 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 52.972262 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 84371 # number of replacements -system.cpu.icache.tags.tagsinuse 1906.431852 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 12250505 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1905.831723 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 12250503 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 141.760360 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 141.760337 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1905.831723 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.930582 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.930582 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 24821911 # Number of tag accesses system.cpu.icache.tags.data_accesses 24821911 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12250505 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12250505 # number of overall hits -system.cpu.icache.overall_hits::total 12250505 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 117242 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 117242 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 117242 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 117242 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 117242 # number of overall misses -system.cpu.icache.overall_misses::total 117242 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2020332731 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2020332731 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2020332731 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2020332731 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2020332731 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2020332731 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 12250503 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250503 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250503 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250503 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250503 # number of overall hits +system.cpu.icache.overall_hits::total 12250503 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117244 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 117244 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 117244 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 117244 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 117244 # number of overall misses +system.cpu.icache.overall_misses::total 117244 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1999895234 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1999895234 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1999895234 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1999895234 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1999895234 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1999895234 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 12367747 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 12367747 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 12367747 # number of demand (read+write) accesses @@ -483,106 +435,106 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.009480 system.cpu.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.009480 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17232.158535 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17232.158535 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17232.158535 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17232.158535 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17232.158535 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 376 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17057.548651 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17057.548651 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17057.548651 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17057.548651 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17057.548651 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 343 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.117647 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.866667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30825 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30825 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30825 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30825 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30825 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30825 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30827 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30827 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30827 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30827 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30827 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30827 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1432321765 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1432321765 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1432321765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1432321765 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1432321765 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1432321765 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1419611513 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1419611513 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1419611513 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1419611513 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1419611513 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1419611513 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16574.537012 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16574.537012 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16574.537012 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16574.537012 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16427.456554 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16427.456554 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16427.456554 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16427.456554 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 672540151 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 146994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 146994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168351 # Transaction distribution +system.cpu.toL2Bus.throughput 676121104 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577043 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 749877 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29383296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29383296 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 397908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 130875735 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 130829487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 325637219 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 323146469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.l2cache.tags.replacements 131591 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30890.802594 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 151432 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30877.243576 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.925335 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27098.006137 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.747165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1785.049292 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27092.654478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.905024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1776.684074 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.826802 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061276 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.054220 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.942299 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1155 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17071 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17173 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13478 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3980332 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3980332 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 3980348 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3980348 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 112369 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168351 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168351 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168352 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168352 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45934 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125248 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 45935 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 125249 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45934 # number of overall hits -system.cpu.l2cache.overall_hits::total 125248 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 45935 # number of overall hits +system.cpu.l2cache.overall_hits::total 125249 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 34625 # number of ReadReq misses @@ -594,52 +546,52 @@ system.cpu.l2cache.demand_misses::total 165515 # nu system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses system.cpu.l2cache.overall_misses::total 165515 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 550125750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2043322000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2593447750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13452980250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13452980250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 550125750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15496302250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16046428000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 550125750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15496302250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16046428000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 537407000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1972226500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2509633500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12899781250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12899781250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 537407000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14872007750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15409414750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 537407000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14872007750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15409414750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 60577 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 146994 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168351 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168351 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204346 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 290763 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204346 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 290763 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454331 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.235554 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775215 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569244 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775215 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569244 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77449.774743 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74243.223603 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74901.018051 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102780.810222 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102780.810222 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 96948.482011 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77449.774743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 97822.780156 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 96948.482011 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75659.158102 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71659.999273 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72480.389892 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98554.368172 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98554.368172 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 93099.808174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75659.158102 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93881.825556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 93099.808174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,80 +613,80 @@ system.cpu.l2cache.demand_mshr_misses::total 165515 system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 460945750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695556500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2156502250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11851363750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11851363750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 460945750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13546920250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14007866000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 460945750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13546920250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14007866000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 448296500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1624855000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2073151500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11301062250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11301062250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448296500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12925917250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13374213750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448296500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12925917250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13374213750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454331 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235554 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569244 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775215 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569244 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64894.516402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61607.314149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62281.653430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90544.455268 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90544.455268 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64894.516402 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85517.007866 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84632.003142 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63113.684359 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59038.405639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59874.411552 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86340.150126 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86340.150126 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63113.684359 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81596.831364 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80803.635622 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200250 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.382661 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33754883 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204346 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.184946 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 297515000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 200251 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.081511 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33755026 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.184838 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 302612000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.081511 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995137 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995137 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 922 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3118 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984376 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984376 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574591 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 33754883 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754883 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754883 # number of overall hits -system.cpu.dcache.overall_hits::total 33754883 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96346 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96346 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038786 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038786 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135132 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135132 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135132 # number of overall misses -system.cpu.dcache.overall_misses::total 1135132 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5098666234 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5098666234 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85921765380 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85921765380 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 91020431614 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 91020431614 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 91020431614 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 91020431614 # number of overall miss cycles +system.cpu.dcache.tags.tag_accesses 69984377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984377 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20180293 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180293 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574733 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574733 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33755026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33755026 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33755026 # number of overall hits +system.cpu.dcache.overall_hits::total 33755026 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96345 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96345 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038644 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038644 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1134989 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1134989 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1134989 # number of overall misses +system.cpu.dcache.overall_misses::total 1134989 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4945314984 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4945314984 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 82211352380 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 82211352380 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 87156667364 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 87156667364 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 87156667364 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 87156667364 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -745,54 +697,54 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52920.372761 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52920.372761 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82713.634358 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82713.634358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80184.887409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80184.887409 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80184.887409 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5745787 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071075 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032530 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032530 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032530 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032530 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51329.233318 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51329.233318 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79152.580076 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79152.580076 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76790.759526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76790.759526 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76790.759526 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5467849 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116872 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.220352 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.784936 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks -system.cpu.dcache.writebacks::total 168351 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35580 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35580 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895206 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895206 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930786 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930786 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930786 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930786 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks +system.cpu.dcache.writebacks::total 168352 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35578 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35578 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895064 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895064 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930642 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930642 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930642 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930642 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2437943016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2437943016 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13723508765 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13723508765 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16161451781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16161451781 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16161451781 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16161451781 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2366861266 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2366861266 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13170287765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13170287765 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15537149031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15537149031 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15537149031 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15537149031 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -801,14 +753,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40120.182602 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40120.182602 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95580.921890 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95580.921890 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79088.662274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79088.662274 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38949.779749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38949.779749 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91727.871326 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91727.871326 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76033.164328 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76033.164328 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 629fb2f13..7573bf6de 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024877 # Number of seconds simulated -sim_ticks 24876941500 # Number of ticks simulated -final_tick 24876941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024671 # Number of seconds simulated +sim_ticks 24670906500 # Number of ticks simulated +final_tick 24670906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 202143 # Simulator instruction rate (inst/s) -host_op_rate 202143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63181048 # Simulator tick rate (ticks/s) -host_mem_usage 239772 # Number of bytes of host memory used -host_seconds 393.74 # Real time elapsed on the host +host_inst_rate 168282 # Simulator instruction rate (inst/s) +host_op_rate 168282 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52161952 # Simulator tick rate (ticks/s) +host_mem_usage 276592 # Number of bytes of host memory used +host_seconds 472.97 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 490624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory -system.physmem.bytes_read::total 10645376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490624 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7297216 # Number of bytes written to this memory -system.physmem.bytes_written::total 7297216 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7666 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158668 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166334 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114019 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114019 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19722039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 408199376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 427921415 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19722039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19722039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 293332522 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 293332522 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 293332522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19722039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 408199376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 721253937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166334 # Number of read requests accepted -system.physmem.writeReqs 114019 # Number of write requests accepted -system.physmem.readBursts 166334 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114019 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10645312 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10645376 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7297216 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 489344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153856 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7297088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7297088 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158654 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166300 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114017 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114017 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19834861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 411572068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 431406929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19834861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19834861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 295777052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 295777052 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 295777052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19834861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 411572068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 727183981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166300 # Number of read requests accepted +system.physmem.writeReqs 114017 # Number of write requests accepted +system.physmem.readBursts 166300 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114017 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10642752 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 7295296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10643200 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7297088 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10436 # Per bank write bursts -system.physmem.perBankRdBursts::1 10466 # Per bank write bursts -system.physmem.perBankRdBursts::2 10310 # Per bank write bursts -system.physmem.perBankRdBursts::3 10058 # Per bank write bursts -system.physmem.perBankRdBursts::4 10431 # Per bank write bursts -system.physmem.perBankRdBursts::5 10410 # Per bank write bursts -system.physmem.perBankRdBursts::6 9846 # Per bank write bursts -system.physmem.perBankRdBursts::7 10323 # Per bank write bursts -system.physmem.perBankRdBursts::8 10612 # Per bank write bursts -system.physmem.perBankRdBursts::9 10641 # Per bank write bursts -system.physmem.perBankRdBursts::10 10552 # Per bank write bursts -system.physmem.perBankRdBursts::11 10231 # Per bank write bursts -system.physmem.perBankRdBursts::12 10282 # Per bank write bursts +system.physmem.perBankRdBursts::0 10427 # Per bank write bursts +system.physmem.perBankRdBursts::1 10465 # Per bank write bursts +system.physmem.perBankRdBursts::2 10308 # Per bank write bursts +system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::4 10424 # Per bank write bursts +system.physmem.perBankRdBursts::5 10403 # Per bank write bursts +system.physmem.perBankRdBursts::6 9851 # Per bank write bursts +system.physmem.perBankRdBursts::7 10318 # Per bank write bursts +system.physmem.perBankRdBursts::8 10615 # Per bank write bursts +system.physmem.perBankRdBursts::9 10643 # Per bank write bursts +system.physmem.perBankRdBursts::10 10551 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10273 # Per bank write bursts system.physmem.perBankRdBursts::13 10619 # Per bank write bursts -system.physmem.perBankRdBursts::14 10489 # Per bank write bursts -system.physmem.perBankRdBursts::15 10627 # Per bank write bursts -system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7258 # Per bank write bursts +system.physmem.perBankRdBursts::14 10486 # Per bank write bursts +system.physmem.perBankRdBursts::15 10626 # Per bank write bursts +system.physmem.perBankWrBursts::0 7082 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7177 # Per bank write bursts +system.physmem.perBankWrBursts::5 7170 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7092 # Per bank write bursts -system.physmem.perBankWrBursts::8 7228 # Per bank write bursts +system.physmem.perBankWrBursts::7 7086 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts system.physmem.perBankWrBursts::9 6941 # Per bank write bursts -system.physmem.perBankWrBursts::10 7087 # Per bank write bursts -system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::11 6991 # Per bank write bursts +system.physmem.perBankWrBursts::12 6963 # Per bank write bursts system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7286 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24876907500 # Total gap between requests +system.physmem.totGap 24670873000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166334 # Read request sizes (log2) +system.physmem.readPktSize::6 166300 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114019 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 71615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56813 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 31969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114017 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 69085 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 53344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -129,233 +129,193 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52112 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 344.289837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 164.462354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 671.053187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 22533 43.24% 43.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 7819 15.00% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4221 8.10% 66.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 3179 6.10% 72.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 2215 4.25% 76.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1656 3.18% 79.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1349 2.59% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 1165 2.24% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 821 1.58% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 640 1.23% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 526 1.01% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 503 0.97% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 384 0.74% 90.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 279 0.54% 90.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 312 0.60% 91.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 436 0.84% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 202 0.39% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 182 0.35% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 166 0.32% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 352 0.68% 93.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 220 0.42% 94.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 250 0.48% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 131 0.25% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 818 1.57% 96.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 224 0.43% 97.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 79 0.15% 97.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 35 0.07% 97.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 217 0.42% 97.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 119 0.23% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 48 0.09% 98.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 34 0.07% 98.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 83 0.16% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 65 0.12% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 27 0.05% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 17 0.03% 98.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 59 0.11% 98.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 39 0.07% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 22 0.04% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 18 0.03% 98.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 16 0.03% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 20 0.04% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 18 0.03% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 13 0.02% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 16 0.03% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 32 0.06% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 16 0.03% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 10 0.02% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 12 0.02% 99.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 13 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 13 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 12 0.02% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 12 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 14 0.03% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 6 0.01% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 9 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 11 0.02% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 10 0.02% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 10 0.02% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 14 0.03% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 9 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 6 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 11 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 9 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 5 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 6 0.01% 99.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 3 0.01% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 6 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 6 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 6 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 5 0.01% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 5 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 9 0.02% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 6 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 4 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 10 0.02% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 4 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 15 0.03% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 82 0.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52112 # Bytes accessed per row activation -system.physmem.totQLat 6294270000 # Total ticks spent queuing -system.physmem.totMemAccLat 8641432500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831665000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1515497500 # Total ticks spent accessing banks -system.physmem.avgQLat 37841.38 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 9111.23 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 43247 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 376.488173 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 224.222062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.745587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13435 31.07% 31.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8988 20.78% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4626 10.70% 62.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2682 6.20% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2451 5.67% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1626 3.76% 78.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1548 3.58% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1315 3.04% 84.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6576 15.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 43247 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6943 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.949301 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.898812 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6941 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6943 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.417831 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.341311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.942818 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6412 92.35% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 14 0.20% 92.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 48 0.69% 93.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 135 1.94% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 111 1.60% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 69 0.99% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 62 0.89% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 19 0.27% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.20% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 9 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.09% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.06% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 3 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 4 0.06% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 10 0.14% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6943 # Writes before turning the bus around for reads +system.physmem.totQLat 5579601250 # Total ticks spent queuing +system.physmem.totMemAccLat 7987531250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831465000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1576465000 # Total ticks spent accessing banks +system.physmem.avgQLat 33552.83 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 9480.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51952.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 427.92 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 293.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 427.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 293.33 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48032.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 431.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 295.70 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 431.41 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 295.78 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 5.63 # Data bus utilization in percentage -system.physmem.busUtilRead 3.34 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.29 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.35 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing -system.physmem.readRowHits 152220 # Number of row buffer hits during reads -system.physmem.writeRowHits 76017 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 88734.23 # Average gap between requests -system.physmem.pageHitRate 81.41 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.97 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 721253937 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 35533 # Transaction distribution -system.membus.trans_dist::ReadResp 35533 # Transaction distribution -system.membus.trans_dist::Writeback 114019 # Transaction distribution -system.membus.trans_dist::ReadExReq 130801 # Transaction distribution -system.membus.trans_dist::ReadExResp 130801 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446687 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17942592 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17942592 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17942592 # Total data (bytes) +system.physmem.busUtil 5.68 # Data bus utilization in percentage +system.physmem.busUtilRead 3.37 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.31 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing +system.physmem.readRowHits 144952 # Number of row buffer hits during reads +system.physmem.writeRowHits 82533 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.39 # Row buffer hit rate for writes +system.physmem.avgGap 88010.62 # Average gap between requests +system.physmem.pageHitRate 81.15 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 12.46 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 727183981 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35502 # Transaction distribution +system.membus.trans_dist::ReadResp 35502 # Transaction distribution +system.membus.trans_dist::Writeback 114017 # Transaction distribution +system.membus.trans_dist::ReadExReq 130798 # Transaction distribution +system.membus.trans_dist::ReadExResp 130798 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446617 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940288 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 17940288 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940288 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1242193000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1242249500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1539567000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1535210250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16535475 # Number of BP lookups -system.cpu.branchPred.condPredicted 10680150 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 413128 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11281450 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7332394 # Number of BTB hits +system.cpu.branchPred.lookups 16545461 # Number of BP lookups +system.cpu.branchPred.condPredicted 10688882 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 416220 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11528806 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7341014 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.995138 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1986702 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41528 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.675406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1988101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 40517 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22396974 # DTB read hits -system.cpu.dtb.read_misses 220986 # DTB read misses -system.cpu.dtb.read_acv 45 # DTB read access violations -system.cpu.dtb.read_accesses 22617960 # DTB read accesses -system.cpu.dtb.write_hits 15703419 # DTB write hits -system.cpu.dtb.write_misses 41132 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15744551 # DTB write accesses -system.cpu.dtb.data_hits 38100393 # DTB hits -system.cpu.dtb.data_misses 262118 # DTB misses -system.cpu.dtb.data_acv 49 # DTB access violations -system.cpu.dtb.data_accesses 38362511 # DTB accesses -system.cpu.itb.fetch_hits 13901400 # ITB hits -system.cpu.itb.fetch_misses 35038 # ITB misses +system.cpu.dtb.read_hits 22395847 # DTB read hits +system.cpu.dtb.read_misses 219375 # DTB read misses +system.cpu.dtb.read_acv 51 # DTB read access violations +system.cpu.dtb.read_accesses 22615222 # DTB read accesses +system.cpu.dtb.write_hits 15705719 # DTB write hits +system.cpu.dtb.write_misses 41176 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 15746895 # DTB write accesses +system.cpu.dtb.data_hits 38101566 # DTB hits +system.cpu.dtb.data_misses 260551 # DTB misses +system.cpu.dtb.data_acv 53 # DTB access violations +system.cpu.dtb.data_accesses 38362117 # DTB accesses +system.cpu.itb.fetch_hits 13909771 # ITB hits +system.cpu.itb.fetch_misses 35326 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13936438 # ITB accesses +system.cpu.itb.fetch_accesses 13945097 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -369,238 +329,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 49753887 # number of cpu cycles simulated +system.cpu.numCycles 49341816 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15785706 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105319377 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16535475 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9319096 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19535939 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1995771 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7614067 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7763 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 310803 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 76 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13901400 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 208167 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44703895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.355933 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.120018 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15790710 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105357061 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16545461 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9329115 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19544756 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1999793 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7570274 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314157 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13909771 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 205601 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44679590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.358058 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120608 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25167956 56.30% 56.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1528006 3.42% 59.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1366750 3.06% 62.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1512499 3.38% 66.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4138976 9.26% 75.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846420 4.13% 79.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 671442 1.50% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1071050 2.40% 83.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7400796 16.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25134834 56.26% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1529938 3.42% 59.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1370308 3.07% 62.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1511826 3.38% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4137251 9.26% 75.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1848058 4.14% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674230 1.51% 81.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1068805 2.39% 83.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7404340 16.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44703895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.332345 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.116807 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16874554 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7142634 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18558802 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 783225 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1344680 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3743647 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107085 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103596223 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 302671 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1344680 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17346175 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4853031 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85455 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18830704 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2243850 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102345999 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 509 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2584 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2124299 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61632193 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123331325 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123012632 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 318692 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44679590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.335323 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.135249 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16882265 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7097756 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18571135 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 780643 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1347791 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3745694 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 106722 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103639332 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 302042 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1347791 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17356196 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4802628 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85206 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18838214 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2249555 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102372003 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 486 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2542 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2130672 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61646955 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123349032 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123030884 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 318147 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9085312 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5523 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5521 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4830878 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23230757 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16269125 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1199559 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 452349 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90724395 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5268 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88415459 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 94171 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10689316 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4663748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 685 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44703895 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.977802 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109542 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9100074 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5525 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5523 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4824517 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23234080 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16271017 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1195142 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 460766 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90738136 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5320 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88425930 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 95845 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10681231 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4663960 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 737 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44679590 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.979112 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109137 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16507369 36.93% 36.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6840922 15.30% 52.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5582133 12.49% 64.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4775843 10.68% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4724672 10.57% 85.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2622986 5.87% 91.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1924028 4.30% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1282580 2.87% 99.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443362 0.99% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16474837 36.87% 36.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6839728 15.31% 52.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5595634 12.52% 64.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4775900 10.69% 75.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4713198 10.55% 85.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2628457 5.88% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1926364 4.31% 96.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1289803 2.89% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 435669 0.98% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44703895 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44679590 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126532 6.78% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 788261 42.26% 49.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 950494 50.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126495 6.81% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 783002 42.16% 48.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 947503 51.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49348241 55.81% 55.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43886 0.05% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121319 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49357567 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43846 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121254 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 121135 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38977 0.04% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22847876 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15893880 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 59 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38967 0.04% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22848069 25.84% 82.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15894942 17.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88415459 # Type of FU issued -system.cpu.iq.rate 1.777056 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1865287 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021097 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222890546 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101022608 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86533727 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603725 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414375 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294393 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89978801 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301945 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1469946 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88425930 # Type of FU issued +system.cpu.iq.rate 1.792109 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1857000 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021001 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222881148 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101028016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86544064 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603147 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414515 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294050 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 89981281 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301649 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467705 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2954119 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4771 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18244 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1655748 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2957442 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4633 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18287 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1657640 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3011 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 95424 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2832 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 88581 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1344680 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3730457 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74850 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100207935 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 218697 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23230757 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16269125 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5268 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49823 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6563 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18244 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192844 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 159688 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 352532 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87575579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22621211 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 839880 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1347791 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3663804 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 77381 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100225939 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 227298 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23234080 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16271017 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5320 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49801 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6534 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18287 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 195800 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160651 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 356451 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87582928 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22618546 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 843002 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9478272 # number of nop insts executed -system.cpu.iew.exec_refs 38366084 # number of memory reference insts executed -system.cpu.iew.exec_branches 15081989 # Number of branches executed -system.cpu.iew.exec_stores 15744873 # Number of stores executed -system.cpu.iew.exec_rate 1.760176 # Inst execution rate -system.cpu.iew.wb_sent 87218892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86828120 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33348545 # num instructions producing a value -system.cpu.iew.wb_consumers 43472168 # num instructions consuming a value +system.cpu.iew.exec_nop 9482483 # number of nop insts executed +system.cpu.iew.exec_refs 38365741 # number of memory reference insts executed +system.cpu.iew.exec_branches 15084551 # Number of branches executed +system.cpu.iew.exec_stores 15747195 # Number of stores executed +system.cpu.iew.exec_rate 1.775024 # Inst execution rate +system.cpu.iew.wb_sent 87227797 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86838114 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33351220 # num instructions producing a value +system.cpu.iew.wb_consumers 43473707 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.745152 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.767124 # average fanout of values written-back +system.cpu.iew.wb_rate 1.759929 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.767158 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8870802 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8889589 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 308267 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43359215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.037414 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.791048 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 311933 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43331799 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.038703 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.791883 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20533772 47.36% 47.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7032064 16.22% 63.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3351851 7.73% 71.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2056930 4.74% 76.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2048633 4.72% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1170984 2.70% 83.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1108500 2.56% 86.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718184 1.66% 87.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5338297 12.31% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20501224 47.31% 47.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7041698 16.25% 63.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3356099 7.75% 71.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2051116 4.73% 76.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2049317 4.73% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1167384 2.69% 83.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1102119 2.54% 86.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 716210 1.65% 87.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5346632 12.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43359215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43331799 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -611,230 +571,229 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5338297 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5346632 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133915050 # The number of ROB reads -system.cpu.rob.rob_writes 195770285 # The number of ROB writes -system.cpu.timesIdled 83590 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5049992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133898086 # The number of ROB reads +system.cpu.rob.rob_writes 195811124 # The number of ROB writes +system.cpu.timesIdled 85852 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4662226 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.625114 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.625114 # CPI: Total CPI of All Threads -system.cpu.ipc 1.599709 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.599709 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115901393 # number of integer regfile reads -system.cpu.int_regfile_writes 57502981 # number of integer regfile writes -system.cpu.fp_regfile_reads 249622 # number of floating regfile reads -system.cpu.fp_regfile_writes 240154 # number of floating regfile writes -system.cpu.misc_regfile_reads 38048 # number of misc regfile reads +system.cpu.cpi 0.619936 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.619936 # CPI: Total CPI of All Threads +system.cpu.ipc 1.613069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.613069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115913702 # number of integer regfile reads +system.cpu.int_regfile_writes 57508814 # number of integer regfile writes +system.cpu.fp_regfile_reads 249357 # number of floating regfile reads +system.cpu.fp_regfile_writes 240037 # number of floating regfile writes +system.cpu.misc_regfile_reads 38036 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1204366702 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 155800 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 155799 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143411 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143411 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 187341 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580010 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 767351 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5994880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23966080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29960960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29960960 # Total data (bytes) +system.cpu.toL2Bus.throughput 1213726946 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168929 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143419 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143419 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 580053 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 766814 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5976320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23967424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 29943744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29943744 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 403000500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 402865000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 141888472 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 141399227 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 326227248 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 324564248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.cpu.icache.tags.replacements 91622 # number of replacements -system.cpu.icache.tags.tagsinuse 1926.124790 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13794941 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 93670 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.271709 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20019697250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1926.124790 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.940491 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.940491 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 91332 # number of replacements +system.cpu.icache.tags.tagsinuse 1925.493490 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13803368 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93380 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 147.819319 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19891128250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1925.493490 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.940182 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.940182 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1531 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 359 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1527 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 358 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27896466 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27896466 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13794941 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13794941 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13794941 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13794941 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13794941 # number of overall hits -system.cpu.icache.overall_hits::total 13794941 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106457 # number of overall misses -system.cpu.icache.overall_misses::total 106457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2019960968 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2019960968 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2019960968 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2019960968 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2019960968 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2019960968 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13901398 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13901398 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13901398 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13901398 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13901398 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13901398 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007658 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007658 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007658 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007658 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007658 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007658 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18974.430690 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18974.430690 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18974.430690 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18974.430690 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18974.430690 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27912922 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27912922 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13803368 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13803368 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13803368 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13803368 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13803368 # number of overall hits +system.cpu.icache.overall_hits::total 13803368 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 106403 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 106403 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 106403 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 106403 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 106403 # number of overall misses +system.cpu.icache.overall_misses::total 106403 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2000796974 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2000796974 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2000796974 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2000796974 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2000796974 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2000796974 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13909771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13909771 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13909771 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13909771 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13909771 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13909771 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007650 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007650 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007650 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007650 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007650 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007650 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18803.952652 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18803.952652 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18803.952652 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18803.952652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18803.952652 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18803.952652 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 263 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.187500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.916667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12786 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12786 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12786 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12786 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12786 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12786 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93671 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93671 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93671 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93671 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93671 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93671 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551735028 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1551735028 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551735028 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1551735028 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551735028 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1551735028 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006738 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006738 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006738 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006738 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16565.799746 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16565.799746 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16565.799746 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16565.799746 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13022 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 13022 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 13022 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 13022 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 13022 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 13022 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93381 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93381 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93381 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93381 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93381 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93381 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1534559773 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1534559773 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1534559773 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1534559773 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1534559773 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1534559773 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006713 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006713 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006713 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006713 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16433.319123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16433.319123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16433.319123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16433.319123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16433.319123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16433.319123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132428 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30694.665852 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 159970 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164497 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.972480 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132391 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30672.416469 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 159732 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164458 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.971263 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26341.005950 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2105.517354 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2248.142548 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.803864 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.068608 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.936727 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32069 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1443 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18046 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12352 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 26335.603733 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.899695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 2234.913041 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.803699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064145 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.068204 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.936048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32067 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1463 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18089 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12275 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 61 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978668 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4053036 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4053036 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 86004 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34262 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120266 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168930 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168930 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12610 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12610 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 86004 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46872 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132876 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 86004 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46872 # number of overall hits -system.cpu.l2cache.overall_hits::total 132876 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7667 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27867 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35534 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130801 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130801 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7667 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158668 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166335 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7667 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158668 # number of overall misses -system.cpu.l2cache.overall_misses::total 166335 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 597389250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2119099250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2716488500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13782092500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13782092500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 597389250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15901191750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16498581000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 597389250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15901191750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16498581000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 93671 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62129 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 155800 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168930 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168930 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143411 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143411 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 93671 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205540 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 299211 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 93671 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205540 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 299211 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081850 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448535 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.228074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912071 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912071 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081850 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771957 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.555912 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081850 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771957 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.555912 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77916.949263 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76043.321850 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 76447.585411 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 105366.874106 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 105366.874106 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77916.949263 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100216.752905 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 99188.871855 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77916.949263 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100216.752905 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 99188.871855 # average overall miss latency +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978607 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4050853 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4050853 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 85734 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34287 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 120021 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168929 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168929 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12621 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12621 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 85734 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46908 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 132642 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 85734 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46908 # number of overall hits +system.cpu.l2cache.overall_hits::total 132642 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7647 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 27856 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35503 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130798 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130798 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7647 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158654 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166301 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7647 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158654 # number of overall misses +system.cpu.l2cache.overall_misses::total 166301 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 583211250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2050433250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2633644500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13218958750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13218958750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 583211250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15269392000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15852603250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 583211250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15269392000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15852603250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 93381 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62143 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 155524 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168929 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168929 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143419 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143419 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 93381 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205562 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 298943 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 93381 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205562 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 298943 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.081890 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448256 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.228280 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911999 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911999 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.081890 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771806 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.556297 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.081890 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771806 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.556297 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76266.673205 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73608.315982 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74180.900206 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101063.921084 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101063.921084 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76266.673205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96243.347158 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 95324.762028 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76266.673205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96243.347158 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 95324.762028 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -843,171 +802,171 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114019 # number of writebacks -system.cpu.l2cache.writebacks::total 114019 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7667 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27867 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35534 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130801 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130801 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7667 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158668 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166335 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7667 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158668 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166335 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 500389250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1762290750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2262680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12178041500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12178041500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 500389250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13940332250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14440721500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 500389250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13940332250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14440721500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448535 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228074 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912071 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912071 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.555912 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081850 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771957 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.555912 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65265.325421 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63239.342233 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63676.478865 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93103.581012 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93103.581012 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65265.325421 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87858.498563 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86817.095019 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114017 # number of writebacks +system.cpu.l2cache.writebacks::total 114017 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7647 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27856 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35503 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130798 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130798 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7647 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158654 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7647 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158654 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166301 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 486616750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1695026750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2181643500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11619308250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11619308250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 486616750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13314335000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13800951750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 486616750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13314335000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13800951750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448256 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228280 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911999 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911999 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771806 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.556297 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081890 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771806 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.556297 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63634.987577 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60849.610497 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61449.553559 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88833.990199 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88833.990199 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63634.987577 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83920.575592 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82987.785702 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63634.987577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83920.575592 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82987.785702 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 201444 # number of replacements -system.cpu.dcache.tags.tagsinuse 4074.011744 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34183901 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205540 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 166.312645 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 220306250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4074.011744 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994632 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994632 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201466 # number of replacements +system.cpu.dcache.tags.tagsinuse 4073.410780 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34191132 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205562 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 166.330022 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 225470250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4073.410780 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.994485 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.994485 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1078 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1081 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2933 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71186914 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71186914 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20609776 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20609776 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574069 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574069 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34183845 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34183845 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34183845 # number of overall hits -system.cpu.dcache.overall_hits::total 34183845 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 267478 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 267478 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1039308 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1039308 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1306786 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1306786 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1306786 # number of overall misses -system.cpu.dcache.overall_misses::total 1306786 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16319754498 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16319754498 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 88798095012 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 88798095012 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105117849510 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105117849510 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105117849510 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105117849510 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20877254 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20877254 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 71201646 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71201646 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20617040 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20617040 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574040 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574040 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34191080 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34191080 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34191080 # number of overall hits +system.cpu.dcache.overall_hits::total 34191080 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267573 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267573 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039337 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039337 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306910 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306910 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306910 # number of overall misses +system.cpu.dcache.overall_misses::total 1306910 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15791609498 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15791609498 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 85266584825 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 85266584825 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 101058194323 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 101058194323 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 101058194323 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 101058194323 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20884613 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20884613 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35490631 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35490631 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35490631 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35490631 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35497990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35497990 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35497990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35497990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012812 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012812 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036821 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036821 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036821 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036821 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61013.445958 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61013.445958 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85439.633883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85439.633883 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80439.987504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80439.987504 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80439.987504 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5138864 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071122 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036816 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036816 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036816 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036816 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59017.948365 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59017.948365 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82039.400911 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 82039.400911 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 77326.054834 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 77326.054834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 77326.054834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 77326.054834 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4861037 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112181 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 111685 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.808684 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.524529 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 131 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168930 # number of writebacks -system.cpu.dcache.writebacks::total 168930 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205345 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205345 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1101246 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1101246 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1101246 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1101246 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62133 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62133 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143407 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143407 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205540 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205540 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205540 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205540 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2525887252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2525887252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14052510994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14052510994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16578398246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16578398246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16578398246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16578398246 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168929 # number of writebacks +system.cpu.dcache.writebacks::total 168929 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205428 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205428 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895920 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895920 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1101348 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1101348 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1101348 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1101348 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62145 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62145 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143417 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143417 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205562 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205562 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205562 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205562 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2457360502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2457360502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13489619744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13489619744 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15946980246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15946980246 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15946980246 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15946980246 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002976 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002976 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005791 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005791 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005791 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40652.909919 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40652.909919 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97990.411863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97990.411863 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80657.770974 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80657.770974 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39542.368686 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39542.368686 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94058.722076 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94058.722076 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77577.471741 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77577.471741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77577.471741 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77577.471741 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 9978094b9..e2e70aeb1 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026790 # Number of seconds simulated -sim_ticks 26790388000 # Number of ticks simulated -final_tick 26790388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026596 # Number of seconds simulated +sim_ticks 26596403000 # Number of ticks simulated +final_tick 26596403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134448 # Simulator instruction rate (inst/s) -host_op_rate 190799 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50797444 # Simulator tick rate (ticks/s) -host_mem_usage 278572 # Number of bytes of host memory used -host_seconds 527.40 # Real time elapsed on the host +host_inst_rate 110554 # Simulator instruction rate (inst/s) +host_op_rate 156889 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41466984 # Simulator tick rate (ticks/s) +host_mem_usage 321816 # Number of bytes of host memory used +host_seconds 641.39 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 297344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7942912 # Number of bytes read from this memory -system.physmem.bytes_read::total 8240256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 297344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 297344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5371968 # Number of bytes written to this memory -system.physmem.bytes_written::total 5371968 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124108 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83937 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83937 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11098906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 296483649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 307582555 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11098906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11098906 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 200518484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 200518484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 200518484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11098906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 296483649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 508101040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128754 # Number of read requests accepted -system.physmem.writeReqs 83937 # Number of write requests accepted -system.physmem.readBursts 128754 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83937 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8240128 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 5371648 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8240256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5371968 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 297984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942976 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124109 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128765 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11203921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 298648505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 309852426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11203921 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11203921 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 202000248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 202000248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 202000248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11203921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 298648505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 511852674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128766 # Number of read requests accepted +system.physmem.writeReqs 83945 # Number of write requests accepted +system.physmem.readBursts 128766 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 83945 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8240704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8241024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5372480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 308 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8131 # Per bank write bursts -system.physmem.perBankRdBursts::1 8390 # Per bank write bursts -system.physmem.perBankRdBursts::2 8247 # Per bank write bursts -system.physmem.perBankRdBursts::3 8163 # Per bank write bursts -system.physmem.perBankRdBursts::4 8302 # Per bank write bursts -system.physmem.perBankRdBursts::5 8446 # Per bank write bursts -system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7962 # Per bank write bursts -system.physmem.perBankRdBursts::8 8060 # Per bank write bursts -system.physmem.perBankRdBursts::9 7613 # Per bank write bursts -system.physmem.perBankRdBursts::10 7786 # Per bank write bursts -system.physmem.perBankRdBursts::11 7812 # Per bank write bursts -system.physmem.perBankRdBursts::12 7879 # Per bank write bursts -system.physmem.perBankRdBursts::13 7885 # Per bank write bursts -system.physmem.perBankRdBursts::14 7978 # Per bank write bursts -system.physmem.perBankRdBursts::15 8010 # Per bank write bursts -system.physmem.perBankWrBursts::0 5179 # Per bank write bursts -system.physmem.perBankWrBursts::1 5375 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 300 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 8143 # Per bank write bursts +system.physmem.perBankRdBursts::1 8388 # Per bank write bursts +system.physmem.perBankRdBursts::2 8255 # Per bank write bursts +system.physmem.perBankRdBursts::3 8165 # Per bank write bursts +system.physmem.perBankRdBursts::4 8298 # Per bank write bursts +system.physmem.perBankRdBursts::5 8451 # Per bank write bursts +system.physmem.perBankRdBursts::6 8084 # Per bank write bursts +system.physmem.perBankRdBursts::7 7964 # Per bank write bursts +system.physmem.perBankRdBursts::8 8055 # Per bank write bursts +system.physmem.perBankRdBursts::9 7611 # Per bank write bursts +system.physmem.perBankRdBursts::10 7782 # Per bank write bursts +system.physmem.perBankRdBursts::11 7815 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7884 # Per bank write bursts +system.physmem.perBankRdBursts::14 7976 # Per bank write bursts +system.physmem.perBankRdBursts::15 8009 # Per bank write bursts +system.physmem.perBankWrBursts::0 5177 # Per bank write bursts +system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5289 # Per bank write bursts system.physmem.perBankWrBursts::3 5157 # Per bank write bursts -system.physmem.perBankWrBursts::4 5265 # Per bank write bursts +system.physmem.perBankWrBursts::4 5267 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5207 # Per bank write bursts -system.physmem.perBankWrBursts::7 5048 # Per bank write bursts -system.physmem.perBankWrBursts::8 5029 # Per bank write bursts +system.physmem.perBankWrBursts::6 5201 # Per bank write bursts +system.physmem.perBankWrBursts::7 5049 # Per bank write bursts +system.physmem.perBankWrBursts::8 5030 # Per bank write bursts system.physmem.perBankWrBursts::9 5089 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts +system.physmem.perBankWrBursts::10 5246 # Per bank write bursts system.physmem.perBankWrBursts::11 5144 # Per bank write bursts system.physmem.perBankWrBursts::12 5342 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5226 # Per bank write bursts +system.physmem.perBankWrBursts::14 5452 # Per bank write bursts +system.physmem.perBankWrBursts::15 5225 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26790282500 # Total gap between requests +system.physmem.totGap 26596386500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128754 # Read request sizes (log2) +system.physmem.readPktSize::6 128766 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83937 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 73147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1319 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83945 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 71874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1900 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -129,219 +129,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 3678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 3681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 3686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 3683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 3698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 37879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.276222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.215706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 692.456870 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 15075 39.80% 39.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 5750 15.18% 54.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 3421 9.03% 64.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2320 6.12% 70.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1668 4.40% 74.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1547 4.08% 78.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 1100 2.90% 81.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 895 2.36% 83.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 687 1.81% 85.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 539 1.42% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 385 1.02% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 594 1.57% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 272 0.72% 90.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 354 0.93% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 173 0.46% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 239 0.63% 92.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 118 0.31% 92.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 247 0.65% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 108 0.29% 93.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 279 0.74% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 118 0.31% 94.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 446 1.18% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 106 0.28% 96.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 237 0.63% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 43 0.11% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 118 0.31% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 42 0.11% 97.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 85 0.22% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 20 0.05% 97.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 62 0.16% 97.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 44 0.12% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 19 0.05% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 33 0.09% 98.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 16 0.04% 98.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 33 0.09% 98.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 8 0.02% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 24 0.06% 98.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 13 0.03% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 33 0.09% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 14 0.04% 98.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 23 0.06% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 10 0.03% 98.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 16 0.04% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 9 0.02% 98.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 18 0.05% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 4 0.01% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 17 0.04% 98.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 11 0.03% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 19 0.05% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3265 11 0.03% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 26 0.07% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3393 4 0.01% 98.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 7 0.02% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 10 0.03% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 5 0.01% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 7 0.02% 99.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 10 0.03% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 9 0.02% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 16 0.04% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 7 0.02% 99.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 9 0.02% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4161 5 0.01% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4225 10 0.03% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 10 0.03% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 11 0.03% 99.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 6 0.02% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 10 0.03% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 7 0.02% 99.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 6 0.02% 99.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4673 5 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4801 2 0.01% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 12 0.03% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 8 0.02% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 5 0.01% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5121 9 0.02% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 2 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 7 0.02% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5313 4 0.01% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 6 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 5 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5505 7 0.02% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 10 0.03% 99.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5825 5 0.01% 99.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 2 0.01% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 4 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6017 1 0.00% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 6 0.02% 99.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6209 6 0.02% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 3 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 5 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6401 4 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 5 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6657 4 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 5 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 5 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6913 4 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 5 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7297 3 0.01% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7681 3 0.01% 99.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8065 4 0.01% 99.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8129 6 0.02% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 37 0.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 37879 # Bytes accessed per row activation -system.physmem.totQLat 3022726750 # Total ticks spent queuing -system.physmem.totMemAccLat 4971045500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 643760000 # Total ticks spent in databus transfers -system.physmem.totBankLat 1304558750 # Total ticks spent accessing banks -system.physmem.avgQLat 23477.12 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 10132.34 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5492 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 29627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 410.695649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 253.351666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 359.831379 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7793 26.30% 26.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6034 20.37% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3130 10.56% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2203 7.44% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2053 6.93% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1365 4.61% 76.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1045 3.53% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1191 4.02% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4813 16.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 29627 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5084 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.322974 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 394.325536 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5082 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5084 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.507474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.421096 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.063173 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4555 89.59% 89.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 21 0.41% 90.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 58 1.14% 91.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 170 3.34% 94.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 125 2.46% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 1.12% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 23 0.45% 98.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 15 0.30% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 10 0.20% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.12% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 5 0.10% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.08% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.04% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 2 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 13 0.26% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5084 # Writes before turning the bus around for reads +system.physmem.totQLat 2537399000 # Total ticks spent queuing +system.physmem.totMemAccLat 4590111500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643805000 # Total ticks spent in databus transfers +system.physmem.totBankLat 1408907500 # Total ticks spent accessing banks +system.physmem.avgQLat 19706.27 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 10942.04 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38609.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 307.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 200.51 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 307.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 200.52 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 35648.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 309.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 201.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 309.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 202.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.97 # Data bus utilization in percentage -system.physmem.busUtilRead 2.40 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.57 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.70 # Average write queue length when enqueuing -system.physmem.readRowHits 117872 # Number of row buffer hits during reads -system.physmem.writeRowHits 56933 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 67.83 # Row buffer hit rate for writes -system.physmem.avgGap 125958.70 # Average gap between requests -system.physmem.pageHitRate 82.19 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 11.78 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 508101040 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 26500 # Transaction distribution -system.membus.trans_dist::ReadResp 26500 # Transaction distribution -system.membus.trans_dist::Writeback 83937 # Transaction distribution -system.membus.trans_dist::UpgradeReq 308 # Transaction distribution -system.membus.trans_dist::UpgradeResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 102254 # Transaction distribution -system.membus.trans_dist::ReadExResp 102254 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342061 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 342061 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13612224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 13612224 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 13612224 # Total data (bytes) +system.physmem.busUtil 4.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.58 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.36 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 112537 # Number of row buffer hits during reads +system.physmem.writeRowHits 62593 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.56 # Row buffer hit rate for writes +system.physmem.avgGap 125035.31 # Average gap between requests +system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 11.63 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 511852674 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26511 # Transaction distribution +system.membus.trans_dist::ReadResp 26510 # Transaction distribution +system.membus.trans_dist::Writeback 83945 # Transaction distribution +system.membus.trans_dist::UpgradeReq 300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 300 # Transaction distribution +system.membus.trans_dist::ReadExReq 102255 # Transaction distribution +system.membus.trans_dist::ReadExResp 102255 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342076 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 342076 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13613440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 13613440 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13613440 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 934459500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 934794000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1203485442 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1201882201 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 16615535 # Number of BP lookups -system.cpu.branchPred.condPredicted 12754556 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602333 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10795457 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7770077 # Number of BTB hits +system.cpu.branchPred.lookups 16626299 # Number of BP lookups +system.cpu.branchPred.condPredicted 12761376 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 603542 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10553987 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7772041 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.975434 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1823925 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 112966 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.640805 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1823891 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 112970 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -427,136 +381,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 53580777 # number of cpu cycles simulated +system.cpu.numCycles 53192807 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12546836 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85170403 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16615535 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9594002 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21183792 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2362024 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10685029 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 63 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 557 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11675856 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179932 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46149323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.583841 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.333163 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12548027 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85225985 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16626299 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9595932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21195811 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2371567 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10764095 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 524 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11679981 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179230 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46249849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.580108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.332376 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24986446 54.14% 54.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2137638 4.63% 58.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1962079 4.25% 63.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2043997 4.43% 67.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466310 3.18% 70.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1377582 2.99% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 960310 2.08% 75.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1185958 2.57% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10029003 21.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25074842 54.22% 54.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2134843 4.62% 58.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1965334 4.25% 63.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2045724 4.42% 67.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1467866 3.17% 70.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1377638 2.98% 73.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 956719 2.07% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1188096 2.57% 78.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10038787 21.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46149323 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310103 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.589570 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14635353 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9029918 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19485051 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1368887 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1630114 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3325603 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104819 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116788167 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 363460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1630114 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16340014 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2585458 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1028005 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19100045 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5465687 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114914880 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17272 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4606354 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 316 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115243032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529540867 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 476170049 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2600 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46249849 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.312567 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.602209 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14635842 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9109376 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19493309 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1372783 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1638539 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3331010 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104505 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116880506 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 361697 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1638539 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16346771 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2652791 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1020533 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19105290 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5485925 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114999580 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 152 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17445 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4623062 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 183 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115318587 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529932404 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 476522297 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2751 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16110360 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20388 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20384 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12995984 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29602749 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22439249 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3932152 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4401403 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111507434 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 36062 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107242523 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272405 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10768427 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25739903 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2276 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46149323 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.323816 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.990206 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16185915 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20374 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20369 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13024660 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29615928 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22451967 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3877153 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4417845 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111572377 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35991 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107273861 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 274045 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10831021 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25918238 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2205 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46249849 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.319442 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.990414 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10919279 23.66% 23.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8079518 17.51% 41.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7423472 16.09% 57.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7094481 15.37% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5420902 11.75% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3930329 8.52% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1841974 3.99% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 869423 1.88% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 569945 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10978806 23.74% 23.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8116860 17.55% 41.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7434269 16.07% 57.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7097763 15.35% 72.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5421519 11.72% 84.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3913580 8.46% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842525 3.98% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 870168 1.88% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 574359 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46149323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46249849 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112279 4.53% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1361817 54.98% 59.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1002641 40.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 113368 4.58% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1353818 54.73% 59.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1006223 40.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56635396 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91455 0.09% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56655592 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91505 0.09% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 208 0.00% 52.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 217 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued @@ -582,84 +536,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28883502 26.93% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21631955 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28893939 26.93% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21632601 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107242523 # Type of FU issued -system.cpu.iq.rate 2.001511 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2476739 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023095 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263382945 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122340040 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105564996 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 568 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 856 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109718975 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 287 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2181751 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107273861 # Type of FU issued +system.cpu.iq.rate 2.016699 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2473411 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023057 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263544444 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122467509 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105589962 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 583 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 918 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 177 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109746981 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 291 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2178933 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2295641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6455 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29983 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1883511 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2308820 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6717 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29962 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1896229 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 679 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 670 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1630114 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1093825 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45147 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111553302 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 294819 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29602749 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22439249 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 20142 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6322 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5200 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29983 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391827 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 180696 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 572523 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106211851 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28585179 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030672 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1638539 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1135526 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 46796 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111618146 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297287 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29615928 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22451967 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 20071 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6522 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5186 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29962 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 392730 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181164 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573894 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106245086 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28594669 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1028775 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9806 # number of nop insts executed -system.cpu.iew.exec_refs 49926975 # number of memory reference insts executed -system.cpu.iew.exec_branches 14599283 # Number of branches executed -system.cpu.iew.exec_stores 21341796 # Number of stores executed -system.cpu.iew.exec_rate 1.982275 # Inst execution rate -system.cpu.iew.wb_sent 105782073 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105565164 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53316718 # num instructions producing a value -system.cpu.iew.wb_consumers 103963305 # num instructions consuming a value +system.cpu.iew.exec_nop 9778 # number of nop insts executed +system.cpu.iew.exec_refs 49940992 # number of memory reference insts executed +system.cpu.iew.exec_branches 14602318 # Number of branches executed +system.cpu.iew.exec_stores 21346323 # Number of stores executed +system.cpu.iew.exec_rate 1.997358 # Inst execution rate +system.cpu.iew.wb_sent 105809508 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105590139 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53305824 # num instructions producing a value +system.cpu.iew.wb_consumers 103866304 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.970206 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512842 # average fanout of values written-back +system.cpu.iew.wb_rate 1.985045 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.513216 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10921742 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10986690 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499421 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44519209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.260427 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.765009 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 500884 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44611310 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.255760 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.762475 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15470185 34.75% 34.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11634994 26.13% 60.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3452010 7.75% 68.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2868846 6.44% 75.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1865323 4.19% 79.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1954753 4.39% 83.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 686748 1.54% 85.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 559469 1.26% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6026881 13.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15517142 34.78% 34.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11686207 26.20% 60.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3450926 7.74% 68.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2867812 6.43% 75.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1872959 4.20% 79.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1945129 4.36% 83.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 689747 1.55% 85.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 566134 1.27% 86.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6015254 13.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44519209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44611310 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -670,243 +624,243 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6026881 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6015254 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 150021199 # The number of ROB reads -system.cpu.rob.rob_writes 224747411 # The number of ROB writes -system.cpu.timesIdled 76674 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7431454 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150189875 # The number of ROB reads +system.cpu.rob.rob_writes 224886049 # The number of ROB writes +system.cpu.timesIdled 80066 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6942958 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.755642 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.755642 # CPI: Total CPI of All Threads -system.cpu.ipc 1.323378 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.323378 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511545132 # number of integer regfile reads -system.cpu.int_regfile_writes 103340839 # number of integer regfile writes -system.cpu.fp_regfile_reads 806 # number of floating regfile reads -system.cpu.fp_regfile_writes 694 # number of floating regfile writes -system.cpu.misc_regfile_reads 49339612 # number of misc regfile reads +system.cpu.cpi 0.750170 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.750170 # CPI: Total CPI of All Threads +system.cpu.ipc 1.333030 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.333030 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511686083 # number of integer regfile reads +system.cpu.int_regfile_writes 103364033 # number of integer regfile writes +system.cpu.fp_regfile_reads 870 # number of floating regfile reads +system.cpu.fp_regfile_writes 762 # number of floating regfile writes +system.cpu.misc_regfile_reads 49348247 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.toL2Bus.throughput 773036658 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 87363 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 87363 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 129182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107048 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63452 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454686 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 518138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2013952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18662976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 20676928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 20676928 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 33024 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 291143497 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 778162370 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 87191 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 87190 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129156 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63123 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 517732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2003904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660352 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 20664256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20664256 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 32064 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 291006496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 48712731 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 48441979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 260354993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 259878236 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 29638 # number of replacements -system.cpu.icache.tags.tagsinuse 1806.211071 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 11640103 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 31672 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 367.520302 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 29471 # number of replacements +system.cpu.icache.tags.tagsinuse 1806.055358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11644351 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 31508 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 369.568078 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1806.211071 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.881939 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.881939 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2034 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.993164 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 23383696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 23383696 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 11640118 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11640118 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11640118 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11640118 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11640118 # number of overall hits -system.cpu.icache.overall_hits::total 11640118 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35738 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35738 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35738 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35738 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35738 # number of overall misses -system.cpu.icache.overall_misses::total 35738 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 828271479 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 828271479 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 828271479 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 828271479 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 828271479 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 828271479 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11675856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11675856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11675856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11675856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11675856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11675856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003061 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003061 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003061 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003061 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003061 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23176.212407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23176.212407 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 856 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1806.055358 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.881863 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.881863 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2037 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 681 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.994629 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 23391772 # Number of tag accesses +system.cpu.icache.tags.data_accesses 23391772 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 11644361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11644361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11644361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11644361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11644361 # number of overall hits +system.cpu.icache.overall_hits::total 11644361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 35619 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 35619 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 35619 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 35619 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 35619 # number of overall misses +system.cpu.icache.overall_misses::total 35619 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 813918226 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 813918226 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 813918226 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 813918226 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 813918226 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 813918226 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11679980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11679980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11679980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11679980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11679980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11679980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003050 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003050 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003050 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003050 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003050 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003050 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22850.675931 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22850.675931 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22850.675931 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22850.675931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22850.675931 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22850.675931 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1148 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52.181818 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3754 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3754 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3754 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3754 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3754 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3754 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31984 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 31984 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 31984 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 31984 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 31984 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 31984 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 671357769 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 671357769 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 671357769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 671357769 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 671357769 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 671357769 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002739 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002739 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002739 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002739 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20990.425494 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20990.425494 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20990.425494 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20990.425494 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20990.425494 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20990.425494 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3807 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3807 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3807 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3807 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3807 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3807 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31812 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31812 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31812 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31812 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31812 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31812 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 661574021 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 661574021 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 661574021 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 661574021 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 661574021 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 661574021 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002724 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002724 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002724 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002724 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20796.366811 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20796.366811 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20796.366811 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20796.366811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20796.366811 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20796.366811 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 95620 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29882.992791 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 89182 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126734 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.703694 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 95635 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29857.974256 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 88990 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126748 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.702102 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26677.610156 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.039955 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1839.342681 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.814136 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041688 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.056132 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.911957 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1849 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20244 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8486 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 391 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949524 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2821016 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2821016 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26805 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33463 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 60268 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 129182 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 129182 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4794 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4794 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26805 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 38257 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 65062 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26805 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 38257 # number of overall hits -system.cpu.l2cache.overall_hits::total 65062 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 4663 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21916 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 26579 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 308 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 308 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102254 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102254 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 4663 # number of demand (read+write) misses +system.cpu.l2cache.tags.occ_blocks::writebacks 26666.144476 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1368.316766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1823.513014 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.813786 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.055649 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.911193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31113 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1837 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20828 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7917 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 394 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949493 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2819349 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2819349 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 26638 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33464 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 60102 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 129156 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 129156 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 14 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 14 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4779 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4779 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 26638 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 38243 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 64881 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 26638 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 38243 # number of overall hits +system.cpu.l2cache.overall_hits::total 64881 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 4673 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21915 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 26588 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 300 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 300 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 102255 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102255 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 4673 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 124170 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128833 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 4663 # number of overall misses +system.cpu.l2cache.demand_misses::total 128843 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 4673 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124170 # number of overall misses -system.cpu.l2cache.overall_misses::total 128833 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 370582250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1870540500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2241122750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22999 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8514187000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8514187000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 370582250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10384727500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10755309750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 370582250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10384727500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10755309750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 31468 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 128843 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 362632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1783611000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2146243500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8210815250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8210815250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 362632500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9994426250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10357058750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 362632500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9994426250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10357058750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 31311 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55379 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 86847 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 129182 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 129182 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 325 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 325 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107048 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107048 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 31468 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 162427 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 193895 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 31468 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 162427 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 193895 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.148182 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395746 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.306044 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947692 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947692 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955216 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955216 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.148182 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.764466 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.664447 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.148182 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.764466 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.664447 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79472.925155 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85350.451725 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 84319.302833 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 74.672078 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 74.672078 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83265.075205 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83265.075205 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79472.925155 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83633.144077 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83482.568519 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79472.925155 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83633.144077 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83482.568519 # average overall miss latency +system.cpu.l2cache.ReadReq_accesses::total 86690 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 129156 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 129156 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 314 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 314 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 31311 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 162413 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 193724 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 31311 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 162413 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 193724 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.149245 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395728 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.306702 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.955414 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.955414 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955351 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955351 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149245 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.764532 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.665085 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149245 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.764532 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.665085 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77601.647764 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81387.679671 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80722.261923 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 78.330000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 78.330000 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80297.445113 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80297.445113 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77601.647764 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80489.862688 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80385.110173 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77601.647764 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80489.862688 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80385.110173 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -915,202 +869,202 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83937 # number of writebacks -system.cpu.l2cache.writebacks::total 83937 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83945 # number of writebacks +system.cpu.l2cache.writebacks::total 83945 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 79 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4646 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21854 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26500 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 308 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102254 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102254 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 4646 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 124108 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 4646 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 124108 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128754 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 311360750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1593475000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1904835750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3080308 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3080308 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7238548000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7238548000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 311360750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8832023000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9143383750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 311360750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8832023000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9143383750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305134 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947692 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947692 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955216 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955216 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764085 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.664040 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.147642 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764085 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.664040 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67016.950065 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72914.569415 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71880.594340 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70789.876191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70789.876191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71164.010378 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71014.366544 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67016.950065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71164.010378 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71014.366544 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4656 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21855 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 26511 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 300 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 300 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102255 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102255 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4656 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124110 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128766 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4656 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124110 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128766 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 303015250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1507731500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1810746750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3014299 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3014299 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6936413750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6936413750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 303015250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8444145250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8747160500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 303015250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8444145250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8747160500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.148702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394644 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305814 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.955414 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.955414 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955351 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955351 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.148702 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764163 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.664688 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.148702 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764163 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.664688 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65080.594931 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68987.943262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68301.714383 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10047.663333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10047.663333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67834.470197 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67834.470197 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65080.594931 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68037.589638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67930.668810 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65080.594931 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68037.589638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67930.668810 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 158331 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.839586 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 44347897 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 162427 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 273.032790 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 363282250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.839586 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993369 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993369 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 158316 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.473281 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 44361466 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 162412 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 273.141554 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 367394250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.473281 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993280 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993280 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2254 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1757 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2276 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 92273995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 92273995 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 26048802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26048802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18266579 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18266579 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15981 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15981 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 92298894 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 92298894 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 26061245 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26061245 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267715 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15989 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15989 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44315381 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44315381 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44315381 # number of overall hits -system.cpu.dcache.overall_hits::total 44315381 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 125140 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 125140 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1583322 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1583322 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1708462 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1708462 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1708462 # number of overall misses -system.cpu.dcache.overall_misses::total 1708462 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5205484954 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5205484954 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127036653749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127036653749 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 856750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 856750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 132242138703 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 132242138703 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 132242138703 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 132242138703 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26173942 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26173942 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44328960 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44328960 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44328960 # number of overall hits +system.cpu.dcache.overall_hits::total 44328960 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125143 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125143 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582186 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582186 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707329 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707329 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707329 # number of overall misses +system.cpu.dcache.overall_misses::total 1707329 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5010352449 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5010352449 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 122380602729 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 122380602729 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 944750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 944750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 127390955178 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 127390955178 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 127390955178 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 127390955178 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26186388 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26186388 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16022 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16022 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16033 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16033 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46023843 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46023843 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46023843 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46023843 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004781 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004781 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079765 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079765 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037121 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037121 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037121 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037121 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77404.202554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77404.202554 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4865 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1223 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.510949 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 87.357143 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46036289 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46036289 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46036289 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46036289 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004779 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079708 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079708 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002744 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002744 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037087 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037087 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037087 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037087 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40037.017244 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40037.017244 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77349.061823 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77349.061823 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21471.590909 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21471.590909 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74614.181085 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74614.181085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74614.181085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74614.181085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4179 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1300 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 140 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.850000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86.666667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129182 # number of writebacks -system.cpu.dcache.writebacks::total 129182 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69727 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69727 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475983 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475983 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1545710 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1545710 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1545710 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1545710 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 129156 # number of writebacks +system.cpu.dcache.writebacks::total 129156 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69730 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69730 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1474872 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1474872 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544602 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107339 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107339 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162752 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162752 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162752 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162752 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2263243564 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2263243564 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8680214182 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8680214182 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10943457746 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10943457746 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10943457746 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10943457746 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107314 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107314 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162727 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162727 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162727 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162727 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2176479313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2176479313 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8375757941 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8375757941 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10552237254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10552237254 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10552237254 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10552237254 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39277.413477 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39277.413477 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78049.070401 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78049.070401 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64846.259404 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64846.259404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64846.259404 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64846.259404 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |