diff options
Diffstat (limited to 'tests/long/se/50.vortex')
4 files changed, 2736 insertions, 2661 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index bd4df05db..dfd14c576 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059732 # Number of seconds simulated -sim_ticks 59731559000 # Number of ticks simulated -final_tick 59731559000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059580 # Number of seconds simulated +sim_ticks 59579614000 # Number of ticks simulated +final_tick 59579614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 330143 # Simulator instruction rate (inst/s) -host_op_rate 330143 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 222980587 # Simulator tick rate (ticks/s) -host_mem_usage 304704 # Number of bytes of host memory used -host_seconds 267.88 # Real time elapsed on the host +host_inst_rate 321432 # Simulator instruction rate (inst/s) +host_op_rate 321432 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216544599 # Simulator tick rate (ticks/s) +host_mem_usage 304972 # Number of bytes of host memory used +host_seconds 275.14 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 516416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10147392 # Number of bytes read from this memory -system.physmem.bytes_read::total 10663808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 516416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 516416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7298880 # Number of bytes written to this memory -system.physmem.bytes_written::total 7298880 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8069 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158553 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166622 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114045 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114045 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8645614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 169883261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178528874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8645614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8645614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122194701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122194701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122194701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8645614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 169883261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 300723576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166622 # Number of read requests accepted -system.physmem.writeReqs 114045 # Number of write requests accepted -system.physmem.readBursts 166622 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114045 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10663168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10663808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7298880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 500672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10147648 # Number of bytes read from this memory +system.physmem.bytes_read::total 10648320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 500672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 500672 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7320576 # Number of bytes written to this memory +system.physmem.bytes_written::total 7320576 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7823 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158557 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166380 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114384 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114384 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8403411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170320808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178724219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8403411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8403411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122870484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122870484 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122870484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8403411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170320808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301594703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166380 # Number of read requests accepted +system.physmem.writeReqs 114384 # Number of write requests accepted +system.physmem.readBursts 166380 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114384 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10648064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 256 # Total number of bytes read from write queue +system.physmem.bytesWritten 7319040 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10648320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7320576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10463 # Per bank write bursts -system.physmem.perBankRdBursts::1 10512 # Per bank write bursts -system.physmem.perBankRdBursts::2 10314 # Per bank write bursts -system.physmem.perBankRdBursts::3 10093 # Per bank write bursts -system.physmem.perBankRdBursts::4 10430 # Per bank write bursts -system.physmem.perBankRdBursts::5 10428 # Per bank write bursts -system.physmem.perBankRdBursts::6 9849 # Per bank write bursts -system.physmem.perBankRdBursts::7 10305 # Per bank write bursts -system.physmem.perBankRdBursts::8 10593 # Per bank write bursts -system.physmem.perBankRdBursts::9 10642 # Per bank write bursts -system.physmem.perBankRdBursts::10 10591 # Per bank write bursts +system.physmem.perBankRdBursts::0 10451 # Per bank write bursts +system.physmem.perBankRdBursts::1 10506 # Per bank write bursts +system.physmem.perBankRdBursts::2 10284 # Per bank write bursts +system.physmem.perBankRdBursts::3 10088 # Per bank write bursts +system.physmem.perBankRdBursts::4 10415 # Per bank write bursts +system.physmem.perBankRdBursts::5 10418 # Per bank write bursts +system.physmem.perBankRdBursts::6 9828 # Per bank write bursts +system.physmem.perBankRdBursts::7 10277 # Per bank write bursts +system.physmem.perBankRdBursts::8 10580 # Per bank write bursts +system.physmem.perBankRdBursts::9 10645 # Per bank write bursts +system.physmem.perBankRdBursts::10 10557 # Per bank write bursts system.physmem.perBankRdBursts::11 10259 # Per bank write bursts -system.physmem.perBankRdBursts::12 10303 # Per bank write bursts -system.physmem.perBankRdBursts::13 10653 # Per bank write bursts -system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10649 # Per bank write bursts -system.physmem.perBankWrBursts::0 7087 # Per bank write bursts -system.physmem.perBankWrBursts::1 7261 # Per bank write bursts -system.physmem.perBankWrBursts::2 7256 # Per bank write bursts -system.physmem.perBankWrBursts::3 6998 # Per bank write bursts -system.physmem.perBankWrBursts::4 7125 # Per bank write bursts -system.physmem.perBankWrBursts::5 7180 # Per bank write bursts -system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7091 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts -system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7094 # Per bank write bursts +system.physmem.perBankRdBursts::12 10298 # Per bank write bursts +system.physmem.perBankRdBursts::13 10623 # Per bank write bursts +system.physmem.perBankRdBursts::14 10516 # Per bank write bursts +system.physmem.perBankRdBursts::15 10631 # Per bank write bursts +system.physmem.perBankWrBursts::0 7162 # Per bank write bursts +system.physmem.perBankWrBursts::1 7274 # Per bank write bursts +system.physmem.perBankWrBursts::2 7295 # Per bank write bursts +system.physmem.perBankWrBursts::3 6999 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 7182 # Per bank write bursts +system.physmem.perBankWrBursts::6 6834 # Per bank write bursts +system.physmem.perBankWrBursts::7 7095 # Per bank write bursts +system.physmem.perBankWrBursts::8 7222 # Per bank write bursts +system.physmem.perBankWrBursts::9 6994 # Per bank write bursts +system.physmem.perBankWrBursts::10 7111 # Per bank write bursts system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6965 # Per bank write bursts -system.physmem.perBankWrBursts::13 7289 # Per bank write bursts -system.physmem.perBankWrBursts::14 7283 # Per bank write bursts -system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.perBankWrBursts::12 6990 # Per bank write bursts +system.physmem.perBankWrBursts::13 7296 # Per bank write bursts +system.physmem.perBankWrBursts::14 7306 # Per bank write bursts +system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59731532000 # Total gap between requests +system.physmem.totGap 59579590000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166622 # Read request sizes (log2) +system.physmem.readPktSize::6 166380 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114045 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1551 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114384 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164758 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1592 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,28 +144,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -193,121 +193,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54759 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 327.975602 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.612520 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.469121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19499 35.61% 35.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11959 21.84% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5687 10.39% 67.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3574 6.53% 74.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2717 4.96% 79.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2083 3.80% 83.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1679 3.07% 86.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1528 2.79% 88.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6033 11.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54759 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.742625 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.245058 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7015 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7017 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.249109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.233383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.749815 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6248 89.04% 89.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 18 0.26% 89.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 569 8.11% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 155 2.21% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 21 0.30% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 54737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.220838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.100573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.685535 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19472 35.57% 35.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11861 21.67% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5645 10.31% 67.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3680 6.72% 74.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2860 5.22% 79.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2018 3.69% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1694 3.09% 86.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1489 2.72% 89.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6018 10.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54737 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7040 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.631676 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.376134 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7037 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7040 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7040 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.244318 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.229045 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.737232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6278 89.18% 89.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 16 0.23% 89.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 578 8.21% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 145 2.06% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 15 0.21% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.03% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7017 # Writes before turning the bus around for reads -system.physmem.totQLat 1993187750 # Total ticks spent queuing -system.physmem.totMemAccLat 5117162750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11963.05 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7040 # Writes before turning the bus around for reads +system.physmem.totQLat 2004219750 # Total ticks spent queuing +system.physmem.totMemAccLat 5123769750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12046.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30713.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.53 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.19 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30796.33 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.84 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.72 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.35 # Data bus utilization in percentage -system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.36 # Data bus utilization in percentage +system.physmem.busUtilRead 1.40 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.13 # Average write queue length when enqueuing -system.physmem.readRowHits 144646 # Number of row buffer hits during reads -system.physmem.writeRowHits 81220 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing +system.physmem.readRowHits 144447 # Number of row buffer hits during reads +system.physmem.writeRowHits 81540 # Number of row buffer hits during writes system.physmem.readRowHitRate 86.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.22 # Row buffer hit rate for writes -system.physmem.avgGap 212819.93 # Average gap between requests -system.physmem.pageHitRate 80.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199621800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108920625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 642564000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367681680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3901163760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12761553015 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24642806250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42624311130 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.633365 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40844346250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1994460000 # Time in different power states +system.physmem.writeRowHitRate 71.29 # Row buffer hit rate for writes +system.physmem.avgGap 212205.23 # Average gap between requests +system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199372320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108784500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 641464200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 368938800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3890992560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12501731340 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24777284250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42488567970 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.220229 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 41071172000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1989260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16889792000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16512675000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214235280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116894250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 656728800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370960560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3901163760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13264546950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24201582750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42726112350 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.337777 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40104532750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1994460000 # Time in different power states +system.physmem_1.actEnergy 214189920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116869500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 655792800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371790000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3890992560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13114227690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24240006750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42603869220 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.155695 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40171909250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1989260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17629849250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17411703250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14669488 # Number of BP lookups -system.cpu.branchPred.condPredicted 9491497 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 392361 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10408467 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6389552 # Number of BTB hits +system.cpu.branchPred.lookups 14668515 # Number of BP lookups +system.cpu.branchPred.condPredicted 9490335 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 391198 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9984003 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6387554 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.388022 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1708748 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85394 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.977885 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708558 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85259 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20569996 # DTB read hits -system.cpu.dtb.read_misses 97344 # DTB read misses +system.cpu.dtb.read_hits 20570256 # DTB read hits +system.cpu.dtb.read_misses 97321 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20667340 # DTB read accesses -system.cpu.dtb.write_hits 14665866 # DTB write hits -system.cpu.dtb.write_misses 9405 # DTB write misses +system.cpu.dtb.read_accesses 20667577 # DTB read accesses +system.cpu.dtb.write_hits 14665734 # DTB write hits +system.cpu.dtb.write_misses 9406 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675271 # DTB write accesses -system.cpu.dtb.data_hits 35235862 # DTB hits -system.cpu.dtb.data_misses 106749 # DTB misses +system.cpu.dtb.write_accesses 14675140 # DTB write accesses +system.cpu.dtb.data_hits 35235990 # DTB hits +system.cpu.dtb.data_misses 106727 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35342611 # DTB accesses -system.cpu.itb.fetch_hits 25629903 # ITB hits -system.cpu.itb.fetch_misses 5247 # ITB misses +system.cpu.dtb.data_accesses 35342717 # DTB accesses +system.cpu.itb.fetch_hits 25623202 # ITB hits +system.cpu.itb.fetch_misses 5252 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25635150 # ITB accesses +system.cpu.itb.fetch_accesses 25628454 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,81 +322,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 119463118 # number of cpu cycles simulated +system.cpu.numCycles 119159228 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1109771 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1111760 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.350811 # CPI: cycles per instruction -system.cpu.ipc 0.740296 # IPC: instructions per cycle -system.cpu.tickCycles 91541167 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27921951 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200768 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.577182 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616116 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204864 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.971200 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 693853250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.577182 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993793 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993793 # Average percentage of cache occupancy +system.cpu.cpi 1.347375 # CPI: cycles per instruction +system.cpu.ipc 0.742184 # IPC: instructions per cycle +system.cpu.tickCycles 91522395 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27636833 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200775 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.716592 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616548 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204871 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.967536 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 688117500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.716592 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993827 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993827 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 679 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176158 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176158 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20282855 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20282855 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333261 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333261 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616116 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616116 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616116 # number of overall hits -system.cpu.dcache.overall_hits::total 34616116 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89415 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89415 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280116 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280116 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369531 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369531 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369531 # number of overall misses -system.cpu.dcache.overall_misses::total 369531 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4791422750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4791422750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21873540250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21873540250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26664963000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26664963000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26664963000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26664963000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372270 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372270 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70177059 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70177059 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20283298 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20283298 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333250 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333250 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34616548 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616548 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34616548 # number of overall hits +system.cpu.dcache.overall_hits::total 34616548 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89419 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89419 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280127 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280127 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369546 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369546 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369546 # number of overall misses +system.cpu.dcache.overall_misses::total 369546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4766015000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4766015000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21725113500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21725113500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26491128500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26491128500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26491128500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26491128500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372717 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372717 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34985647 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34985647 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34985647 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34985647 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34986094 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34986094 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34986094 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34986094 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53586.341777 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53586.341777 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78087.436098 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 78087.436098 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72158.933892 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72158.933892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72158.933892 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72158.933892 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53299.802055 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53299.802055 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77554.514559 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77554.514559 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71685.604769 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71685.604769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71685.604769 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71685.604769 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,32 +405,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168537 # number of writebacks -system.cpu.dcache.writebacks::total 168537 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136551 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136551 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164667 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164667 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61299 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61299 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143565 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143565 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204864 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204864 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204864 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204864 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2648121500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2648121500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10930365250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10930365250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13578486750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13578486750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13578486750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13578486750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168451 # number of writebacks +system.cpu.dcache.writebacks::total 168451 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28112 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136563 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136563 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164675 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164675 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164675 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164675 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61307 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61307 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143564 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143564 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204871 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204871 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204871 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204871 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2678080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2678080000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10985374000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10985374000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13663454000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13663454000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13663454000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13663454000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003009 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -438,68 +439,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43200.076673 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43200.076673 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76135.306307 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76135.306307 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66280.492180 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66280.492180 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66280.492180 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66280.492180 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43683.103071 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43683.103071 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76519.001978 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76519.001978 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66692.962889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66692.962889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66692.962889 # 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number of replacements +system.cpu.icache.tags.tagsinuse 1932.585595 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25467714 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155487 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.793205 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42332946500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.585595 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943645 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943645 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1043 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51414833 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51414833 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25474875 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25474875 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25474875 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25474875 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25474875 # number of overall hits -system.cpu.icache.overall_hits::total 25474875 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155028 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 155028 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 155028 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 155028 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 155028 # number of overall misses -system.cpu.icache.overall_misses::total 155028 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2574589242 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2574589242 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2574589242 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2574589242 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2574589242 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2574589242 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25629903 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25629903 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25629903 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25629903 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25629903 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25629903 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16607.253154 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16607.253154 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16607.253154 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16607.253154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16607.253154 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16607.253154 # average overall miss latency +system.cpu.icache.tags.tag_accesses 51401891 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51401891 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25467714 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25467714 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25467714 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25467714 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25467714 # number of overall hits +system.cpu.icache.overall_hits::total 25467714 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 155488 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 155488 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 155488 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 155488 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 155488 # number of overall misses +system.cpu.icache.overall_misses::total 155488 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2558679500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2558679500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2558679500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2558679500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2558679500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2558679500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25623202 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25623202 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25623202 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25623202 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25623202 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25623202 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006068 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.006068 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.006068 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.006068 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.006068 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.006068 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16455.800448 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16455.800448 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16455.800448 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16455.800448 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16455.800448 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16455.800448 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,123 +510,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155028 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155028 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155028 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155028 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155028 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155028 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2338939258 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2338939258 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2338939258 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2338939258 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2338939258 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2338939258 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006049 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006049 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006049 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15087.205266 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15087.205266 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15087.205266 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15087.205266 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15087.205266 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15087.205266 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155488 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 155488 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 155488 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 155488 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155488 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155488 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2403192500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2403192500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2403192500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2403192500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2403192500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2403192500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006068 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006068 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006068 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15455.806879 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15455.806879 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15455.806879 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15455.806879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15455.806879 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15455.806879 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2366.479179 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1894.410957 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.798357 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072219 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.057813 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.928389 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 25960.344438 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2481.956505 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1983.310560 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.792247 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075743 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 126 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4535770 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4535770 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 146958 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33627 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 180585 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168537 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168537 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12684 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12684 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 146958 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46311 # 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number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9327992500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9327992500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 541189000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 541189000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1955782000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1955782000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541189000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11283774500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11824963500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541189000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11283774500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11824963500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911657 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911657 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.050319 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451424 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451424 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.461709 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.461709 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71270.247246 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71270.247246 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69170.373211 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69170.373211 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70669.629630 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70669.629630 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69170.373211 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71165.413700 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71071.597718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69170.373211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71165.413700 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71071.597718 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 216326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 216325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168537 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143566 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143566 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 310055 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 888320 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9921728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23897664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33819392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 528429 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 216793 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 282835 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 203834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 155488 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61306 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464414 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610517 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1074931 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9951168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23892608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33843776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132455 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 847028 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.156376 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.363212 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 528429 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 714573 84.36% 84.36% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 132455 15.64% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 528429 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 432751500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 234095242 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 847028 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 525737500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 233232496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343202250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35740 # Transaction distribution -system.membus.trans_dist::ReadResp 35740 # Transaction distribution -system.membus.trans_dist::Writeback 114045 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 307309993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadResp 35498 # Transaction distribution +system.membus.trans_dist::Writeback 114384 # Transaction distribution +system.membus.trans_dist::CleanEvict 16134 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447289 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447289 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17962688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17962688 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 35498 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 463278 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17968896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17968896 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280667 # Request fanout histogram +system.membus.snoop_fanout::samples 296898 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280667 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 296898 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280667 # Request fanout histogram -system.membus.reqLayer0.occupancy 816993000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 296898 # Request fanout histogram +system.membus.reqLayer0.occupancy 824886500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 879772000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 878487500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 9afa0da2d..2061356b3 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022578 # Number of seconds simulated -sim_ticks 22578120000 # Number of ticks simulated -final_tick 22578120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022637 # Number of seconds simulated +sim_ticks 22637068500 # Number of ticks simulated +final_tick 22637068500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210348 # Simulator instruction rate (inst/s) -host_op_rate 210348 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59670380 # Simulator tick rate (ticks/s) -host_mem_usage 234940 # Number of bytes of host memory used -host_seconds 378.38 # Real time elapsed on the host +host_inst_rate 222882 # Simulator instruction rate (inst/s) +host_op_rate 222882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63391012 # Simulator tick rate (ticks/s) +host_mem_usage 306268 # Number of bytes of host memory used +host_seconds 357.10 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10151104 # Number of bytes read from this memory -system.physmem.bytes_read::total 10638720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7619 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158611 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166230 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21596838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449599169 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 471196007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21596838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21596838 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 323181558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 323181558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 323181558 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21596838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449599169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 794377566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166230 # Number of read requests accepted -system.physmem.writeReqs 114013 # Number of write requests accepted -system.physmem.readBursts 166230 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114013 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10638720 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7296832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 472384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153088 # Number of bytes read from this memory +system.physmem.bytes_read::total 10625472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 472384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 472384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7318784 # Number of bytes written to this memory +system.physmem.bytes_written::total 7318784 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7381 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158642 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166023 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114356 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114356 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20867720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 448516026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 469383746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20867720 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20867720 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 323309708 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 323309708 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 323309708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20867720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 448516026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 792693453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166023 # Number of read requests accepted +system.physmem.writeReqs 114356 # Number of write requests accepted +system.physmem.readBursts 166023 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114356 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10625216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 256 # Total number of bytes read from write queue +system.physmem.bytesWritten 7317504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10625472 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7318784 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 4 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10435 # Per bank write bursts -system.physmem.perBankRdBursts::1 10460 # Per bank write bursts -system.physmem.perBankRdBursts::2 10318 # Per bank write bursts +system.physmem.perBankRdBursts::0 10427 # Per bank write bursts +system.physmem.perBankRdBursts::1 10469 # Per bank write bursts +system.physmem.perBankRdBursts::2 10285 # Per bank write bursts system.physmem.perBankRdBursts::3 10058 # Per bank write bursts -system.physmem.perBankRdBursts::4 10413 # Per bank write bursts -system.physmem.perBankRdBursts::5 10396 # Per bank write bursts -system.physmem.perBankRdBursts::6 9837 # Per bank write bursts -system.physmem.perBankRdBursts::7 10308 # Per bank write bursts -system.physmem.perBankRdBursts::8 10587 # Per bank write bursts -system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10547 # Per bank write bursts -system.physmem.perBankRdBursts::11 10228 # Per bank write bursts -system.physmem.perBankRdBursts::12 10270 # Per bank write bursts -system.physmem.perBankRdBursts::13 10618 # Per bank write bursts -system.physmem.perBankRdBursts::14 10481 # Per bank write bursts -system.physmem.perBankRdBursts::15 10621 # Per bank write bursts -system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7259 # Per bank write bursts -system.physmem.perBankWrBursts::2 7255 # Per bank write bursts -system.physmem.perBankWrBursts::3 6997 # Per bank write bursts -system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7171 # Per bank write bursts -system.physmem.perBankWrBursts::6 6772 # Per bank write bursts -system.physmem.perBankWrBursts::7 7083 # Per bank write bursts -system.physmem.perBankWrBursts::8 7219 # Per bank write bursts -system.physmem.perBankWrBursts::9 6939 # Per bank write bursts -system.physmem.perBankWrBursts::10 7083 # Per bank write bursts -system.physmem.perBankWrBursts::11 6988 # Per bank write bursts -system.physmem.perBankWrBursts::12 6964 # Per bank write bursts -system.physmem.perBankWrBursts::13 7288 # Per bank write bursts -system.physmem.perBankWrBursts::14 7284 # Per bank write bursts -system.physmem.perBankWrBursts::15 7472 # Per bank write bursts +system.physmem.perBankRdBursts::4 10410 # Per bank write bursts +system.physmem.perBankRdBursts::5 10383 # Per bank write bursts +system.physmem.perBankRdBursts::6 9823 # Per bank write bursts +system.physmem.perBankRdBursts::7 10285 # Per bank write bursts +system.physmem.perBankRdBursts::8 10562 # Per bank write bursts +system.physmem.perBankRdBursts::9 10635 # Per bank write bursts +system.physmem.perBankRdBursts::10 10512 # Per bank write bursts +system.physmem.perBankRdBursts::11 10227 # Per bank write bursts +system.physmem.perBankRdBursts::12 10266 # Per bank write bursts +system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::14 10475 # Per bank write bursts +system.physmem.perBankRdBursts::15 10612 # Per bank write bursts +system.physmem.perBankWrBursts::0 7161 # Per bank write bursts +system.physmem.perBankWrBursts::1 7270 # Per bank write bursts +system.physmem.perBankWrBursts::2 7294 # Per bank write bursts +system.physmem.perBankWrBursts::3 6998 # Per bank write bursts +system.physmem.perBankWrBursts::4 7127 # Per bank write bursts +system.physmem.perBankWrBursts::5 7175 # Per bank write bursts +system.physmem.perBankWrBursts::6 6835 # Per bank write bursts +system.physmem.perBankWrBursts::7 7095 # Per bank write bursts +system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::9 6995 # Per bank write bursts +system.physmem.perBankWrBursts::10 7100 # Per bank write bursts +system.physmem.perBankWrBursts::11 6989 # Per bank write bursts +system.physmem.perBankWrBursts::12 6993 # Per bank write bursts +system.physmem.perBankWrBursts::13 7294 # Per bank write bursts +system.physmem.perBankWrBursts::14 7307 # Per bank write bursts +system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22578086500 # Total gap between requests +system.physmem.totGap 22637037500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166230 # Read request sizes (log2) +system.physmem.readPktSize::6 166023 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114013 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 52462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114356 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 52265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1941 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 195 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,121 +193,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52260 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.127440 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.641716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 343.309325 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18423 35.25% 35.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10477 20.05% 55.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5934 11.35% 66.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2978 5.70% 72.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2855 5.46% 77.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1509 2.89% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2072 3.96% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 924 1.77% 86.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7088 13.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52260 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6982 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.804927 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.249057 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6981 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52301 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.050573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.162039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.313279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18282 34.96% 34.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10576 20.22% 55.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5922 11.32% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2988 5.71% 72.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3062 5.85% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1483 2.84% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1989 3.80% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1021 1.95% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6978 13.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52301 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6994 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.736917 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.159441 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6991 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6982 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6982 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.325265 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.299310 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.979398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6150 88.08% 88.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 25 0.36% 88.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 468 6.70% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 181 2.59% 97.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 78 1.12% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.66% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 19 0.27% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.14% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 4 0.06% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6982 # Writes before turning the bus around for reads -system.physmem.totQLat 5742111500 # Total ticks spent queuing -system.physmem.totMemAccLat 8858755250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34545.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6994 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6994 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.347727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.319415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.025091 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6123 87.55% 87.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 26 0.37% 87.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 468 6.69% 94.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 194 2.77% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 92 1.32% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 55 0.79% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 18 0.26% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6994 # Writes before turning the bus around for reads +system.physmem.totQLat 5783499750 # Total ticks spent queuing +system.physmem.totMemAccLat 8896356000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 830095000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34836.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53295.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 471.17 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 323.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 471.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 323.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53586.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 469.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 323.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 469.38 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 323.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.21 # Data bus utilization in percentage -system.physmem.busUtilRead 3.68 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 146222 # Number of row buffer hits during reads -system.physmem.writeRowHits 81709 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.97 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.67 # Row buffer hit rate for writes -system.physmem.avgGap 80566.10 # Average gap between requests +system.physmem.busUtil 6.19 # Data bus utilization in percentage +system.physmem.busUtilRead 3.67 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.53 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 145949 # Number of row buffer hits during reads +system.physmem.writeRowHits 82096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes +system.physmem.avgGap 80737.28 # Average gap between requests system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190685880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 104044875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641035200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367584480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6555814245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7792863750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 17126343870 # Total energy per rank (pJ) -system.physmem_0.averagePower 758.721685 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12883309000 # Time in different power states -system.physmem_0.memoryStateTime::REF 753740000 # Time in different power states +system.physmem_0.actEnergy 190852200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 104135625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640543800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 368925840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1478383920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6748287570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7661408250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 17192537205 # Total energy per rank (pJ) +system.physmem_0.averagePower 759.557739 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12661521500 # Time in different power states +system.physmem_0.memoryStateTime::REF 755820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8935594000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9217738000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204104880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111366750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370701360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6889050495 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7500532500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 17204990625 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.206905 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12395641000 # Time in different power states -system.physmem_1.memoryStateTime::REF 753740000 # Time in different power states +system.physmem_1.actEnergy 204354360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111502875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654108000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371764080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1478383920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6845140260 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7576424250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17241677745 # Total energy per rank (pJ) +system.physmem_1.averagePower 761.730174 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12521267250 # Time in different power states +system.physmem_1.memoryStateTime::REF 755820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9423231500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9357815250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16619938 # Number of BP lookups -system.cpu.branchPred.condPredicted 10751763 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 361573 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10694449 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7373128 # Number of BTB hits +system.cpu.branchPred.lookups 16666171 # Number of BP lookups +system.cpu.branchPred.condPredicted 10777513 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 373740 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11097684 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7405754 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.943505 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1990233 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3119 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 66.732428 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1996658 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2898 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22587975 # DTB read hits -system.cpu.dtb.read_misses 226213 # DTB read misses -system.cpu.dtb.read_acv 17 # DTB read access violations -system.cpu.dtb.read_accesses 22814188 # DTB read accesses -system.cpu.dtb.write_hits 15866557 # DTB write hits -system.cpu.dtb.write_misses 44947 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15911504 # DTB write accesses -system.cpu.dtb.data_hits 38454532 # DTB hits -system.cpu.dtb.data_misses 271160 # DTB misses -system.cpu.dtb.data_acv 18 # DTB access violations -system.cpu.dtb.data_accesses 38725692 # DTB accesses -system.cpu.itb.fetch_hits 13913083 # ITB hits -system.cpu.itb.fetch_misses 32600 # ITB misses +system.cpu.dtb.read_hits 22620977 # DTB read hits +system.cpu.dtb.read_misses 226849 # DTB read misses +system.cpu.dtb.read_acv 27 # DTB read access violations +system.cpu.dtb.read_accesses 22847826 # DTB read accesses +system.cpu.dtb.write_hits 15870488 # DTB write hits +system.cpu.dtb.write_misses 45057 # DTB write misses +system.cpu.dtb.write_acv 4 # DTB write access violations +system.cpu.dtb.write_accesses 15915545 # DTB write accesses +system.cpu.dtb.data_hits 38491465 # DTB hits +system.cpu.dtb.data_misses 271906 # DTB misses +system.cpu.dtb.data_acv 31 # DTB access violations +system.cpu.dtb.data_accesses 38763371 # DTB accesses +system.cpu.itb.fetch_hits 13971550 # ITB hits +system.cpu.itb.fetch_misses 35700 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13945683 # ITB accesses +system.cpu.itb.fetch_accesses 14007250 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -321,101 +323,101 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 45156244 # number of cpu cycles simulated +system.cpu.numCycles 45274140 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15767330 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106100961 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16619938 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9363361 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27775290 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 962592 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 339291 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13913083 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 207051 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 44368516 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.391357 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.125574 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15840684 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106412182 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16666171 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9402412 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27820247 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 987192 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 787 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5202 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 343767 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13971550 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 209132 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 44504386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.391049 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.126296 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24640012 55.53% 55.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1537852 3.47% 59.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1401576 3.16% 62.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1522530 3.43% 65.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4244947 9.57% 75.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1845094 4.16% 79.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 677475 1.53% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1069981 2.41% 83.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7429049 16.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24724412 55.56% 55.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1545163 3.47% 59.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1406842 3.16% 62.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1520478 3.42% 65.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4242713 9.53% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1851895 4.16% 79.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 685374 1.54% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070742 2.41% 83.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7456767 16.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44368516 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.368054 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.349641 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15099347 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9823247 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18465046 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 597969 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 382907 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3741515 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100209 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104016227 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 314595 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 382907 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15487504 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6707215 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96849 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18654699 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3039342 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102867556 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4643 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 101006 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 348263 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2491758 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61906530 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124122948 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123794647 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 328300 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44504386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.368117 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.350397 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15190182 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9797968 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18517517 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 603822 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 394897 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3753615 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100898 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104278713 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 316536 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 394897 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15562376 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4515044 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96153 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18732590 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5203326 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103086111 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 6702 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 93508 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 341438 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4700364 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 62061981 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124384146 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124055114 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 329031 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9359649 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5745 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5793 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2522683 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23265731 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16453437 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1244012 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 539260 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91299347 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5639 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89055311 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 77552 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11713229 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4714239 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1056 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44368516 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.007174 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.246117 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9515100 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5718 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2349661 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23316234 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16465365 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1246740 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 545757 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91441079 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5553 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89167924 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 83024 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11854875 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4801848 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 970 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44504386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003576 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.243462 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17795444 40.11% 40.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5774110 13.01% 53.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5077311 11.44% 64.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4396727 9.91% 74.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4357066 9.82% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2650893 5.97% 90.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1948119 4.39% 94.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1385813 3.12% 97.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 983033 2.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17850579 40.11% 40.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5788896 13.01% 53.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5155949 11.59% 64.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4393297 9.87% 74.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4359248 9.80% 84.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2645472 5.94% 90.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1941559 4.36% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1381555 3.10% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 987831 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44368516 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44504386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 243204 9.64% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 244058 9.64% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available @@ -443,118 +445,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1172094 46.45% 56.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1108166 43.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1174802 46.40% 56.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1112961 43.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49651741 55.75% 55.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44157 0.05% 55.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121956 0.14% 55.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121436 0.14% 56.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39055 0.04% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23004684 25.83% 81.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16072139 18.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49705550 55.74% 55.74% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44198 0.05% 55.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121960 0.14% 55.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121539 0.14% 56.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39076 0.04% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23058691 25.86% 81.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16076765 18.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89055311 # Type of FU issued -system.cpu.iq.rate 1.972159 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2523465 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028336 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224465346 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102605449 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87163804 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 614809 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 433844 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 300747 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91271228 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 307548 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1661543 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89167924 # Type of FU issued +system.cpu.iq.rate 1.969511 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2531821 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028394 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224839378 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102887543 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87218101 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 615701 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 435266 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 300894 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91391726 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 308019 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1669932 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2989093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6317 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21548 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1840060 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3039596 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21688 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1851988 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3023 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 186080 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3150 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 205518 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 382907 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1413856 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4974138 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100829471 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 151929 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23265731 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16453437 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5565 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4957861 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21548 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 151078 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 158072 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 309150 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88275465 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22814985 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 779846 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 394897 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1352665 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2733681 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100982224 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 167502 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23316234 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16465365 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5553 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3853 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2732159 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21688 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 162395 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 158558 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 320953 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88354535 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22848688 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 813389 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9524485 # number of nop insts executed -system.cpu.iew.exec_refs 38726852 # number of memory reference insts executed -system.cpu.iew.exec_branches 15171568 # Number of branches executed -system.cpu.iew.exec_stores 15911867 # Number of stores executed -system.cpu.iew.exec_rate 1.954889 # Inst execution rate -system.cpu.iew.wb_sent 87882002 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87464551 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33900833 # num instructions producing a value -system.cpu.iew.wb_consumers 44342613 # num instructions consuming a value +system.cpu.iew.exec_nop 9535592 # number of nop insts executed +system.cpu.iew.exec_refs 38764588 # number of memory reference insts executed +system.cpu.iew.exec_branches 15181336 # Number of branches executed +system.cpu.iew.exec_stores 15915900 # Number of stores executed +system.cpu.iew.exec_rate 1.951545 # Inst execution rate +system.cpu.iew.wb_sent 87941007 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87518995 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33890392 # num instructions producing a value +system.cpu.iew.wb_consumers 44346264 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.936931 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764520 # average fanout of values written-back +system.cpu.iew.wb_rate 1.933090 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764222 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9282281 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9432406 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 263184 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43000551 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.054408 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.876009 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 275041 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43112835 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.049057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.870632 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21467431 49.92% 49.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6329802 14.72% 64.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2918642 6.79% 71.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1760390 4.09% 75.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1670777 3.89% 79.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1138707 2.65% 82.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1203989 2.80% 84.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 794665 1.85% 86.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5716148 13.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21537439 49.96% 49.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6339258 14.70% 64.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2938097 6.81% 71.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1767481 4.10% 75.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1703049 3.95% 79.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1136594 2.64% 82.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1201073 2.79% 84.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 797579 1.85% 86.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5692265 13.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43000551 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43112835 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -600,343 +602,349 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5716148 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 133590014 # The number of ROB reads -system.cpu.rob.rob_writes 196617452 # The number of ROB writes -system.cpu.timesIdled 47547 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 787728 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5692265 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 133876306 # The number of ROB reads +system.cpu.rob.rob_writes 196941310 # The number of ROB writes +system.cpu.timesIdled 47582 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 769754 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.567348 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.567348 # CPI: Total CPI of All Threads -system.cpu.ipc 1.762586 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.762586 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116851082 # number of integer regfile reads -system.cpu.int_regfile_writes 57926468 # number of integer regfile writes -system.cpu.fp_regfile_reads 255690 # number of floating regfile reads -system.cpu.fp_regfile_writes 241313 # number of floating regfile writes -system.cpu.misc_regfile_reads 38160 # number of misc regfile reads +system.cpu.cpi 0.568830 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.568830 # CPI: Total CPI of All Threads +system.cpu.ipc 1.757996 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.757996 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116950893 # number of integer regfile reads +system.cpu.int_regfile_writes 57974920 # number of integer regfile writes +system.cpu.fp_regfile_reads 255771 # number of floating regfile reads +system.cpu.fp_regfile_writes 241359 # number of floating regfile writes +system.cpu.misc_regfile_reads 38164 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.706489 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34086491 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.904910 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 231989000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.706489 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201397 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.850359 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34098493 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205493 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.935059 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 231077500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.850359 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993860 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993860 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2590 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2777 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1229 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71020044 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71020044 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20525035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20525035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561393 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561393 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34086428 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34086428 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34086428 # number of overall hits -system.cpu.dcache.overall_hits::total 34086428 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268817 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268817 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1051984 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1051984 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 71045365 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71045365 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20537317 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20537317 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561115 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561115 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34098432 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34098432 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34098432 # number of overall hits +system.cpu.dcache.overall_hits::total 34098432 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 269180 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 269180 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052262 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052262 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1320801 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1320801 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1320801 # number of overall misses -system.cpu.dcache.overall_misses::total 1320801 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17503667749 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17503667749 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89467046923 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89467046923 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 99750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106970714672 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106970714672 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106970714672 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106970714672 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20793852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20793852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1321442 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321442 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321442 # number of overall misses +system.cpu.dcache.overall_misses::total 1321442 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17386725500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17386725500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89260696666 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89260696666 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106647422166 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106647422166 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106647422166 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106647422166 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20806497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20806497 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 64 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 64 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35407229 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35407229 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35407229 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35407229 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012928 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012928 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071988 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071988 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015625 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015625 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037303 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037303 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65113.693513 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65113.693513 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85046.014885 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85046.014885 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80989.274442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80989.274442 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6831456 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35419874 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35419874 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35419874 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35419874 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012937 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012937 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072007 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.072007 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016129 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016129 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037308 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037308 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037308 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037308 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64591.446244 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64591.446244 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84827.444749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84827.444749 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80705.337174 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80705.337174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80705.337174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80705.337174 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6894813 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88055 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 88842 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.581693 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.607584 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168921 # number of writebacks -system.cpu.dcache.writebacks::total 168921 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206754 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206754 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908590 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908590 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115344 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115344 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115344 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115344 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62063 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62063 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168840 # number of writebacks +system.cpu.dcache.writebacks::total 168840 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207085 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 207085 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908865 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908865 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115950 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115950 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115950 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115950 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62095 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62095 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143397 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143397 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205457 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205457 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205457 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205457 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3191920501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3191920501 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14187677704 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14187677704 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 97750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 97750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17379598205 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17379598205 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17379598205 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17379598205 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002985 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002985 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 205492 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205492 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205492 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205492 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3215385000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3215385000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14267732202 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14267732202 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483117202 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17483117202 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17483117202 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17483117202 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002984 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002984 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.015625 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005803 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005803 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51430.328875 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51430.328875 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98941.920192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98941.920192 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 97750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 97750 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84589.954127 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84589.954127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84589.954127 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84589.954127 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.016129 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.016129 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005802 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005802 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005802 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005802 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51781.705451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51781.705451 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99498.122011 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99498.122011 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85079.308207 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 85079.308207 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85079.308207 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 85079.308207 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 92948 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.254210 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13805160 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 94996 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 145.323593 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19026930250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1916.254210 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935671 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935671 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 93160 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.318628 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13863089 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 95208 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 145.608447 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19085068500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.318628 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935702 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935702 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 379 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1486 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 371 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27921160 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27921160 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13805160 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13805160 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13805160 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13805160 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13805160 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2071977734 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13913082 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13913082 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13913082 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13913082 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13913082 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13913082 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007757 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007757 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007757 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007757 # 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number of cycles access was blocked @@ -945,105 +953,116 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114013 # number of writebacks -system.cpu.l2cache.writebacks::total 114013 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7620 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35450 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 114356 # number of writebacks +system.cpu.l2cache.writebacks::total 114356 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2054 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 2054 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15087792000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15616602000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912020 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912020 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077535 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448676 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448676 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772007 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.552121 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772007 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.552121 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96407.417744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96407.417744 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71635.058250 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71635.058250 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88996.572269 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88996.572269 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71635.058250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95105.911423 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94062.316292 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71635.058250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95105.911423 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94062.316292 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 157060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157059 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168921 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189993 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 769830 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6079744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23960256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30040000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 469376 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 157304 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 283196 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 143468 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 95209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 62096 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 283577 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612383 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 895960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6093312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23957312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30050624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132107 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 727366 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.181624 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.385534 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 469376 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 595259 81.84% 81.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 132107 18.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 469376 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 403609000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 143899236 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 727366 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 466469500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 142819485 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 325469999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308243991 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35449 # Transaction distribution -system.membus.trans_dist::ReadResp 35449 # Transaction distribution -system.membus.trans_dist::Writeback 114013 # Transaction distribution +system.membus.trans_dist::ReadResp 35242 # Transaction distribution +system.membus.trans_dist::Writeback 114356 # Transaction distribution +system.membus.trans_dist::CleanEvict 15775 # Transaction distribution system.membus.trans_dist::ReadExReq 130781 # Transaction distribution system.membus.trans_dist::ReadExResp 130781 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446473 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446473 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17935552 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 35242 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462177 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462177 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17944256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17944256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280243 # Request fanout histogram +system.membus.snoop_fanout::samples 296154 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280243 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 296154 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280243 # Request fanout histogram -system.membus.reqLayer0.occupancy 786749500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 865056500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 296154 # Request fanout histogram +system.membus.reqLayer0.occupancy 778878000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 857917500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c3c27d986..a8d113a77 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057148 # Number of seconds simulated -sim_ticks 57147901500 # Number of ticks simulated -final_tick 57147901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.057054 # Number of seconds simulated +sim_ticks 57053790500 # Number of ticks simulated +final_tick 57053790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198372 # Simulator instruction rate (inst/s) -host_op_rate 253689 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 159860838 # Simulator tick rate (ticks/s) -host_mem_usage 323444 # Number of bytes of host memory used -host_seconds 357.49 # Real time elapsed on the host +host_inst_rate 195523 # Simulator instruction rate (inst/s) +host_op_rate 250045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157305109 # Simulator tick rate (ticks/s) +host_mem_usage 323528 # Number of bytes of host memory used +host_seconds 362.70 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923136 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123799 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5672299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138642641 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144314940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5672299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5672299 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 94015701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 94015701 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 94015701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5672299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138642641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 238330641 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128864 # Number of read requests accepted -system.physmem.writeReqs 83950 # Number of write requests accepted -system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 83950 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM +system.physmem.bytes_read::cpu.inst 319296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7924224 # Number of bytes read from this memory +system.physmem.bytes_read::total 8243520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 319296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 319296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5514240 # Number of bytes written to this memory +system.physmem.bytes_written::total 5514240 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123816 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86160 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86160 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5596403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138890404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144486807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5596403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5596403 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96649845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96649845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96649845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5596403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138890404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241136652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128805 # Number of read requests accepted +system.physmem.writeReqs 86160 # Number of write requests accepted +system.physmem.readBursts 128805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86160 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8243200 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5372800 # Total written bytes from the system interface side +system.physmem.bytesWritten 5512512 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8243520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5514240 # Total written bytes from the system interface side system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8158 # Per bank write bursts +system.physmem.perBankRdBursts::0 8145 # Per bank write bursts system.physmem.perBankRdBursts::1 8375 # Per bank write bursts -system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::2 8247 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts -system.physmem.perBankRdBursts::4 8317 # Per bank write bursts -system.physmem.perBankRdBursts::5 8450 # Per bank write bursts -system.physmem.perBankRdBursts::6 8089 # Per bank write bursts -system.physmem.perBankRdBursts::7 7970 # Per bank write bursts -system.physmem.perBankRdBursts::8 8070 # Per bank write bursts -system.physmem.perBankRdBursts::9 7639 # Per bank write bursts -system.physmem.perBankRdBursts::10 7818 # Per bank write bursts -system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::4 8318 # Per bank write bursts +system.physmem.perBankRdBursts::5 8434 # Per bank write bursts +system.physmem.perBankRdBursts::6 8084 # Per bank write bursts +system.physmem.perBankRdBursts::7 7957 # Per bank write bursts +system.physmem.perBankRdBursts::8 8058 # Per bank write bursts +system.physmem.perBankRdBursts::9 7633 # Per bank write bursts +system.physmem.perBankRdBursts::10 7816 # Per bank write bursts +system.physmem.perBankRdBursts::11 7829 # Per bank write bursts system.physmem.perBankRdBursts::12 7882 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts -system.physmem.perBankRdBursts::14 7978 # Per bank write bursts -system.physmem.perBankRdBursts::15 8005 # Per bank write bursts -system.physmem.perBankWrBursts::0 5181 # Per bank write bursts -system.physmem.perBankWrBursts::1 5374 # Per bank write bursts -system.physmem.perBankWrBursts::2 5285 # Per bank write bursts -system.physmem.perBankWrBursts::3 5155 # Per bank write bursts -system.physmem.perBankWrBursts::4 5266 # Per bank write bursts -system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5197 # Per bank write bursts -system.physmem.perBankWrBursts::7 5049 # Per bank write bursts -system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5087 # Per bank write bursts -system.physmem.perBankWrBursts::10 5251 # Per bank write bursts -system.physmem.perBankWrBursts::11 5143 # Per bank write bursts -system.physmem.perBankWrBursts::12 5343 # Per bank write bursts -system.physmem.perBankWrBursts::13 5363 # Per bank write bursts -system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5224 # Per bank write bursts +system.physmem.perBankRdBursts::14 7977 # Per bank write bursts +system.physmem.perBankRdBursts::15 7996 # Per bank write bursts +system.physmem.perBankWrBursts::0 5393 # Per bank write bursts +system.physmem.perBankWrBursts::1 5541 # Per bank write bursts +system.physmem.perBankWrBursts::2 5463 # Per bank write bursts +system.physmem.perBankWrBursts::3 5328 # Per bank write bursts +system.physmem.perBankWrBursts::4 5352 # Per bank write bursts +system.physmem.perBankWrBursts::5 5550 # Per bank write bursts +system.physmem.perBankWrBursts::6 5247 # Per bank write bursts +system.physmem.perBankWrBursts::7 5180 # Per bank write bursts +system.physmem.perBankWrBursts::8 5155 # Per bank write bursts +system.physmem.perBankWrBursts::9 5102 # Per bank write bursts +system.physmem.perBankWrBursts::10 5289 # Per bank write bursts +system.physmem.perBankWrBursts::11 5270 # Per bank write bursts +system.physmem.perBankWrBursts::12 5531 # Per bank write bursts +system.physmem.perBankWrBursts::13 5597 # Per bank write bursts +system.physmem.perBankWrBursts::14 5703 # Per bank write bursts +system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57147867000 # Total gap between requests +system.physmem.totGap 57053759500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128864 # Read request sizes (log2) +system.physmem.readPktSize::6 128805 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 83950 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86160 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12216 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,98 +193,97 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38410 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.471023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.710692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.512328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12078 31.44% 31.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8121 21.14% 52.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4196 10.92% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2833 7.38% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2487 6.47% 77.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1687 4.39% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1308 3.41% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1147 2.99% 88.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4553 11.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38410 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.969750 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.703721 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5155 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38707 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.314336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.053807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.949103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12175 31.45% 31.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8182 21.14% 52.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4142 10.70% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2786 7.20% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2727 7.05% 77.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1625 4.20% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1301 3.36% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1172 3.03% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4597 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38707 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.311061 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 351.967739 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5296 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.272833 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256213 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.766988 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4532 87.88% 87.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 8 0.16% 88.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 487 9.44% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 109 2.11% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 13 0.25% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.08% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 1657207000 # Total ticks spent queuing -system.physmem.totMemAccLat 4073313250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12860.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.259581 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.243681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.749380 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4690 88.54% 88.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 4 0.08% 88.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 472 8.91% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 18 0.34% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads +system.physmem.totQLat 1693807750 # Total ticks spent queuing +system.physmem.totMemAccLat 4108807750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644000000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13150.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31610.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 93.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 94.02 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31900.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.62 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.65 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.86 # Data bus utilization in percentage +system.physmem.busUtil 1.88 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing -system.physmem.readRowHits 112198 # Number of row buffer hits during reads -system.physmem.writeRowHits 62160 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.04 # Row buffer hit rate for writes -system.physmem.avgGap 268534.34 # Average gap between requests -system.physmem.pageHitRate 81.93 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 150580080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82161750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512592600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11751586830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 23977725000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40479283620 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.378781 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39762160500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1908140000 # Time in different power states +system.physmem.avgWrQLen 23.52 # Average write queue length when enqueuing +system.physmem.readRowHits 112096 # Number of row buffer hits during reads +system.physmem.writeRowHits 64121 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.42 # Row buffer hit rate for writes +system.physmem.avgGap 265409.53 # Average gap between requests +system.physmem.pageHitRate 81.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 151956000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82912500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512405400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 278951040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3726219120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11612859660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24043349250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40408652970 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.301006 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39871864500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1905020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15473270000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15273243000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139769280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76263000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492016200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271479600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3732321840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11244014370 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24422958750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40378823040 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.620851 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40500942500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1908140000 # Time in different power states +system.physmem_1.actEnergy 140638680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76737375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491797800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 279151920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3726219120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11026970910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24557286750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40298802555 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.375499 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40728832250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1905020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14734649500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14416275250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14823153 # Number of BP lookups -system.cpu.branchPred.condPredicted 9921447 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 393425 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9508830 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6745421 # Number of BTB hits +system.cpu.branchPred.lookups 14816555 # Number of BP lookups +system.cpu.branchPred.condPredicted 9915062 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 392110 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9527196 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6742365 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.938496 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1716328 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.769668 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1716488 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -404,97 +403,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 114295803 # number of cpu cycles simulated +system.cpu.numCycles 114107581 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1165738 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1163698 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.611727 # CPI: cycles per instruction -system.cpu.ipc 0.620453 # IPC: instructions per cycle -system.cpu.tickCycles 95732462 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18563341 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156421 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.059654 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42628242 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160517 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.568395 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 829804250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.059654 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992934 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992934 # Average percentage of cache occupancy +system.cpu.cpi 1.609072 # CPI: cycles per instruction +system.cpu.ipc 0.621476 # IPC: instructions per cycle +system.cpu.tickCycles 95702284 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18405297 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156420 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.153595 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42625103 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160516 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.550493 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 823362500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.153595 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2909 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1109 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86023319 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86023319 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22869697 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22869697 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642191 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642191 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 84516 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 84516 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86018450 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86018450 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22867482 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22867482 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642183 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642183 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83600 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83600 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42511888 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42511888 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42596404 # number of overall hits -system.cpu.dcache.overall_hits::total 42596404 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51738 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51738 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207710 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 43711 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 43711 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259448 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259448 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 303159 # number of overall misses -system.cpu.dcache.overall_misses::total 303159 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1479377187 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1479377187 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16921529000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16921529000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18400906187 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18400906187 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18400906187 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18400906187 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22921435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22921435 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42509665 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42509665 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42593265 # number of overall hits +system.cpu.dcache.overall_hits::total 42593265 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51591 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51591 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207718 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207718 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44555 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44555 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259309 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259309 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303864 # number of overall misses +system.cpu.dcache.overall_misses::total 303864 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1486882500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1486882500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16821632500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16821632500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18308515000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18308515000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18308515000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18308515000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22919073 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22919073 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128227 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128227 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128155 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128155 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42771336 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42771336 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42899563 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42899563 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002257 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002257 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42768974 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42768974 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42897129 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42897129 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002251 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002251 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340888 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.340888 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007067 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007067 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28593.629189 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28593.629189 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81467.088729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81467.088729 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70923.291708 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70923.291708 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60697.212311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60697.212311 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.347665 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.347665 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006063 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006063 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28820.579171 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28820.579171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80983.027470 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80983.027470 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70605.011781 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70605.011781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60252.333281 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60252.333281 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,110 +502,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128425 # number of writebacks -system.cpu.dcache.writebacks::total 128425 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22255 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22255 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100680 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100680 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122935 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122935 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122935 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122935 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29483 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29483 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 24004 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 24004 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136513 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136513 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160517 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160517 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 559151063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 559151063 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8446390250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8446390250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1684744250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1684744250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9005541313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9005541313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10690285563 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10690285563 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001286 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001286 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128380 # number of writebacks +system.cpu.dcache.writebacks::total 128380 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22097 # 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number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23994 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136522 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136522 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160516 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160516 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 572555000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 572555000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8494060500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8494060500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1717129000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1717129000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9066615500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10783744500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10783744500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187199 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187199 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187226 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187226 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18965.202422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18965.202422 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78916.100626 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78916.100626 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70185.979420 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70185.979420 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65968.378931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65968.378931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66599.086471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66599.086471 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.592392 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.592392 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79362.975109 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79362.975109 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71564.932900 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71564.932900 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66411.387908 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66411.387908 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67181.742007 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67181.742007 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42924 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.595671 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24987535 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 555.698417 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42980 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.974873 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24976744 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 45022 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 554.767536 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.595671 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904588 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904588 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.974873 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904773 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904773 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 914 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1007 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50109970 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50109970 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24987535 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20644.603869 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20644.603869 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20644.603869 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,123 +614,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44967 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44967 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,114 +745,126 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83950 # number of writebacks -system.cpu.l2cache.writebacks::total 83950 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 63 # number of demand (read+write) MSHR hits +system.cpu.l2cache.writebacks::writebacks 86160 # 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number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5066 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 26587 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102278 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102278 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5066 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123799 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128865 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5066 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123799 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128865 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342787750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1580541000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923328750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7010820250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7010820250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342787750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8591361250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8934149000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342787750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8591361250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8934149000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402359 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270045 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955601 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627129 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.112660 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771252 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627129 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67664.380182 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73441.801032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72340.946703 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68546.708481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68546.708481 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67664.380182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69397.662744 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69329.523144 # average overall mshr miss latency +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1376 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1376 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4990 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4990 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21535 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21535 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4990 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123816 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128806 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4990 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123816 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128806 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7260824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7260824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 346082000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 346082000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1654286500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1654286500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 346082000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8915110500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9261192500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 346082000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8915110500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9261192500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955647 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955647 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110832 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402614 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402614 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771362 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.626674 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771362 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.626674 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70988.981336 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70988.981336 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69355.110220 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69355.110220 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76818.504760 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76818.504760 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69355.110220 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72002.895425 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71900.319085 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69355.110220 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72002.895425 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71900.319085 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98453 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89933 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 539392 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2877824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21370112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333909 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 98510 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 214540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 72719 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45023 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53488 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129456 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473213 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 602669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2881408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18489344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21370752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 95667 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 500606 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.191102 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.393170 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 333909 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 404939 80.89% 80.89% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 95667 19.11% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333909 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295379500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68407488 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 500606 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 330849500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 67538489 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268248937 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 26586 # Transaction distribution -system.membus.trans_dist::ReadResp 26586 # Transaction distribution -system.membus.trans_dist::Writeback 83950 # Transaction distribution -system.membus.trans_dist::ReadExReq 102278 # Transaction distribution -system.membus.trans_dist::ReadExResp 102278 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341678 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341678 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 240805936 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadResp 26524 # Transaction distribution +system.membus.trans_dist::Writeback 86160 # Transaction distribution +system.membus.trans_dist::CleanEvict 7518 # Transaction distribution +system.membus.trans_dist::ReadExReq 102281 # Transaction distribution +system.membus.trans_dist::ReadExResp 102281 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26524 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 351288 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13757760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13757760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212814 # Request fanout histogram +system.membus.snoop_fanout::samples 222483 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212814 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222483 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212814 # Request fanout histogram -system.membus.reqLayer0.occupancy 578378500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222483 # Request fanout histogram +system.membus.reqLayer0.occupancy 591579500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 680081000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 679724750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 3b7597919..54ac67971 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033331 # Number of seconds simulated -sim_ticks 33330913000 # Number of ticks simulated -final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033295 # Number of seconds simulated +sim_ticks 33294994000 # Number of ticks simulated +final_tick 33294994000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123947 # Simulator instruction rate (inst/s) -host_op_rate 158514 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58262578 # Simulator tick rate (ticks/s) -host_mem_usage 323704 # Number of bytes of host memory used -host_seconds 572.08 # Real time elapsed on the host +host_inst_rate 125667 # Simulator instruction rate (inst/s) +host_op_rate 160714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59007684 # Simulator tick rate (ticks/s) +host_mem_usage 325068 # Number of bytes of host memory used +host_seconds 564.25 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 583488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2505024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6203200 # Number of bytes read from this memory -system.physmem.bytes_read::total 9291712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 583488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 583488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6256128 # Number of bytes written to this memory -system.physmem.bytes_written::total 6256128 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9117 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96925 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145183 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97752 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97752 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17505911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75156177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 186109513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 278771602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17505911 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17505911 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 187697469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 187697469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 187697469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17505911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75156177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 186109513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 466469070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145183 # Number of read requests accepted -system.physmem.writeReqs 97752 # Number of write requests accepted -system.physmem.readBursts 145183 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97752 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9284992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue -system.physmem.bytesWritten 6254720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9291712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6256128 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 579648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2508288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6196352 # Number of bytes read from this memory +system.physmem.bytes_read::total 9284288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 579648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 579648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6263808 # Number of bytes written to this memory +system.physmem.bytes_written::total 6263808 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9057 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39192 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96818 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145067 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97872 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97872 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17409464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75335289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 186104614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 278849367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17409464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17409464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 188130624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 188130624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 188130624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17409464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75335289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 186104614 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 466979991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145067 # Number of read requests accepted +system.physmem.writeReqs 97872 # Number of write requests accepted +system.physmem.readBursts 145067 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97872 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9276928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 6262080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9284288 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6263808 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9145 # Per bank write bursts -system.physmem.perBankRdBursts::1 9372 # Per bank write bursts -system.physmem.perBankRdBursts::2 9233 # Per bank write bursts -system.physmem.perBankRdBursts::3 9500 # Per bank write bursts -system.physmem.perBankRdBursts::4 9743 # Per bank write bursts -system.physmem.perBankRdBursts::5 9700 # Per bank write bursts -system.physmem.perBankRdBursts::6 9083 # Per bank write bursts -system.physmem.perBankRdBursts::7 8995 # Per bank write bursts -system.physmem.perBankRdBursts::8 9233 # Per bank write bursts -system.physmem.perBankRdBursts::9 8567 # Per bank write bursts -system.physmem.perBankRdBursts::10 8856 # Per bank write bursts -system.physmem.perBankRdBursts::11 8704 # Per bank write bursts -system.physmem.perBankRdBursts::12 8629 # Per bank write bursts -system.physmem.perBankRdBursts::13 8694 # Per bank write bursts -system.physmem.perBankRdBursts::14 8697 # Per bank write bursts -system.physmem.perBankRdBursts::15 8927 # Per bank write bursts -system.physmem.perBankWrBursts::0 5993 # Per bank write bursts -system.physmem.perBankWrBursts::1 6233 # Per bank write bursts -system.physmem.perBankWrBursts::2 6131 # Per bank write bursts -system.physmem.perBankWrBursts::3 6188 # Per bank write bursts -system.physmem.perBankWrBursts::4 6147 # Per bank write bursts -system.physmem.perBankWrBursts::5 6290 # Per bank write bursts -system.physmem.perBankWrBursts::6 6056 # Per bank write bursts -system.physmem.perBankWrBursts::7 6014 # Per bank write bursts -system.physmem.perBankWrBursts::8 6000 # Per bank write bursts -system.physmem.perBankWrBursts::9 6152 # Per bank write bursts -system.physmem.perBankWrBursts::10 6228 # Per bank write bursts -system.physmem.perBankWrBursts::11 5920 # Per bank write bursts -system.physmem.perBankWrBursts::12 6078 # Per bank write bursts -system.physmem.perBankWrBursts::13 6086 # Per bank write bursts -system.physmem.perBankWrBursts::14 6193 # Per bank write bursts -system.physmem.perBankWrBursts::15 6021 # Per bank write bursts +system.physmem.perBankRdBursts::0 9133 # Per bank write bursts +system.physmem.perBankRdBursts::1 9402 # Per bank write bursts +system.physmem.perBankRdBursts::2 9189 # Per bank write bursts +system.physmem.perBankRdBursts::3 9501 # Per bank write bursts +system.physmem.perBankRdBursts::4 9688 # Per bank write bursts +system.physmem.perBankRdBursts::5 9749 # Per bank write bursts +system.physmem.perBankRdBursts::6 9050 # Per bank write bursts +system.physmem.perBankRdBursts::7 9017 # Per bank write bursts +system.physmem.perBankRdBursts::8 9142 # Per bank write bursts +system.physmem.perBankRdBursts::9 8554 # Per bank write bursts +system.physmem.perBankRdBursts::10 8859 # Per bank write bursts +system.physmem.perBankRdBursts::11 8689 # Per bank write bursts +system.physmem.perBankRdBursts::12 8621 # Per bank write bursts +system.physmem.perBankRdBursts::13 8707 # Per bank write bursts +system.physmem.perBankRdBursts::14 8654 # Per bank write bursts +system.physmem.perBankRdBursts::15 8997 # Per bank write bursts +system.physmem.perBankWrBursts::0 5994 # Per bank write bursts +system.physmem.perBankWrBursts::1 6239 # Per bank write bursts +system.physmem.perBankWrBursts::2 6113 # Per bank write bursts +system.physmem.perBankWrBursts::3 6223 # Per bank write bursts +system.physmem.perBankWrBursts::4 6099 # Per bank write bursts +system.physmem.perBankWrBursts::5 6360 # Per bank write bursts +system.physmem.perBankWrBursts::6 6100 # Per bank write bursts +system.physmem.perBankWrBursts::7 5988 # Per bank write bursts +system.physmem.perBankWrBursts::8 5999 # Per bank write bursts +system.physmem.perBankWrBursts::9 6164 # Per bank write bursts +system.physmem.perBankWrBursts::10 6223 # Per bank write bursts +system.physmem.perBankWrBursts::11 5911 # Per bank write bursts +system.physmem.perBankWrBursts::12 6098 # Per bank write bursts +system.physmem.perBankWrBursts::13 6094 # Per bank write bursts +system.physmem.perBankWrBursts::14 6156 # Per bank write bursts +system.physmem.perBankWrBursts::15 6084 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33330641500 # Total gap between requests +system.physmem.totGap 33294791000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145183 # Read request sizes (log2) +system.physmem.readPktSize::6 145067 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97752 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 41867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 51877 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6097 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97872 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 42425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 52688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6069 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 5279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4636 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4301 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 3567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,101 +197,102 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88649 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.273178 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.551570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.030923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52157 58.84% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22538 25.42% 84.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4461 5.03% 89.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1758 1.98% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1068 1.20% 92.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 785 0.89% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 713 0.80% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 748 0.84% 95.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4421 4.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88649 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.566130 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.054973 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 187.117675 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5904 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88605 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.366717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.599846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 238.987527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52022 58.71% 58.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22627 25.54% 84.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4475 5.05% 89.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1626 1.84% 91.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1127 1.27% 92.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 853 0.96% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 741 0.84% 94.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 771 0.87% 95.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4363 4.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88605 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.519032 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.016952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 186.911555 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.550381 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.508750 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.243905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4712 79.80% 79.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 29 0.49% 80.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 757 12.82% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 163 2.76% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 111 1.88% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 62 1.05% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 43 0.73% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.34% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.10% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads -system.physmem.totQLat 7425181339 # Total ticks spent queuing -system.physmem.totMemAccLat 10145393839 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 725390000 # Total ticks spent in databus transfers -system.physmem.avgQLat 51180.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.553037 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.510340 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.264183 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4718 79.82% 79.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.51% 80.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 754 12.76% 93.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 178 3.01% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 93 1.57% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 63 1.07% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 39 0.66% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.30% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.22% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads +system.physmem.totQLat 7210112096 # Total ticks spent queuing +system.physmem.totMemAccLat 9927962096 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 724760000 # Total ticks spent in databus transfers +system.physmem.avgQLat 49741.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 69930.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 278.57 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 187.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 278.77 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 187.70 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 68491.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 278.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 188.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 278.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 188.13 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.64 # Data bus utilization in percentage +system.physmem.busUtil 3.65 # Data bus utilization in percentage system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing -system.physmem.readRowHits 117819 # Number of row buffer hits during reads -system.physmem.writeRowHits 36329 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 37.16 # Row buffer hit rate for writes -system.physmem.avgGap 137199.83 # Average gap between requests -system.physmem.pageHitRate 63.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342679680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186978000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 582769200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 317714400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2176636800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11943657450 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9518358000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25068793530 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.242445 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15735797307 # Time in different power states -system.physmem_0.memoryStateTime::REF 1112800000 # Time in different power states +system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing +system.physmem.readRowHits 117862 # Number of row buffer hits during reads +system.physmem.writeRowHits 36326 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 37.12 # Row buffer hit rate for writes +system.physmem.avgGap 137050.00 # Average gap between requests +system.physmem.pageHitRate 63.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341636400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186408750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 582823800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 318271680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2174602560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11786161320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9637821000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25027725510 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.712810 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15936534744 # Time in different power states +system.physmem_0.memoryStateTime::REF 1111760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16476833443 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16245984006 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 327053160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178451625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 548121600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315264960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2176636800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11265215805 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10113486000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24924229950 # Total energy per rank (pJ) -system.physmem_1.averagePower 747.904367 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16730540892 # Time in different power states -system.physmem_1.memoryStateTime::REF 1112800000 # Time in different power states +system.physmem_1.actEnergy 328217400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179086875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 547723800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315763920 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2174602560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11208088125 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 10144902750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24898385430 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.828055 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16783464024 # Time in different power states +system.physmem_1.memoryStateTime::REF 1111760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15482244108 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15399360476 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17205793 # Number of BP lookups -system.cpu.branchPred.condPredicted 11516695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648305 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9352037 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7676056 # Number of BTB hits +system.cpu.branchPred.lookups 17206050 # Number of BP lookups +system.cpu.branchPred.condPredicted 11517760 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648066 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9347785 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7673761 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.078974 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1873350 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101557 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.091758 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1873139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -410,95 +411,95 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66661827 # number of cpu cycles simulated +system.cpu.numCycles 66589989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4979954 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88191186 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17205793 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9549406 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60159688 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322593 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6446 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 13285 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22768352 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68999 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65820694 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.695691 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.296532 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5006781 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88183966 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17206050 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9546900 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60089478 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322083 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 23 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13752 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22762089 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69210 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65777829 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696584 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296287 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20039717 30.45% 30.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8265549 12.56% 43.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9200264 13.98% 56.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28315164 43.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20002417 30.41% 30.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8264821 12.56% 42.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9199012 13.98% 56.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28311579 43.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65820694 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258106 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.322964 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8562659 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19557917 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31575920 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5632021 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492177 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3179708 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171007 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101418024 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3051775 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492177 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13320782 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5331170 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 788978 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32236803 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13650784 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99206458 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 984473 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3857341 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 63915 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4307533 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5353775 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103928524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457724306 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115417327 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65777829 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258388 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.324283 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8581179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19502182 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31574906 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5627602 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 491960 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179377 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 170933 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101404474 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3045182 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 491960 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13335070 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5313056 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 801397 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32234531 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13601815 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99199856 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 982546 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3844821 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62523 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4317608 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5297882 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103921297 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457696388 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115410759 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10299298 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18661 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18655 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12693692 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24322711 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21993814 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1396246 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2340033 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98168548 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 10292071 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12693629 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24321623 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21992796 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1398027 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2340833 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98163899 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 34521 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94889336 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 694958 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7520484 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20257229 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 94893533 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694347 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7515835 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20236855 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 735 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65820694 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.441634 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150001 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 65777829 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.442637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.149664 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17560123 26.68% 26.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17422684 26.47% 53.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17103546 25.99% 79.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11678791 17.74% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2054563 3.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 987 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17511633 26.62% 26.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17428256 26.50% 53.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17102675 26.00% 79.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11682123 17.76% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2052152 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 990 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65820694 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65777829 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6715459 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 39 0.00% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6715699 22.40% 22.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available @@ -526,118 +527,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11205581 37.37% 59.77% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12062957 40.23% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11201748 37.36% 59.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12068794 40.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49498174 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89865 0.09% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24060336 25.36% 77.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21240923 22.38% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49496640 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89875 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24065423 25.36% 77.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21241557 22.38% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94889336 # Type of FU issued -system.cpu.iq.rate 1.423443 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29984036 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315990 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286278153 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105734805 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93465836 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94893533 # Type of FU issued +system.cpu.iq.rate 1.425042 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29986279 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315999 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286245314 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105725496 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93465397 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124873254 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124879694 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1363649 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1364211 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1456449 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2030 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11752 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1438076 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1455361 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11748 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1437058 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 138616 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 176709 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 140354 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 182528 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492177 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 621288 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 454814 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98212928 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 491960 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 620291 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 463716 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98208276 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24322711 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21993814 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 24321623 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21992796 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 18601 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1642 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 450257 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11752 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303335 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221647 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524982 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93971179 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23753264 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 918157 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 1628 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 459155 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11748 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 302696 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221540 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524236 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93976140 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23758122 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 917393 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9859 # number of nop insts executed -system.cpu.iew.exec_refs 44736876 # number of memory reference insts executed -system.cpu.iew.exec_branches 14252919 # Number of branches executed -system.cpu.iew.exec_stores 20983612 # Number of stores executed -system.cpu.iew.exec_rate 1.409670 # Inst execution rate -system.cpu.iew.wb_sent 93587571 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93465893 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44982416 # num instructions producing a value -system.cpu.iew.wb_consumers 76564206 # num instructions consuming a value +system.cpu.iew.exec_nop 9856 # number of nop insts executed +system.cpu.iew.exec_refs 44743070 # number of memory reference insts executed +system.cpu.iew.exec_branches 14251776 # Number of branches executed +system.cpu.iew.exec_stores 20984948 # Number of stores executed +system.cpu.iew.exec_rate 1.411265 # Inst execution rate +system.cpu.iew.wb_sent 93586994 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93465454 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44981756 # num instructions producing a value +system.cpu.iew.wb_consumers 76565949 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.402090 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587512 # average fanout of values written-back +system.cpu.iew.wb_rate 1.403596 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587490 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6539953 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6535729 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479186 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64761460 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.400341 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.165093 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 478985 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64719651 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.401246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.164864 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31172018 48.13% 48.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16800427 25.94% 74.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4337432 6.70% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4161423 6.43% 87.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935218 2.99% 90.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1264756 1.95% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 739046 1.14% 93.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 579471 0.89% 94.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3771669 5.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31116285 48.08% 48.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16809912 25.97% 74.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4342534 6.71% 80.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4161990 6.43% 87.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1938865 3.00% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1263903 1.95% 92.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 739138 1.14% 93.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 578808 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3768216 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64761460 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64719651 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -683,379 +684,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3771669 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158192582 # The number of ROB reads -system.cpu.rob.rob_writes 195517129 # The number of ROB writes -system.cpu.timesIdled 23763 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 841133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3768216 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158150002 # The number of ROB reads +system.cpu.rob.rob_writes 195507605 # The number of ROB writes +system.cpu.timesIdled 23773 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 812160 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.940122 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.940122 # CPI: Total CPI of All Threads -system.cpu.ipc 1.063692 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.063692 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102266688 # number of integer regfile reads -system.cpu.int_regfile_writes 56794481 # number of integer regfile writes +system.cpu.cpi 0.939109 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.939109 # CPI: Total CPI of All Threads +system.cpu.ipc 1.064839 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.064839 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102273698 # number of integer regfile reads +system.cpu.int_regfile_writes 56793498 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 346084159 # number of cc regfile reads -system.cpu.cc_regfile_writes 38805382 # number of cc regfile writes -system.cpu.misc_regfile_reads 44209334 # number of misc regfile reads +system.cpu.cc_regfile_reads 346096996 # number of cc regfile reads +system.cpu.cc_regfile_writes 38804962 # number of cc regfile writes +system.cpu.misc_regfile_reads 44209976 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485106 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.740457 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40427935 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485618 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.250487 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 152807000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.740457 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997540 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997540 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485041 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.740827 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40418511 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485553 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.242223 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 152851500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.740827 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997541 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997541 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84615616 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84615616 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21501539 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21501539 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18833357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18833357 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 61715 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 61715 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84611501 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84611501 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21495962 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21495962 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831064 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831064 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60188 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60188 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15352 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15352 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40334896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40334896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40396611 # number of overall hits -system.cpu.dcache.overall_hits::total 40396611 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 552871 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 552871 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1016544 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1016544 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 67128 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 67128 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1569415 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1569415 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1636543 # number of overall misses -system.cpu.dcache.overall_misses::total 1636543 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9102953011 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9102953011 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14661434456 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14661434456 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5113500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23764387467 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23764387467 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23764387467 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23764387467 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054410 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054410 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40327026 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40327026 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40387214 # number of overall hits +system.cpu.dcache.overall_hits::total 40387214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 556411 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 556411 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018837 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018837 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68667 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68667 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 574 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 574 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1575248 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575248 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1643915 # number of overall misses +system.cpu.dcache.overall_misses::total 1643915 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8968261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8968261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14556255401 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14556255401 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4964500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4964500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23524516401 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23524516401 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23524516401 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23524516401 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22052373 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22052373 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128843 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128843 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128855 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128855 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904311 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904311 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033154 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033154 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025069 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025069 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051212 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051212 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.521006 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.521006 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037452 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037452 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038935 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038935 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16464.876998 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16464.876998 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14422.823268 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14422.823268 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9348.263254 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9348.263254 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15142.194682 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15142.194682 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14521.089557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14521.089557 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3013610 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 128472 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23.457329 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41902274 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41902274 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42031129 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42031129 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025231 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025231 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051327 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051327 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532901 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532901 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036042 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039112 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039112 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16118.051225 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16118.051225 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14287.128757 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14287.128757 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8648.954704 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8648.954704 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14933.849401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14933.849401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14310.056421 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14310.056421 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 45 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3094334 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 130016 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.625000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.799640 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 264409 # number of writebacks -system.cpu.dcache.writebacks::total 264409 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 253375 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 253375 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868011 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 868011 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1121386 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1121386 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1121386 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1121386 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299496 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299496 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148533 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148533 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37600 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37600 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 448029 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 448029 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485629 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485629 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3035888114 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3035888114 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279411901 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279411901 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2033283784 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2033283784 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5315300015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5315300015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7348583799 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7348583799 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013580 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013580 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 256956 # number of writebacks +system.cpu.dcache.writebacks::total 256956 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 256971 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 256971 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870307 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870307 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 574 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 574 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1127278 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1127278 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1127278 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1127278 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299440 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299440 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148530 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148530 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37596 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37596 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 447970 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447970 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3182608500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3182608500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2345597960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2345597960 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2017960000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2017960000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5528206460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5528206460 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7546166460 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7546166460 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013579 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291828 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291828 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010692 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010692 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291770 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010691 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011553 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.011553 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10136.656630 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10136.656630 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15346.164832 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15346.164832 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54076.696383 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54076.696383 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11863.740997 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11863.740997 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15132.094251 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15132.094251 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10628.534932 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10628.534932 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15792.082138 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15792.082138 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53674.859028 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53674.859028 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12340.572940 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12340.572940 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15540.969631 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15540.969631 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322771 # number of replacements -system.cpu.icache.tags.tagsinuse 510.304013 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22435446 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323283 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.398781 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1099609250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.304013 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.replacements 322718 # number of replacements +system.cpu.icache.tags.tagsinuse 510.301604 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22427944 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323227 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.387594 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1102167500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.301604 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996683 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996683 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 354 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 347 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45859770 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45859770 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22435446 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22435446 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22435446 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22435446 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22435446 # number of overall hits -system.cpu.icache.overall_hits::total 22435446 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 332792 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 332792 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 332792 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 332792 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 332792 # number of overall misses -system.cpu.icache.overall_misses::total 332792 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3372368098 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3372368098 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3372368098 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3372368098 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3372368098 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3372368098 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22768238 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22768238 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22768238 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22768238 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22768238 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22768238 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014617 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014617 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014617 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014617 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014617 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014617 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10133.561197 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10133.561197 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10133.561197 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10133.561197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10133.561197 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10133.561197 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 259166 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14826 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 45847164 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45847164 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22427950 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22427950 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22427950 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22427950 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22427950 # number of overall hits +system.cpu.icache.overall_hits::total 22427950 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 334012 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 334012 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 334012 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 334012 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 334012 # number of overall misses +system.cpu.icache.overall_misses::total 334012 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3359547390 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3359547390 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3359547390 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3359547390 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3359547390 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3359547390 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22761962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22761962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22761962 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22761962 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22761962 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22761962 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014674 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014674 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014674 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014674 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014674 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014674 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10058.163749 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10058.163749 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10058.163749 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10058.163749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10058.163749 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10058.163749 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 273191 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 314 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16668 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.480507 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.390149 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 157 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9498 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 9498 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 9498 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 9498 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 9498 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 9498 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323294 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323294 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323294 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323294 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323294 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2922927754 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2922927754 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2922927754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2922927754 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2922927754 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2922927754 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014199 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014199 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014199 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014199 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014199 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014199 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9041.082587 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9041.082587 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9041.082587 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 9041.082587 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9041.082587 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 9041.082587 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 10772 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 10772 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 10772 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 10772 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 10772 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 10772 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323240 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323240 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323240 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323240 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323240 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323240 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3075719938 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 3075719938 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3075719938 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 3075719938 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3075719938 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 3075719938 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014201 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014201 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014201 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014201 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014201 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014201 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9515.282570 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9515.282570 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9515.282570 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9515.282570 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9515.282570 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9515.282570 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 824420 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 826170 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 1539 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 823311 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826037 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 2394 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 78694 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 129309 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16078.989093 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 872580 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 145594 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.993241 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78819 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 129183 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16078.827633 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1332410 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 145465 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.159660 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 12596.793225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1430.956994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1951.680185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 99.558690 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768847 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087339 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.119121 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006077 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.981384 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 24 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16261 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 12584.053825 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1451.251559 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1933.402514 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 110.119734 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768070 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088577 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.118006 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006721 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.981374 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 37 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16245 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # 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mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8283 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8283 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 9057 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 9057 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 30909 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 30909 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9057 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 39192 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 48249 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9057 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 39192 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112459 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 160708 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10889744040 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10889744040 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 101500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 101500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 639425500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 639425500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 650223000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 650223000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2490483000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2490483000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 650223000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3129908500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3780131500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 650223000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3129908500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10889744040 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14669875540 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.054876 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.054876 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028201 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059659 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028201 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080600 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.461538 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.461538 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055753 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055753 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.028021 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.028021 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.091722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.091722 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028021 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080716 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.059657 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028021 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080716 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.198990 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69779.012833 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79124.864270 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77000.288094 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96490.636919 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13667.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13667.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74306.149516 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74306.149516 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69779.012833 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78121.134641 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76545.123938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69779.012833 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78121.134641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90510.811957 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.198705 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96833.015054 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77197.331885 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77197.331885 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71792.315336 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71792.315336 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80574.686984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80574.686984 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71792.315336 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79860.902735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78346.318058 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71792.315336 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79860.902735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91282.795754 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 660341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 660341 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 264409 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 151292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148571 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148571 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646576 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1235667 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1882243 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20690048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48001728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 151304 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.123542 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 660226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 354828 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 502259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 152780 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323240 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336986 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 938639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2345500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20686336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47520576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68206912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 281979 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1898528 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.148517 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.355611 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1073332 87.65% 87.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 151292 12.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1616565 85.15% 85.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 281963 14.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486570693 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1898528 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1065238500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 485020678 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 734618165 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728403365 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 137030 # Transaction distribution -system.membus.trans_dist::ReadResp 137030 # Transaction distribution -system.membus.trans_dist::Writeback 97752 # Transaction distribution +system.membus.trans_dist::ReadResp 136784 # Transaction distribution +system.membus.trans_dist::Writeback 97872 # Transaction distribution +system.membus.trans_dist::CleanEvict 30200 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8153 # Transaction distribution -system.membus.trans_dist::ReadExResp 8153 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388130 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 388130 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15547840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15547840 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8283 # Transaction distribution +system.membus.trans_dist::ReadExResp 8283 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 136784 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 418218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 418218 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15548096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15548096 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 242941 # Request fanout histogram +system.membus.snoop_fanout::samples 273145 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 242941 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 273145 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 242941 # Request fanout histogram -system.membus.reqLayer0.occupancy 691321050 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 757153835 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 273145 # Request fanout histogram +system.membus.reqLayer0.occupancy 717072511 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 756625908 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |