diff options
Diffstat (limited to 'tests/long/se/50.vortex')
34 files changed, 0 insertions, 7152 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini deleted file mode 100644 index bc26b879f..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ /dev/null @@ -1,172 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr deleted file mode 100755 index 506aa6e28..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout deleted file mode 100755 index faff61794..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ /dev/null @@ -1,11 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 18:27:58 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 44221003000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg deleted file mode 100644 index 472b08431..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt deleted file mode 100644 index db2ebe7dc..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ /dev/null @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.044221 # Number of seconds simulated -sim_ticks 44221003000 # Number of ticks simulated -final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2813944 # Simulator instruction rate (inst/s) -host_op_rate 2813942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1408584494 # Simulator tick rate (ticks/s) -host_mem_usage 287952 # Number of bytes of host memory used -host_seconds 31.39 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory -system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory -system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 108714711 # Transaction distribution -system.membus.trans_dist::ReadResp 108714711 # Transaction distribution -system.membus.trans_dist::WriteReq 14613377 # Transaction distribution -system.membus.trans_dist::WriteResp 14613377 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 123328088 # Request fanout histogram -system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram -system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 123328088 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438073 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442007 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 88442007 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 88442007 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini deleted file mode 100644 index 5ccaad7e0..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ /dev/null @@ -1,285 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr deleted file mode 100755 index 506aa6e28..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout deleted file mode 100755 index b6a75fdf5..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ /dev/null @@ -1,11 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 16:27:55 -gem5 started Jan 22 2014 18:28:33 -gem5 executing on u200540-lin -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 133634727000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg deleted file mode 100644 index 472b08431..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt deleted file mode 100644 index 987ba828d..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ /dev/null @@ -1,525 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.133634 # Number of seconds simulated -sim_ticks 133634149500 # Number of ticks simulated -final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1329181 # Simulator instruction rate (inst/s) -host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2010669405 # Simulator tick rate (ticks/s) -host_mem_usage 301232 # Number of bytes of host memory used -host_seconds 66.46 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory -system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory -system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory -system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438074 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442008 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267268299 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267268299 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits -system.cpu.dcache.overall_hits::total 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses -system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363527000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7363527000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9308954000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9308954000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9308954000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9308954000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks -system.cpu.dcache.writebacks::total 168375 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1854278000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1854278000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7148160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7148160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9002438000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686268 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses -system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits -system.cpu.icache.overall_hits::total 88361638 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses -system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1277887500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1277887500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1277887500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1163233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1163233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1163233500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1163233500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 131235 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30728.805700 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.509533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853974 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.833082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 654 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3900109 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168375 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168375 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12697 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12697 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 69672 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45955 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 115627 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 69672 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45955 # number of overall hits -system.cpu.l2cache.overall_hits::total 115627 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 6764 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 27508 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 34272 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130881 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130881 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6764 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158389 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165153 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158389 # number of overall misses -system.cpu.l2cache.overall_misses::total 165153 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 355241500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1444303000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1799544500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6871263500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6871263500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 355241500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8315566500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8670808000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 355241500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8315566500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8670808000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168375 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168375 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088492 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.452687 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.249792 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911567 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911567 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088492 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775110 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.588194 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 113982 # number of writebacks -system.cpu.l2cache.writebacks::total 113982 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 6764 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27508 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130881 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 34272 # Transaction distribution -system.membus.trans_dist::ReadResp 34272 # Transaction distribution -system.membus.trans_dist::Writeback 113982 # Transaction distribution -system.membus.trans_dist::ReadExReq 130881 # Transaction distribution -system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 279135 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 279135 # Request fanout histogram -system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini deleted file mode 100644 index f73c6b128..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ /dev/null @@ -1,270 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[6] - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[5] - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout deleted file mode 100755 index b32e4875d..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:03:38 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x49b6380 -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 53932157000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt deleted file mode 100644 index 93e5e3e06..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,245 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.048960 # Number of seconds simulated -sim_ticks 48960011000 # Number of ticks simulated -final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1566427 # Simulator instruction rate (inst/s) -host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1081494789 # Simulator tick rate (ticks/s) -host_mem_usage 308080 # Number of bytes of host memory used -host_seconds 45.27 # Real time elapsed on the host -sim_insts 70913181 # Number of instructions simulated -sim_ops 90688136 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory -system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory -system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory -system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 97920023 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913181 # Number of instructions committed -system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528488 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 97920022.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741485 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690083 # Class of executed instruction -system.membus.trans_dist::ReadReq 100925135 # Transaction distribution -system.membus.trans_dist::ReadResp 100941054 # Transaction distribution -system.membus.trans_dist::WriteReq 19849901 # Transaction distribution -system.membus.trans_dist::WriteResp 19849901 # Transaction distribution -system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution -system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930618 # Request fanout histogram -system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 2 # Request fanout histogram -system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 120930618 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini deleted file mode 100644 index 8d05feb2e..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ /dev/null @@ -1,383 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[5] - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 -midr=1091551472 -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[4] - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout deleted file mode 100755 index 4bb28ef2b..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 18:04:30 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x5604d00 -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 132689045000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt deleted file mode 100644 index 6d597c67f..000000000 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ /dev/null @@ -1,643 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.127293 # Number of seconds simulated -sim_ticks 127293405500 # Number of ticks simulated -final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 802256 # Simulator instruction rate (inst/s) -host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1451138855 # Simulator tick rate (ticks/s) -host_mem_usage 317568 # Number of bytes of host memory used -host_seconds 87.72 # Real time elapsed on the host -sim_insts 70373628 # Number of instructions simulated -sim_ops 89847362 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory -system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory -system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254586811 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373628 # Number of instructions committed -system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528488 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741485 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690083 # Class of executed instruction -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits -system.cpu.dcache.overall_hits::total 42576331 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses -system.cpu.dcache.overall_misses::total 177381 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks -system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits -system.cpu.icache.overall_hits::total 78126161 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses -system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128239 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128239 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 14916 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36178 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51094 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 14916 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36178 # number of overall hits -system.cpu.l2cache.overall_hits::total 51094 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3992 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21540 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 25532 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3992 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123820 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127812 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses -system.cpu.l2cache.overall_misses::total 127812 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210047000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128239 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128239 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.211128 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.406676 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.355233 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955602 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955602 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.211128 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773885 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.714409 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 83909 # number of writebacks -system.cpu.l2cache.writebacks::total 83909 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3992 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21540 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 25532 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3992 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123820 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127812 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 25532 # Transaction distribution -system.membus.trans_dist::ReadResp 25532 # Transaction distribution -system.membus.trans_dist::Writeback 83909 # Transaction distribution -system.membus.trans_dist::ReadExReq 102280 # Transaction distribution -system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214640 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214640 # Request fanout histogram -system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini deleted file mode 100644 index 5fee4647b..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ /dev/null @@ -1,171 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=SparcInterrupts -eventq_index=0 - -[system.cpu.isa] -type=SparcISA -eventq_index=0 - -[system.cpu.itb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex bendian.raw -cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr deleted file mode 100755 index f7abb9a35..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr +++ /dev/null @@ -1,562 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall time(4026528248, 4026527848, ...) -warn: ignoring syscall time(1375098, 4026527400, ...) -warn: ignoring syscall time(1, 4026527312, ...) -warn: ignoring syscall time(413, 4026527048, ...) -warn: ignoring syscall time(414, 4026527048, ...) -warn: ignoring syscall time(4026527688, 4026527288, ...) -warn: ignoring syscall time(1375098, 4026526840, ...) -warn: ignoring syscall time(409, 4026527048, ...) -warn: ignoring syscall time(409, 4026527048, ...) -warn: ignoring syscall time(409, 4026526960, ...) -warn: ignoring syscall time(409, 4026527040, ...) -warn: ignoring syscall time(409, 4026527000, ...) -warn: ignoring syscall time(409, 4026526984, ...) -warn: ignoring syscall time(409, 4026526984, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(19045, 4026526312, ...) -warn: ignoring syscall time(409, 4026526832, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(409, 4026526848, ...) -warn: ignoring syscall time(409, 4026526840, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(409, 4026526856, ...) -warn: ignoring syscall time(409, 4026526848, ...) -warn: ignoring syscall time(409, 4026526936, ...) -warn: ignoring syscall time(4026527408, 4026527008, ...) -warn: ignoring syscall time(1375098, 4026526560, ...) -warn: ignoring syscall time(18732, 4026527184, ...) -warn: ignoring syscall time(409, 4026526632, ...) -warn: ignoring syscall time(0, 4026526736, ...) -warn: ignoring syscall time(0, 4026527320, ...) -warn: ignoring syscall time(225, 4026527744, ...) -warn: ignoring syscall time(409, 4026527048, ...) -warn: ignoring syscall time(409, 4026526856, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(4026527496, 4026527096, ...) -warn: ignoring syscall time(1375098, 4026526648, ...) -warn: ignoring syscall time(0, 4026526824, ...) -warn: ignoring syscall time(0, 4026527320, ...) -warn: ignoring syscall time(1879089152, 4026527184, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall time(1595768, 4026527472, ...) -warn: ignoring syscall time(17300, 4026526912, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(19045, 4026526912, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(19045, 4026526912, ...) -warn: ignoring syscall time(17300, 4026526912, ...) -warn: ignoring syscall time(20500, 4026525968, ...) -warn: ignoring syscall time(4026526436, 4026525968, ...) -warn: ignoring syscall time(7004192, 4026526056, ...) -warn: ignoring syscall time(4, 4026527512, ...) -warn: ignoring syscall time(0, 4026525760, ...) diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout deleted file mode 100755 index 9c35a9a4f..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ /dev/null @@ -1,11 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 19:46:20 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 68148672000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg deleted file mode 100644 index 0ac2d9980..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := False - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 4 - sizeof(longaddr ) = 4 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 4 - sizeof(char * ) = 4 - ALLOC CORE_1 :: 8 - BHOOLE NATH - - OPEN File ./input/bendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 1b4750 - - OPEN File ./input/bendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt deleted file mode 100644 index 9acb631e8..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,124 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148672000 # Number of ticks simulated -final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2078407 # Simulator instruction rate (inst/s) -host_op_rate 2105318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1053881878 # Simulator tick rate (ticks/s) -host_mem_usage 288492 # Number of bytes of host memory used -host_seconds 64.66 # Real time elapsed on the host -sim_insts 134398962 # Number of instructions simulated -sim_ops 136139190 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory -system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 538214280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 538214280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory -system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 134553570 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171784870 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory -system.physmem.num_other::total 15916 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7897648835 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2165256573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10062905408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7897648835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7897648835 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1318924454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318924454 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 171784870 # Transaction distribution -system.membus.trans_dist::ReadResp 171784870 # Transaction distribution -system.membus.trans_dist::WriteReq 20864304 # Transaction distribution -system.membus.trans_dist::WriteResp 20864304 # Transaction distribution -system.membus.trans_dist::SwapReq 15916 # Transaction distribution -system.membus.trans_dist::SwapResp 15916 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107140 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385330180 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 775783918 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 192665090 # Request fanout histogram -system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram -system.membus.snoop_fanout::1 134553570 69.84% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 192665090 # Request fanout histogram -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 136297345 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398962 # Number of instructions committed -system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187746 # number of integer instructions -system.cpu.num_fp_insts 2326977 # number of float instructions -system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147734 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160248 # number of memory refs -system.cpu.num_load_insts 37275867 # Number of load instructions -system.cpu.num_store_insts 20884381 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 136297344.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719095 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293798 # Class of executed instruction - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini deleted file mode 100644 index 5186e7456..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ /dev/null @@ -1,284 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=SparcInterrupts -eventq_index=0 - -[system.cpu.isa] -type=SparcISA -eventq_index=0 - -[system.cpu.itb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex bendian.raw -cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr deleted file mode 100755 index f7abb9a35..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr +++ /dev/null @@ -1,562 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ignoring syscall time(4026528248, 4026527848, ...) -warn: ignoring syscall time(1375098, 4026527400, ...) -warn: ignoring syscall time(1, 4026527312, ...) -warn: ignoring syscall time(413, 4026527048, ...) -warn: ignoring syscall time(414, 4026527048, ...) -warn: ignoring syscall time(4026527688, 4026527288, ...) -warn: ignoring syscall time(1375098, 4026526840, ...) -warn: ignoring syscall time(409, 4026527048, ...) -warn: ignoring syscall time(409, 4026527048, ...) -warn: ignoring syscall time(409, 4026526960, ...) -warn: ignoring syscall time(409, 4026527040, ...) -warn: ignoring syscall time(409, 4026527000, ...) -warn: ignoring syscall time(409, 4026526984, ...) -warn: ignoring syscall time(409, 4026526984, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(19045, 4026526312, ...) -warn: ignoring syscall time(409, 4026526832, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(409, 4026526848, ...) -warn: ignoring syscall time(409, 4026526840, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(409, 4026526856, ...) -warn: ignoring syscall time(409, 4026526848, ...) -warn: ignoring syscall time(409, 4026526936, ...) -warn: ignoring syscall time(4026527408, 4026527008, ...) -warn: ignoring syscall time(1375098, 4026526560, ...) -warn: ignoring syscall time(18732, 4026527184, ...) -warn: ignoring syscall time(409, 4026526632, ...) -warn: ignoring syscall time(0, 4026526736, ...) -warn: ignoring syscall time(0, 4026527320, ...) -warn: ignoring syscall time(225, 4026527744, ...) -warn: ignoring syscall time(409, 4026527048, ...) -warn: ignoring syscall time(409, 4026526856, ...) -warn: ignoring syscall time(409, 4026526872, ...) -warn: ignoring syscall time(4026527496, 4026527096, ...) -warn: ignoring syscall time(1375098, 4026526648, ...) -warn: ignoring syscall time(0, 4026526824, ...) -warn: ignoring syscall time(0, 4026527320, ...) -warn: ignoring syscall time(1879089152, 4026527184, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall times(246, 4026527728, ...) -warn: ignoring syscall time(1595768, 4026527472, ...) -warn: ignoring syscall time(17300, 4026526912, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(19045, 4026526912, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(0, 4026527472, ...) -warn: ignoring syscall time(19045, 4026526912, ...) -warn: ignoring syscall time(17300, 4026526912, ...) -warn: ignoring syscall time(20500, 4026525968, ...) -warn: ignoring syscall time(4026526436, 4026525968, ...) -warn: ignoring syscall time(7004192, 4026526056, ...) -warn: ignoring syscall time(4, 4026527512, ...) -warn: ignoring syscall time(0, 4026525760, ...) diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout deleted file mode 100755 index 2ff984591..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ /dev/null @@ -1,11 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 19:47:13 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 202242260000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg deleted file mode 100644 index 0ac2d9980..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := False - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 4 - sizeof(longaddr ) = 4 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 4 - sizeof(char * ) = 4 - ALLOC CORE_1 :: 8 - BHOOLE NATH - - OPEN File ./input/bendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 1b4750 - - OPEN File ./input/bendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt deleted file mode 100644 index 718e317fa..000000000 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ /dev/null @@ -1,514 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.202242 # Number of seconds simulated -sim_ticks 202242028500 # Number of ticks simulated -final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1201078 # Simulator instruction rate (inst/s) -host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1807368744 # Simulator tick rate (ticks/s) -host_mem_usage 300888 # Number of bytes of host memory used -host_seconds 111.90 # Real time elapsed on the host -sim_insts 134398962 # Number of instructions simulated -sim_ops 136139190 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory -system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory -system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory -system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404484057 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398962 # Number of instructions committed -system.cpu.committedOps 136139190 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187746 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898969 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187746 # number of integer instructions -system.cpu.num_fp_insts 2326977 # number of float instructions -system.cpu.num_int_register_reads 263032361 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147733 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725607 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160248 # number of memory refs -system.cpu.num_load_insts 37275867 # Number of load instructions -system.cpu.num_store_insts 20884381 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719095 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342070 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296721 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293798 # Class of executed instruction -system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits -system.cpu.dcache.overall_hits::total 57944941 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses -system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1475000000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619674000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5619674000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7094674000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7094674000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7094674000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7094674000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47089.690236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks -system.cpu.dcache.writebacks::total 123970 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1406751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1406751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5461928000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5461928000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 382500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 382500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6868679500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6868679500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6868679500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6868679500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143972077000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 269294166 # Number of tag accesses -system.cpu.icache.tags.data_accesses 269294166 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134366547 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134366547 # number of overall hits -system.cpu.icache.overall_hits::total 134366547 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses -system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819561500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2819561500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2819561500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2819561500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2819561500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2819561500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 134553571 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 134553571 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 134553571 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15075.934105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15075.934105 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2539025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2539025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2539025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2539025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2539025500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2539025500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98540 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30850.758845 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.945467 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264265 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 30994 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 533 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12212 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17536 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 585 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945862 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3928089 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3928089 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 123970 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 123970 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3923 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3923 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 177782 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 28387 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 206169 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 177782 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 28387 # number of overall hits -system.cpu.l2cache.overall_hits::total 206169 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 9242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21035 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 30277 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101256 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101256 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 9242 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122291 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 131533 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses -system.cpu.l2cache.overall_misses::total 131533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 485290500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1104380500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1589671000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5315940000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5315940000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 485290500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6420320500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6905611000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 485290500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6420320500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6905611000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 123970 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 123970 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 150678 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 337702 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 150678 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 337702 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.049416 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.462318 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.130211 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962702 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.962702 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.049416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.811605 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.389494 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 82868 # number of writebacks -system.cpu.l2cache.writebacks::total 82868 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9242 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21035 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 30277 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101256 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101256 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 9242 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122291 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 131533 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 374386000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 851960500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1226346500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4100868000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4100868000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 374386000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4952828500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5327214500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 374386000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4952828500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5327214500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962702 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962702 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 30277 # Transaction distribution -system.membus.trans_dist::ReadResp 30277 # Transaction distribution -system.membus.trans_dist::Writeback 82868 # Transaction distribution -system.membus.trans_dist::ReadExReq 101256 # Transaction distribution -system.membus.trans_dist::ReadExResp 101256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214401 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214401 # Request fanout histogram -system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |