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-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini40
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini45
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini40
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini369
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini7
-rw-r--r--tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini7
10 files changed, 331 insertions, 205 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
index d2cfbc574..e4bee3f35 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini
@@ -632,10 +632,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -665,6 +666,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -683,10 +685,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -695,8 +698,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -705,6 +733,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -718,19 +747,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index e46a676eb..72bc50e35 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -17,6 +17,7 @@ clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
+kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -73,6 +74,7 @@ do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBufferSize=64
+fetchQueueSize=32
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
@@ -125,7 +127,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -580,10 +581,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -603,7 +605,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
@@ -613,6 +615,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -631,10 +634,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -643,8 +647,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -653,6 +682,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -666,19 +696,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 34c305ae5..bc26b879f 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -125,6 +122,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -143,10 +141,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index d2c7c290f..5ccaad7e0 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -201,10 +201,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -234,6 +235,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -252,10 +254,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
index 6ff93edf5..fd6ea1264 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
@@ -730,10 +730,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -763,6 +764,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -781,10 +783,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -793,8 +796,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -803,6 +831,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -816,19 +845,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 11661d187..6bff9ac08 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -47,10 +47,10 @@ voltage_domain=system.voltage_domain
type=DerivO3CPU
children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload
LFSTSize=1024
-LQEntries=32
+LQEntries=16
LSQCheckLoads=true
-LSQDepCheckShift=4
-SQEntries=32
+LSQDepCheckShift=0
+SQEntries=16
SSITSize=1024
activity=0
backComSize=5
@@ -65,19 +65,20 @@ commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
-decodeToRenameDelay=1
-decodeWidth=8
-dispatchWidth=8
+decodeToRenameDelay=2
+decodeWidth=3
+dispatchWidth=6
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
-fetchBufferSize=64
-fetchToDecodeDelay=1
+fetchBufferSize=16
+fetchQueueSize=32
+fetchToDecodeDelay=3
fetchTrapLatency=1
-fetchWidth=8
+fetchWidth=3
forwardComSize=5
fuPool=system.cpu.fuPool
function_trace=false
@@ -97,20 +98,20 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
-numIQEntries=64
-numPhysCCRegs=0
-numPhysFloatRegs=256
-numPhysIntRegs=256
-numROBEntries=192
+numIQEntries=32
+numPhysCCRegs=640
+numPhysFloatRegs=192
+numPhysIntRegs=128
+numROBEntries=40
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
-renameToIEWDelay=2
+renameToIEWDelay=1
renameToROBDelay=1
-renameWidth=8
+renameWidth=3
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
@@ -128,7 +129,6 @@ switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
-wbDepth=1
wbWidth=8
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
@@ -136,8 +136,8 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
+BTBEntries=2048
+BTBTagSize=18
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
@@ -149,7 +149,7 @@ localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
-predType=tournament
+predType=bi-mode
[system.cpu.dcache]
type=BaseCache
@@ -162,17 +162,17 @@ forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=6
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
-size=262144
+size=32768
system=system
tags=system.cpu.dcache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
-write_buffers=8
+write_buffers=16
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
@@ -184,7 +184,7 @@ clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
-size=262144
+size=32768
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -229,14 +229,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.fuPool]
type=FUPool
-children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
-FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
+children=FUList0 FUList1 FUList2 FUList3 FUList4
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4
eventq_index=0
[system.cpu.fuPool.FUList0]
type=FUDesc
children=opList
-count=6
+count=2
eventq_index=0
opList=system.cpu.fuPool.FUList0.opList
@@ -249,10 +249,10 @@ opLat=1
[system.cpu.fuPool.FUList1]
type=FUDesc
-children=opList0 opList1
-count=2
+children=opList0 opList1 opList2
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2
[system.cpu.fuPool.FUList1.opList0]
type=OpDesc
@@ -264,275 +264,233 @@ opLat=3
[system.cpu.fuPool.FUList1.opList1]
type=OpDesc
eventq_index=0
-issueLat=19
+issueLat=12
opClass=IntDiv
-opLat=20
-
-[system.cpu.fuPool.FUList2]
-type=FUDesc
-children=opList0 opList1 opList2
-count=4
-eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+opLat=12
-[system.cpu.fuPool.FUList2.opList0]
+[system.cpu.fuPool.FUList1.opList2]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatAdd
-opLat=2
+opClass=IprAccess
+opLat=3
-[system.cpu.fuPool.FUList2.opList1]
-type=OpDesc
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList
+count=1
eventq_index=0
-issueLat=1
-opClass=FloatCmp
-opLat=2
+opList=system.cpu.fuPool.FUList2.opList
-[system.cpu.fuPool.FUList2.opList2]
+[system.cpu.fuPool.FUList2.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=FloatCvt
+opClass=MemRead
opLat=2
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
-count=2
-eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
-
-[system.cpu.fuPool.FUList3.opList0]
-type=OpDesc
-eventq_index=0
-issueLat=1
-opClass=FloatMult
-opLat=4
-
-[system.cpu.fuPool.FUList3.opList1]
-type=OpDesc
-eventq_index=0
-issueLat=12
-opClass=FloatDiv
-opLat=12
-
-[system.cpu.fuPool.FUList3.opList2]
-type=OpDesc
-eventq_index=0
-issueLat=24
-opClass=FloatSqrt
-opLat=24
-
-[system.cpu.fuPool.FUList4]
-type=FUDesc
children=opList
-count=0
+count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList3.opList
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList3.opList]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=MemWrite
+opLat=2
-[system.cpu.fuPool.FUList5]
+[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
-count=4
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
-[system.cpu.fuPool.FUList5.opList00]
+[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAdd
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList01]
+[system.cpu.fuPool.FUList4.opList01]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAddAcc
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList02]
+[system.cpu.fuPool.FUList4.opList02]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdAlu
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList03]
+[system.cpu.fuPool.FUList4.opList03]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCmp
-opLat=1
+opLat=4
-[system.cpu.fuPool.FUList5.opList04]
+[system.cpu.fuPool.FUList4.opList04]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList05]
+[system.cpu.fuPool.FUList4.opList05]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList06]
+[system.cpu.fuPool.FUList4.opList06]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMult
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList07]
+[system.cpu.fuPool.FUList4.opList07]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdMultAcc
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList08]
+[system.cpu.fuPool.FUList4.opList08]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShift
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList09]
+[system.cpu.fuPool.FUList4.opList09]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdShiftAcc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList10]
+[system.cpu.fuPool.FUList4.opList10]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList5.opList11]
+[system.cpu.fuPool.FUList4.opList11]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAdd
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList12]
+[system.cpu.fuPool.FUList4.opList12]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatAlu
-opLat=1
+opLat=5
-[system.cpu.fuPool.FUList5.opList13]
+[system.cpu.fuPool.FUList4.opList13]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCmp
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList14]
+[system.cpu.fuPool.FUList4.opList14]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatCvt
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList15]
+[system.cpu.fuPool.FUList4.opList15]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatDiv
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList16]
+[system.cpu.fuPool.FUList4.opList16]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMisc
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList17]
+[system.cpu.fuPool.FUList4.opList17]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMult
-opLat=1
+opLat=3
-[system.cpu.fuPool.FUList5.opList18]
+[system.cpu.fuPool.FUList4.opList18]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
-[system.cpu.fuPool.FUList5.opList19]
+[system.cpu.fuPool.FUList4.opList19]
type=OpDesc
eventq_index=0
issueLat=1
opClass=SimdFloatSqrt
-opLat=1
+opLat=9
-[system.cpu.fuPool.FUList6]
-type=FUDesc
-children=opList
-count=0
-eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
-
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList4.opList20]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemWrite
-opLat=1
+opClass=FloatAdd
+opLat=5
-[system.cpu.fuPool.FUList7]
-type=FUDesc
-children=opList0 opList1
-count=4
+[system.cpu.fuPool.FUList4.opList21]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+issueLat=1
+opClass=FloatCmp
+opLat=5
-[system.cpu.fuPool.FUList7.opList0]
+[system.cpu.fuPool.FUList4.opList22]
type=OpDesc
eventq_index=0
issueLat=1
-opClass=MemRead
-opLat=1
+opClass=FloatCvt
+opLat=5
-[system.cpu.fuPool.FUList7.opList1]
+[system.cpu.fuPool.FUList4.opList23]
type=OpDesc
eventq_index=0
-issueLat=1
-opClass=MemWrite
-opLat=1
+issueLat=9
+opClass=FloatDiv
+opLat=9
-[system.cpu.fuPool.FUList8]
-type=FUDesc
-children=opList
-count=1
+[system.cpu.fuPool.FUList4.opList24]
+type=OpDesc
eventq_index=0
-opList=system.cpu.fuPool.FUList8.opList
+issueLat=33
+opClass=FloatSqrt
+opLat=33
-[system.cpu.fuPool.FUList8.opList]
+[system.cpu.fuPool.FUList4.opList25]
type=OpDesc
eventq_index=0
-issueLat=3
-opClass=IprAccess
-opLat=3
+issueLat=1
+opClass=FloatMult
+opLat=4
[system.cpu.icache]
type=BaseCache
@@ -542,18 +500,18 @@ assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=2
+hit_latency=1
is_top_level=true
max_miss_count=0
-mshrs=4
+mshrs=2
prefetch_on_access=false
prefetcher=Null
-response_latency=2
+response_latency=1
sequential_access=false
-size=131072
+size=32768
system=system
tags=system.cpu.icache.tags
-tgts_per_mshr=20
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -565,9 +523,9 @@ assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=2
+hit_latency=1
sequential_access=false
-size=131072
+size=32768
[system.cpu.interrupts]
type=ArmInterrupts
@@ -645,44 +603,62 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
-children=tags
+children=prefetcher tags
addr_ranges=0:18446744073709551615
-assoc=8
+assoc=16
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
-hit_latency=20
+hit_latency=12
is_top_level=false
max_miss_count=0
-mshrs=20
-prefetch_on_access=false
-prefetcher=Null
-response_latency=20
+mshrs=16
+prefetch_on_access=true
+prefetcher=system.cpu.l2cache.prefetcher
+response_latency=12
sequential_access=false
-size=2097152
+size=1048576
system=system
tags=system.cpu.l2cache.tags
-tgts_per_mshr=12
+tgts_per_mshr=8
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
+[system.cpu.l2cache.prefetcher]
+type=StridePrefetcher
+clk_domain=system.cpu_clk_domain
+cross_pages=false
+data_accesses_only=false
+degree=8
+eventq_index=0
+inst_tagged=true
+latency=1
+on_miss_only=false
+on_prefetch=true
+on_read_only=false
+serial_squash=false
+size=100
+sys=system
+use_master_id=true
+
[system.cpu.l2cache.tags]
-type=LRU
-assoc=8
+type=RandomRepl
+assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
-hit_latency=20
+hit_latency=12
sequential_access=false
-size=2097152
+size=1048576
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -712,6 +688,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -730,10 +707,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
@@ -742,8 +720,33 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
+IDD0=0.075000
+IDD02=0.000000
+IDD2N=0.050000
+IDD2N2=0.000000
+IDD2P0=0.000000
+IDD2P02=0.000000
+IDD2P1=0.000000
+IDD2P12=0.000000
+IDD3N=0.057000
+IDD3N2=0.000000
+IDD3P0=0.000000
+IDD3P02=0.000000
+IDD3P1=0.000000
+IDD3P12=0.000000
+IDD4R=0.187000
+IDD4R2=0.000000
+IDD4W=0.165000
+IDD4W2=0.000000
+IDD5=0.220000
+IDD52=0.000000
+IDD6=0.000000
+IDD62=0.000000
+VDD=1.500000
+VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
+bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
channels=1
@@ -752,6 +755,7 @@ conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
+dll=true
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
@@ -765,19 +769,26 @@ read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
+tCCD_L=0
tCK=1250
tCL=13750
+tCS=2500
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
+tRRD_L=0
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
+tXP=0
+tXPDLL=0
+tXS=0
+tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 7a9144759..f73c6b128 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -70,9 +70,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -223,6 +220,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -241,10 +239,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 0709f1643..8d05feb2e 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -299,10 +299,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -332,6 +333,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -350,10 +352,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index d88b9c728..5fee4647b 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -68,9 +68,6 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
-simpoint_interval=100000000
-simpoint_profile=false
-simpoint_profile_file=simpoint.bb.gz
simpoint_start_insts=
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -124,6 +121,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -142,10 +140,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 0fe5ca901..5186e7456 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -200,10 +200,11 @@ sequential_access=false
size=2097152
[system.cpu.toL2Bus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=32
@@ -233,6 +234,7 @@ ppid=99
simpoint=0
system=system
uid=100
+useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
@@ -251,10 +253,11 @@ sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
-type=CoherentBus
+type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
+snoop_filter=Null
system=system
use_default_range=false
width=8