diff options
Diffstat (limited to 'tests/long/se/50.vortex')
10 files changed, 1668 insertions, 1657 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 81c2390c7..b0d1b1795 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -179,6 +179,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -211,6 +212,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -218,25 +220,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index 41b47fff5..2573c0d57 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorde gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:34:49 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 22:56:38 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 43266024500 because target called exit() +Exiting @ tick 42725646500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 36773aebe..62028d00d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.042726 # Number of seconds simulated -sim_ticks 42726055500 # Number of ticks simulated -final_tick 42726055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 42725646500 # Number of ticks simulated +final_tick 42725646500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80618 # Simulator instruction rate (inst/s) -host_op_rate 80618 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38990762 # Simulator tick rate (ticks/s) -host_mem_usage 257380 # Number of bytes of host memory used -host_seconds 1095.80 # Real time elapsed on the host +host_inst_rate 44211 # Simulator instruction rate (inst/s) +host_op_rate 44211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21382391 # Simulator tick rate (ticks/s) +host_mem_usage 280712 # Number of bytes of host memory used +host_seconds 1998.17 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 454528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 10593216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454848 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10592896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454528 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7107 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7102 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165519 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165514 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10645682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 237287713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 247933395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10645682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10645682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 170757818 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 170757818 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 170757818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10645682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 237287713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 418691213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165519 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10638294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 237289985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 247928279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10638294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10638294 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 170759452 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 170759452 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 170759452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10638294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 237289985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 418687731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165514 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279517 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10593216 # Total number of bytes read from memory +system.physmem.cpureqs 279511 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10592896 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10593216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10592896 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10574 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10269 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10572 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10270 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10770 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10768 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10203 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10514 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10202 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10515 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis @@ -76,15 +76,15 @@ system.physmem.perBankWrReqs::13 7250 # Tr system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry -system.physmem.totGap 42726035000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 42725626000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165519 # Categorize read packet sizes +system.physmem.readPktSize::6 165514 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 62479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76432 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 62488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18709 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,15 +124,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4956 # What write queue length does an incoming req see @@ -147,23 +147,23 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.physmem.totQLat 7053831750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9647394250 # Sum of mem lat for all requests -system.physmem.totBusLat 827595000 # Total cycles spent in databus access -system.physmem.totBankLat 1765967500 # Total cycles spent in bank access -system.physmem.avgQLat 42616.45 # Average queueing delay per request -system.physmem.avgBankLat 10669.27 # Average bank access latency per request +system.physmem.wrQLenPdf::23 2850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.totQLat 7078163250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9669555750 # Sum of mem lat for all requests +system.physmem.totBusLat 827570000 # Total cycles spent in databus access +system.physmem.totBankLat 1763822500 # Total cycles spent in bank access +system.physmem.avgQLat 42764.74 # Average queueing delay per request +system.physmem.avgBankLat 10656.64 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58285.72 # Average memory access latency +system.physmem.avgMemAccLat 58421.38 # Average memory access latency system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s @@ -171,41 +171,41 @@ system.physmem.avgConsumedWrBW 170.76 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.27 # Data bus utilization in percentage system.physmem.avgRdQLen 0.23 # Average read queue length over time -system.physmem.avgWrQLen 10.42 # Average write queue length over time -system.physmem.readRowHits 148856 # Number of row buffer hits during reads -system.physmem.writeRowHits 71619 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.83 # Row buffer hit rate for writes -system.physmem.avgGap 152857.21 # Average gap between requests -system.cpu.branchPred.lookups 18742591 # Number of BP lookups -system.cpu.branchPred.condPredicted 12317071 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4774939 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15471437 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4667620 # Number of BTB hits +system.physmem.avgWrQLen 10.41 # Average write queue length over time +system.physmem.readRowHits 148885 # Number of row buffer hits during reads +system.physmem.writeRowHits 71702 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.90 # Row buffer hit rate for writes +system.physmem.avgGap 152858.48 # Average gap between requests +system.cpu.branchPred.lookups 18741806 # Number of BP lookups +system.cpu.branchPred.condPredicted 12317440 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4774691 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15571063 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4663219 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.169273 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660963 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 29.947981 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660960 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277550 # DTB read hits +system.cpu.dtb.read_hits 20277542 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367698 # DTB read accesses -system.cpu.dtb.write_hits 14728779 # DTB write hits +system.cpu.dtb.read_accesses 20367690 # DTB read accesses +system.cpu.dtb.write_hits 14728781 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736031 # DTB write accesses -system.cpu.dtb.data_hits 35006329 # DTB hits +system.cpu.dtb.write_accesses 14736033 # DTB write accesses +system.cpu.dtb.data_hits 35006323 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103729 # DTB accesses -system.cpu.itb.fetch_hits 12368275 # ITB hits -system.cpu.itb.fetch_misses 11063 # ITB misses +system.cpu.dtb.data_accesses 35103723 # DTB accesses +system.cpu.itb.fetch_hits 12368482 # ITB hits +system.cpu.itb.fetch_misses 10998 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12379338 # ITB accesses +system.cpu.itb.fetch_accesses 12379480 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,34 +219,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 85452112 # number of cpu cycles simulated +system.cpu.numCycles 85451294 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8078019 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10664572 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74169588 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8073687 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10668119 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74170009 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126488838 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66061 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126489259 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66071 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293691 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14166165 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060657 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447555 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216884 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4664439 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9108157 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.867537 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777871 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293701 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14164942 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060353 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447581 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216610 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4664191 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9108383 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.865790 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44777788 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77185132 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77182336 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 229329 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15874710 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69577402 # Number of cycles cpu stages are processed. -system.cpu.activity 81.422683 # Percentage of cycles cpu is active +system.cpu.timesIdled 229187 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15880194 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69571100 # Number of cycles cpu stages are processed. +system.cpu.activity 81.416087 # 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miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009468 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009468 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009468 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009468 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009468 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16131.005243 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16131.005243 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16131.005243 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16131.005243 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16131.005243 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12368472 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12368472 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12368472 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009471 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009471 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009471 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009471 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009471 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009471 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16211.047748 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16211.047748 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16211.047748 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16211.047748 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16211.047748 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16211.047748 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.066667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.812500 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 7 # 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miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 86329 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 290675 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 86329 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 290675 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082267 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454322 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.235683 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082301 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775218 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569383 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082301 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775218 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569383 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64063.599268 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54981.832056 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 56845.760656 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91653.434033 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91653.434033 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.569413 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64029.498733 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55055.575742 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 56896.340583 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91814.472508 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91814.472508 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64029.498733 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85428.330057 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 84510.132804 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64029.498733 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85428.330057 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 84510.132804 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -456,84 +456,84 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks system.cpu.l2cache.writebacks::total 113997 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7107 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7102 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27521 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34623 # 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number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33754882 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33754882 # number of overall hits -system.cpu.dcache.overall_hits::total 33754882 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96369 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96369 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1038764 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1038764 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1135133 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1135133 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1135133 # number of overall misses -system.cpu.dcache.overall_misses::total 1135133 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3867683500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3867683500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 76704328000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 76704328000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80572011500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80572011500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80572011500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80572011500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 4078.188542 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995651 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995651 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180240 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180240 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574610 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574610 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754850 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754850 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754850 # number of overall hits +system.cpu.dcache.overall_hits::total 33754850 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96398 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96398 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038767 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135165 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135165 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135165 # number of overall misses +system.cpu.dcache.overall_misses::total 1135165 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3869387500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3869387500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 76774000000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 76774000000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80643387500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80643387500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80643387500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80643387500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -542,56 +542,56 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004753 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004753 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004754 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004754 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40134.104328 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40134.104328 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73841.919820 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73841.919820 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70980.238879 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70980.238879 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70980.238879 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5030125 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.707255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.707255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73908.778388 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73908.778388 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71041.115168 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71041.115168 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5035459 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116378 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116380 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.222301 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.267391 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168350 # number of writebacks -system.cpu.dcache.writebacks::total 168350 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35604 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35604 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895184 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895184 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930788 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930788 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930788 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930788 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60765 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60765 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks +system.cpu.dcache.writebacks::total 168351 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35632 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35632 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895187 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895187 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930819 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930819 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930819 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930819 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204345 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204345 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204345 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204345 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1908276000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1908276000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12268587000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12268587000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14176863000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14176863000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14176863000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14176863000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910017000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910017000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12290144000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12290144000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14200161000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14200161000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14200161000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14200161000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -600,14 +600,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31404.196495 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31404.196495 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85447.743418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85447.743418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69377.097556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 69377.097556 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31432.330580 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31432.330580 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85597.882713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85597.882713 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 9f30fe52b..d2c7ef690 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -479,6 +479,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -511,6 +512,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -518,25 +520,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index 86a8209ba..dfc94d274 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:35:07 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 22:56:39 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24414646000 because target called exit() +Exiting @ tick 23931821000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index b5df8dc7b..8eb5d8593 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023888 # Number of seconds simulated -sim_ticks 23888231000 # Number of ticks simulated -final_tick 23888231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023932 # Number of seconds simulated +sim_ticks 23931821000 # Number of ticks simulated +final_tick 23931821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183235 # Simulator instruction rate (inst/s) -host_op_rate 183235 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54995028 # Simulator tick rate (ticks/s) -host_mem_usage 260452 # Number of bytes of host memory used -host_seconds 434.37 # Real time elapsed on the host +host_inst_rate 61921 # Simulator instruction rate (inst/s) +host_op_rate 61921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18618559 # Simulator tick rate (ticks/s) +host_mem_usage 281736 # Number of bytes of host memory used +host_seconds 1285.37 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 490944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154112 # Number of bytes read from this memory -system.physmem.bytes_read::total 10645056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 490944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 490944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158658 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166329 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20551710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 425067557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 445619267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20551710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20551710 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 305457194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 305457194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 305457194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20551710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 425067557 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 751076461 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166329 # Total number of read requests seen -system.physmem.writeReqs 114013 # Total number of write requests seen -system.physmem.cpureqs 280342 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10645056 # Total number of bytes read from memory -system.physmem.bytesWritten 7296832 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10645056 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296832 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 4 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10154048 # Number of bytes read from this memory +system.physmem.bytes_read::total 10644032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158657 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166313 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 20474163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 424290655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 444764818 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 20474163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 20474163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 304906175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 304906175 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 304906175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 20474163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 424290655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 749670992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166313 # Total number of read requests seen +system.physmem.writeReqs 114015 # Total number of write requests seen +system.physmem.cpureqs 280328 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10644032 # Total number of bytes read from memory +system.physmem.bytesWritten 7296960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10644032 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10521 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10582 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10798 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10348 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10490 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10474 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 10648 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10321 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10258 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10407 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10349 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10476 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10565 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10397 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10153 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9976 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10152 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10114 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7244 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7026 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7024 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7009 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6935 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6937 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7276 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23888198000 # Total gap between requests +system.physmem.totGap 23931788000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166329 # Categorize read packet sizes +system.physmem.readPktSize::6 166313 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114013 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 67947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7700 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114015 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 67890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,14 +124,14 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4948 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4957 # What write queue length does an incoming req see @@ -147,65 +147,65 @@ system.physmem.wrQLenPdf::19 4957 # Wh system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 617 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 7273642250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9818352250 # Sum of mem lat for all requests -system.physmem.totBusLat 831625000 # Total cycles spent in databus access -system.physmem.totBankLat 1713085000 # Total cycles spent in bank access -system.physmem.avgQLat 43731.50 # Average queueing delay per request -system.physmem.avgBankLat 10299.62 # Average bank access latency per request +system.physmem.totQLat 7245305500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 9792324250 # Sum of mem lat for all requests +system.physmem.totBusLat 831555000 # Total cycles spent in databus access +system.physmem.totBankLat 1715463750 # Total cycles spent in bank access +system.physmem.avgQLat 43564.80 # Average queueing delay per request +system.physmem.avgBankLat 10314.79 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 59031.13 # Average memory access latency -system.physmem.avgRdBW 445.62 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 305.46 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 445.62 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 305.46 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 58879.59 # Average memory access latency +system.physmem.avgRdBW 444.76 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 304.91 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 444.76 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 304.91 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.87 # Data bus utilization in percentage +system.physmem.busUtil 5.86 # Data bus utilization in percentage system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 10.09 # Average write queue length over time -system.physmem.readRowHits 149212 # Number of row buffer hits during reads -system.physmem.writeRowHits 70966 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.24 # Row buffer hit rate for writes -system.physmem.avgGap 85210.91 # Average gap between requests -system.cpu.branchPred.lookups 16542734 # Number of BP lookups -system.cpu.branchPred.condPredicted 10685518 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 416834 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11542683 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7340422 # Number of BTB hits +system.physmem.avgWrQLen 9.84 # Average write queue length over time +system.physmem.readRowHits 149147 # Number of row buffer hits during reads +system.physmem.writeRowHits 70867 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.16 # Row buffer hit rate for writes +system.physmem.avgGap 85370.67 # Average gap between requests +system.cpu.branchPred.lookups 16571170 # Number of BP lookups +system.cpu.branchPred.condPredicted 10694499 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 427048 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11996955 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7368452 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.593724 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1986948 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41598 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.419352 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1995064 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41482 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22395624 # DTB read hits -system.cpu.dtb.read_misses 219289 # DTB read misses -system.cpu.dtb.read_acv 61 # DTB read access violations -system.cpu.dtb.read_accesses 22614913 # DTB read accesses -system.cpu.dtb.write_hits 15707380 # DTB write hits -system.cpu.dtb.write_misses 41224 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15748604 # DTB write accesses -system.cpu.dtb.data_hits 38103004 # DTB hits -system.cpu.dtb.data_misses 260513 # DTB misses -system.cpu.dtb.data_acv 62 # DTB access violations -system.cpu.dtb.data_accesses 38363517 # DTB accesses -system.cpu.itb.fetch_hits 13912342 # ITB hits -system.cpu.itb.fetch_misses 34675 # ITB misses +system.cpu.dtb.read_hits 22414538 # DTB read hits +system.cpu.dtb.read_misses 219003 # DTB read misses +system.cpu.dtb.read_acv 44 # DTB read access violations +system.cpu.dtb.read_accesses 22633541 # DTB read accesses +system.cpu.dtb.write_hits 15711620 # DTB write hits +system.cpu.dtb.write_misses 41172 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 15752792 # DTB write accesses +system.cpu.dtb.data_hits 38126158 # DTB hits +system.cpu.dtb.data_misses 260175 # DTB misses +system.cpu.dtb.data_acv 46 # DTB access violations +system.cpu.dtb.data_accesses 38386333 # DTB accesses +system.cpu.itb.fetch_hits 13959521 # ITB hits +system.cpu.itb.fetch_misses 35718 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13947017 # ITB accesses +system.cpu.itb.fetch_accesses 13995239 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,98 +219,98 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 47776465 # number of cpu cycles simulated +system.cpu.numCycles 47863646 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15792140 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105356372 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16542734 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9327370 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19544101 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1999173 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6408053 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7580 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 309115 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13912342 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 209427 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43512690 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.421279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.137905 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15840434 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105551509 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16571170 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9363516 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19590320 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2026285 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6404003 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7727 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 314524 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13959521 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 209834 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43625903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.419469 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.136822 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23968589 55.08% 55.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1529417 3.51% 58.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1370330 3.15% 61.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1513065 3.48% 65.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4135878 9.50% 74.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846880 4.24% 78.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 674126 1.55% 80.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070808 2.46% 82.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7403597 17.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24035583 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1538195 3.53% 58.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1379254 3.16% 61.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510848 3.46% 65.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4145444 9.50% 74.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1853786 4.25% 79.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 680324 1.56% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1070140 2.45% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7412329 16.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43512690 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346253 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.205194 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16866618 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5950644 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18537765 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 810794 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1346869 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3745393 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107096 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103623154 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 304519 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1346869 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17322284 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3660735 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85948 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18844978 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2251876 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102372237 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 493 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2675 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2125269 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61644392 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123362389 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122911717 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 450672 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43625903 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.346216 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.205254 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16922417 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5946391 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18583818 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 809277 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1364000 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3756330 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107588 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103803150 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 305479 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1364000 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17385205 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3661755 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 85469 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18882151 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2247323 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102504062 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 474 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2634 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2121433 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61730148 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123523109 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123071072 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 452037 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9097511 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5543 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5541 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4645908 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23234130 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16272775 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1204976 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 463178 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90743430 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5284 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88424765 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 96747 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10698511 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4674782 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43512690 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.032160 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.108847 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9183267 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5533 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4628434 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23258454 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16285736 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1194307 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 458239 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90833658 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5326 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88506663 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 99992 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10775029 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4713260 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43625903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.028764 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.109591 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15237669 35.02% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6914925 15.89% 50.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5623850 12.92% 63.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4759728 10.94% 74.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4676300 10.75% 85.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2652660 6.10% 91.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1932814 4.44% 96.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1300380 2.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 414364 0.95% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15319091 35.11% 35.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6943764 15.92% 51.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5619916 12.88% 63.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4753240 10.90% 74.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4687288 10.74% 85.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2648310 6.07% 91.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1927283 4.42% 96.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1307141 3.00% 99.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 419870 0.96% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43512690 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43625903 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 125555 6.75% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126036 6.75% 6.75% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available @@ -339,19 +339,19 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.75% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 785994 42.27% 49.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 947743 50.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 786436 42.09% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 955888 51.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49355125 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43912 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49401565 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43900 0.05% 55.87% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121242 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 91 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121107 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38943 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121291 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121091 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38958 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -373,84 +373,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22848081 25.84% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15896208 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22873159 25.84% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15906558 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88424765 # Type of FU issued -system.cpu.iq.rate 1.850802 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1859292 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021027 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 221714954 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101050466 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86544122 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603305 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 414877 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294005 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 89982323 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301734 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1469012 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88506663 # Type of FU issued +system.cpu.iq.rate 1.849142 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1868360 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021110 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 222003769 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101216135 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86588999 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603812 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 415953 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294156 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90073048 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 301975 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1468681 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2957492 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4689 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18546 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1659398 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2981816 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4834 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18324 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1672359 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2825 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 92449 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2816 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 91767 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1346869 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2686448 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74137 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100230193 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 219543 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23234130 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16272775 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5284 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60080 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 507 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18546 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 196235 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160668 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 356903 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87583307 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22618160 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 841458 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1364000 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2689383 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 74209 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100326423 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 230599 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23258454 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16285736 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5326 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60174 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 487 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18324 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 205931 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161115 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 367046 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87639637 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22636834 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 867026 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9481479 # number of nop insts executed -system.cpu.iew.exec_refs 38367101 # number of memory reference insts executed -system.cpu.iew.exec_branches 15084952 # Number of branches executed -system.cpu.iew.exec_stores 15748941 # Number of stores executed -system.cpu.iew.exec_rate 1.833189 # Inst execution rate -system.cpu.iew.wb_sent 87228229 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86838127 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33365194 # num instructions producing a value -system.cpu.iew.wb_consumers 43783216 # num instructions consuming a value +system.cpu.iew.exec_nop 9487439 # number of nop insts executed +system.cpu.iew.exec_refs 38389952 # number of memory reference insts executed +system.cpu.iew.exec_branches 15091410 # Number of branches executed +system.cpu.iew.exec_stores 15753118 # Number of stores executed +system.cpu.iew.exec_rate 1.831027 # Inst execution rate +system.cpu.iew.wb_sent 87274889 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86883155 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33355142 # num instructions producing a value +system.cpu.iew.wb_consumers 43763107 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.817592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762054 # average fanout of values written-back +system.cpu.iew.wb_rate 1.815222 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762175 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8889017 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8976597 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 312044 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42165821 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.095078 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.806430 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 322215 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42261903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.090315 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.803165 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19296165 45.76% 45.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7025692 16.66% 62.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3426859 8.13% 70.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2055479 4.87% 75.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2052042 4.87% 80.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1160972 2.75% 83.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1093221 2.59% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 720657 1.71% 87.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5334734 12.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 19374336 45.84% 45.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7031479 16.64% 62.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3426891 8.11% 70.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2063946 4.88% 75.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2064090 4.88% 80.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1160431 2.75% 83.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1098411 2.60% 85.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 723960 1.71% 87.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5318359 12.58% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42165821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42261903 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,192 +461,192 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5334734 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5318359 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132743434 # The number of ROB reads -system.cpu.rob.rob_writes 195808907 # The number of ROB writes -system.cpu.timesIdled 70658 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4263775 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 132943471 # The number of ROB reads +system.cpu.rob.rob_writes 196001226 # The number of ROB writes +system.cpu.timesIdled 70501 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 4237743 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.600269 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.600269 # CPI: Total CPI of All Threads -system.cpu.ipc 1.665920 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.665920 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115915036 # number of integer regfile reads -system.cpu.int_regfile_writes 57508829 # number of integer regfile writes -system.cpu.fp_regfile_reads 249335 # number of floating regfile reads -system.cpu.fp_regfile_writes 239876 # number of floating regfile writes +system.cpu.cpi 0.601364 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.601364 # CPI: Total CPI of All Threads +system.cpu.ipc 1.662885 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.662885 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115989230 # number of integer regfile reads +system.cpu.int_regfile_writes 57546941 # number of integer regfile writes +system.cpu.fp_regfile_reads 249538 # number of floating regfile reads +system.cpu.fp_regfile_writes 239891 # number of floating regfile writes system.cpu.misc_regfile_reads 38020 # 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number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13806208 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13806208 # number of overall hits -system.cpu.icache.overall_hits::total 13806208 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 106133 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 106133 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 106133 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 106133 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 106133 # number of overall misses -system.cpu.icache.overall_misses::total 106133 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1879500499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1879500499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1879500499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1879500499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1879500499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1879500499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13912341 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13912341 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13912341 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13912341 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13912341 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13912341 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007629 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007629 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007629 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007629 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007629 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007629 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17708.917104 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17708.917104 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17708.917104 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17708.917104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17708.917104 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17708.917104 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 329 # number of cycles access was blocked +system.cpu.icache.replacements 91116 # number of replacements +system.cpu.icache.tagsinuse 1928.908016 # Cycle average of tags in use +system.cpu.icache.total_refs 13854125 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 93164 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 148.706850 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 19689670000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1928.908016 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.941850 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.941850 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13854125 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13854125 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13854125 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13854125 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13854125 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1863166499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13959520 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13959520 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13959520 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13959520 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13959520 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13959520 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007550 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007550 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007550 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007550 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007550 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007550 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.940120 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17677.940120 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.940120 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17677.940120 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.940120 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17677.940120 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 817 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14 # 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number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93652 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 93652 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 93652 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 93652 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 93652 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 93652 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1448205000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1448205000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1448205000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1448205000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1448205000 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15463.684705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15463.684705 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15463.684705 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12230 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12230 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12230 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12230 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12230 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12230 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 93165 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 93165 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 93165 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 93165 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 93165 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 93165 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1451229000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1451229000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1451229000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1451229000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1451229000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1451229000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006674 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006674 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006674 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006674 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006674 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006674 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15576.976332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15576.976332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15576.976332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15576.976332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15576.976332 # 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Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26654.476755 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2125.293059 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 2044.360903 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.813430 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.064859 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.062389 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.940678 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 85980 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34244 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120224 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168922 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168922 # 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Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995249 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995249 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20636989 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20636989 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574068 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574068 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 58 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 58 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34211057 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34211057 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34211057 # number of overall hits +system.cpu.dcache.overall_hits::total 34211057 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 267186 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 267186 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1039309 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1039309 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1306495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1306495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1306495 # number of overall misses +system.cpu.dcache.overall_misses::total 1306495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12035490500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12035490500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 79072087779 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 79072087779 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91107578279 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91107578279 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91107578279 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91107578279 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20904175 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20904175 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 60 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 60 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35497486 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35497486 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35497486 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35497486 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071121 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071121 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036801 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036801 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036801 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036801 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45186.784482 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45186.784482 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76224.904218 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76224.904218 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69880.492427 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69880.492427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69880.492427 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69880.492427 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4400680 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35517552 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35517552 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35517552 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35517552 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012781 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012781 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036784 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036784 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036784 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036784 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45045.363530 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 45045.363530 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76081.403874 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76081.403874 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69734.348986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69734.348986 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4381626 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112252 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112316 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.203578 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.011592 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168922 # number of writebacks -system.cpu.dcache.writebacks::total 168922 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204918 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 204918 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895901 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895901 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100819 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100819 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100819 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100819 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62109 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62109 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143421 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143421 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205530 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205530 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205530 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205530 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2021126000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2021126000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12474690492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12474690492 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14495816492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14495816492 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14495816492 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14495816492 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002974 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002974 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005790 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32541.596226 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32541.596226 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86979.525258 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86979.525258 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70528.956804 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70528.956804 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70528.956804 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70528.956804 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 168939 # number of writebacks +system.cpu.dcache.writebacks::total 168939 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205002 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 205002 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895906 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895906 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100908 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100908 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100908 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100908 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62184 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62184 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143403 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143403 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205587 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205587 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205587 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205587 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2020761500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2020761500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12440224991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12440224991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14460986491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14460986491 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14460986491 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14460986491 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005788 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005788 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32496.486234 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32496.486234 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86750.102794 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86750.102794 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 39e20487b..9ae4cf5ba 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -528,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index b6a1a957f..e45cd058f 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections -warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4] hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 9f7f9be51..862f6a349 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 3 2013 21:21:53 -gem5 started Mar 4 2013 01:35:26 -gem5 executing on zizzer +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 02:50:34 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 25578307500 because target called exit() +Exiting @ tick 25534556000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index f9d46e356..ba9e20c75 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025579 # Number of seconds simulated -sim_ticks 25578679000 # Number of ticks simulated -final_tick 25578679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.025535 # Number of seconds simulated +sim_ticks 25534556000 # Number of ticks simulated +final_tick 25534556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106593 # Simulator instruction rate (inst/s) -host_op_rate 151269 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38451628 # Simulator tick rate (ticks/s) -host_mem_usage 298528 # Number of bytes of host memory used -host_seconds 665.22 # Real time elapsed on the host +host_inst_rate 42425 # Simulator instruction rate (inst/s) +host_op_rate 60207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15277801 # Simulator tick rate (ticks/s) +host_mem_usage 296924 # Number of bytes of host memory used +host_seconds 1671.35 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128776 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11654707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 310553645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 322208352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11654707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11654707 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 210029924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 210029924 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 210029924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11654707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 310553645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 532238275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128777 # Total number of read requests seen -system.physmem.writeReqs 83942 # Total number of write requests seen -system.physmem.cpureqs 213038 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241664 # Total number of bytes read from memory -system.physmem.bytesWritten 5372288 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 297536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 297536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 297536 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128765 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11652288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 311085260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322737548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11652288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11652288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210400369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210400369 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210400369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11652288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 311085260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 533137917 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128766 # Total number of read requests seen +system.physmem.writeReqs 83945 # Total number of write requests seen +system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8240960 # Total number of bytes read from memory +system.physmem.bytesWritten 5372480 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8240960 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372480 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8192 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8047 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7986 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 325 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 7974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8181 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8060 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8007 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7985 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7981 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7987 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5142 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 8125 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7988 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7948 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5143 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5260 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5372 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5374 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5312 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25578660500 # Total gap between requests +system.physmem.totGap 25534539500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128777 # Categorize read packet sizes +system.physmem.readPktSize::6 128766 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83942 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56559 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83945 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2075 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,10 +124,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3638 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see @@ -139,53 +139,53 @@ system.physmem.wrQLenPdf::11 3650 # Wh system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3210060500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5252104250 # Sum of mem lat for all requests -system.physmem.totBusLat 643875000 # Total cycles spent in databus access -system.physmem.totBankLat 1398168750 # Total cycles spent in bank access -system.physmem.avgQLat 24927.67 # Average queueing delay per request -system.physmem.avgBankLat 10857.45 # Average bank access latency per request +system.physmem.totQLat 3209266500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5253345250 # Sum of mem lat for all requests +system.physmem.totBusLat 643820000 # Total cycles spent in databus access +system.physmem.totBankLat 1400258750 # Total cycles spent in bank access +system.physmem.avgQLat 24923.63 # Average queueing delay per request +system.physmem.avgBankLat 10874.61 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40785.12 # Average memory access latency -system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 210.03 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 40798.25 # Average memory access latency +system.physmem.avgRdBW 322.74 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 210.40 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 322.74 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 210.40 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.16 # Data bus utilization in percentage +system.physmem.busUtil 4.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.21 # Average read queue length over time -system.physmem.avgWrQLen 9.59 # Average write queue length over time -system.physmem.readRowHits 116755 # Number of row buffer hits during reads -system.physmem.writeRowHits 52878 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes -system.physmem.avgGap 120246.24 # Average gap between requests -system.cpu.branchPred.lookups 16623550 # Number of BP lookups -system.cpu.branchPred.condPredicted 12760225 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 602776 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10462790 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7764993 # Number of BTB hits +system.physmem.avgWrQLen 9.90 # Average write queue length over time +system.physmem.readRowHits 116738 # Number of row buffer hits during reads +system.physmem.writeRowHits 52892 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 63.01 # Row buffer hit rate for writes +system.physmem.avgGap 120043.34 # Average gap between requests +system.cpu.branchPred.lookups 16612549 # Number of BP lookups +system.cpu.branchPred.condPredicted 12751503 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 599939 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10534593 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7757405 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.215319 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825730 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.637444 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1822464 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113740 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 51157359 # number of cpu cycles simulated +system.cpu.numCycles 51069113 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12528196 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85178151 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16623550 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9590723 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21186766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2362966 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10580824 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 65 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 592 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11675240 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179625 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46030286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.591135 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335079 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12514698 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85141272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16612549 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9579869 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21174766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2353264 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10532726 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 498 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11663165 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 178973 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 45949088 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.594403 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24863758 54.02% 54.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2136664 4.64% 58.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1964751 4.27% 62.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2042058 4.44% 67.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1465237 3.18% 70.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1378794 3.00% 73.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 958007 2.08% 75.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1192757 2.59% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10028260 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24794811 53.96% 53.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2137100 4.65% 58.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1960912 4.27% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2040333 4.44% 67.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1467005 3.19% 70.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1375299 2.99% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 957293 2.08% 75.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1188429 2.59% 78.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10027906 21.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46030286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324949 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.665022 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14611843 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8929429 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19464778 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1393400 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1630836 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3329843 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104767 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116826409 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 364015 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1630836 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16323672 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2560343 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 881200 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19095931 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5538304 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114955778 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 16357 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4684077 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115266627 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529628092 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529622760 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 45949088 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.325295 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.667177 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14598305 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8880724 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19456140 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1390682 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1623237 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3327841 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 105063 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116768795 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 361627 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1623237 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16304725 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2541710 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 873067 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19090805 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5515544 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114897326 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 145 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17204 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4661371 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115217977 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529361609 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529355204 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6405 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16133955 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20202 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20198 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13085199 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29620303 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22433978 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3897320 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4410132 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111515414 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35833 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107233709 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 271611 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10777789 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25822592 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2047 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46030286 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.329634 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.987559 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16085305 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20097 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20095 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13032825 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29592002 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22430174 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3871274 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4372916 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111465960 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35763 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107205683 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272681 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10729594 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25689486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1977 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 45949088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.333141 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.988541 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10772482 23.40% 23.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8089494 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7436899 16.16% 57.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7132502 15.50% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5411548 11.76% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3908660 8.49% 92.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839023 4.00% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 868143 1.89% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 571535 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10727081 23.35% 23.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8071190 17.57% 40.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7423915 16.16% 57.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7121409 15.50% 72.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5405073 11.76% 84.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3914653 8.52% 92.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842463 4.01% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 872331 1.90% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 570973 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46030286 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 45949088 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112260 4.55% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1357456 55.03% 59.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 996870 40.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112030 4.53% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1365116 55.14% 59.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 998484 40.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56624482 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91603 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56613299 52.81% 52.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91558 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 214 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -384,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28897893 26.95% 79.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21619537 20.16% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28880685 26.94% 79.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21619920 20.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107233709 # Type of FU issued -system.cpu.iq.rate 2.096154 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2466586 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023002 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263235386 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122356888 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105553525 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109700035 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2179098 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107205683 # Type of FU issued +system.cpu.iq.rate 2.099227 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2475632 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023092 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263108179 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122259769 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105531184 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 588 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 948 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 171 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109681022 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2183832 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2313195 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6752 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29821 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1878240 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2284894 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30581 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1874436 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 495 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1630836 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1047773 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45606 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111560996 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 293586 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29620303 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22433978 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19913 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6800 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5244 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29821 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391475 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181717 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573192 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106207305 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28598865 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1026404 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1623237 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1048241 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45255 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111511491 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 294294 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29592002 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22430174 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19843 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6298 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5233 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30581 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 389128 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 180293 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 569421 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106181677 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28584422 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1024006 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9749 # number of nop insts executed -system.cpu.iew.exec_refs 49933799 # number of memory reference insts executed -system.cpu.iew.exec_branches 14599943 # Number of branches executed -system.cpu.iew.exec_stores 21334934 # Number of stores executed -system.cpu.iew.exec_rate 2.076090 # Inst execution rate -system.cpu.iew.wb_sent 105772568 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105553695 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53290851 # num instructions producing a value -system.cpu.iew.wb_consumers 103571318 # num instructions consuming a value +system.cpu.iew.exec_nop 9768 # number of nop insts executed +system.cpu.iew.exec_refs 49919694 # number of memory reference insts executed +system.cpu.iew.exec_branches 14596236 # Number of branches executed +system.cpu.iew.exec_stores 21335272 # Number of stores executed +system.cpu.iew.exec_rate 2.079176 # Inst execution rate +system.cpu.iew.wb_sent 105750985 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105531355 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53247115 # num instructions producing a value +system.cpu.iew.wb_consumers 103478593 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.063314 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back +system.cpu.iew.wb_rate 2.066442 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514571 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10929447 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10879947 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 499822 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44399450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266524 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764020 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 496884 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44325851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.270288 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.765576 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15322466 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11640372 26.22% 60.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3466304 7.81% 68.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2879944 6.49% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1880994 4.24% 79.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1947998 4.39% 83.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685125 1.54% 85.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 565076 1.27% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6011171 13.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15270109 34.45% 34.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11622337 26.22% 60.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3461272 7.81% 68.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2876318 6.49% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1875937 4.23% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1955484 4.41% 83.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 687541 1.55% 85.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 562645 1.27% 86.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6014208 13.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44399450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44325851 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,204 +472,204 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6011171 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6014208 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149924855 # The number of ROB reads -system.cpu.rob.rob_writes 224763597 # The number of ROB writes -system.cpu.timesIdled 74024 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5127073 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149798719 # The number of ROB reads +system.cpu.rob.rob_writes 224657070 # The number of ROB writes +system.cpu.timesIdled 74104 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5120025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.721465 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.721465 # CPI: Total CPI of All Threads -system.cpu.ipc 1.386069 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.386069 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511541679 # number of integer regfile reads -system.cpu.int_regfile_writes 103323268 # number of integer regfile writes -system.cpu.fp_regfile_reads 788 # number of floating regfile reads -system.cpu.fp_regfile_writes 660 # number of floating regfile writes -system.cpu.misc_regfile_reads 49173958 # number of misc regfile reads +system.cpu.cpi 0.720220 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.720220 # CPI: Total CPI of All Threads +system.cpu.ipc 1.388464 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.388464 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511419514 # number of integer regfile reads +system.cpu.int_regfile_writes 103305187 # number of integer regfile writes +system.cpu.fp_regfile_reads 846 # number of floating regfile reads +system.cpu.fp_regfile_writes 738 # number of floating regfile writes +system.cpu.misc_regfile_reads 49163804 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 28620 # number of replacements -system.cpu.icache.tagsinuse 1814.215623 # Cycle average of tags in use -system.cpu.icache.total_refs 11640482 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30656 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379.713009 # Average number of references to valid blocks. +system.cpu.icache.replacements 28595 # number of replacements +system.cpu.icache.tagsinuse 1814.564534 # Cycle average of tags in use +system.cpu.icache.total_refs 11628419 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30629 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379.653890 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.215623 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885847 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885847 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11640487 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11640487 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11640487 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11640487 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11640487 # number of overall hits -system.cpu.icache.overall_hits::total 11640487 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34753 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34753 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34753 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34753 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34753 # number of overall misses -system.cpu.icache.overall_misses::total 34753 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 732473500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 732473500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 732473500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 732473500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 732473500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 732473500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11675240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11675240 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11675240 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11675240 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11675240 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11675240 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002977 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002977 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002977 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002977 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002977 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002977 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21076.554542 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21076.554542 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21076.554542 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21076.554542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21076.554542 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21076.554542 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 767 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1814.564534 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.886018 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.886018 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11628429 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11628429 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11628429 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11628429 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11628429 # number of overall hits +system.cpu.icache.overall_hits::total 11628429 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34736 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34736 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34736 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34736 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34736 # number of overall misses +system.cpu.icache.overall_misses::total 34736 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 739851499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 739851499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 739851499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 739851499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 739851499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 739851499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11663165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11663165 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11663165 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11663165 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11663165 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11663165 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002978 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002978 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002978 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002978 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002978 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002978 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21299.271620 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21299.271620 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21299.271620 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21299.271620 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21299.271620 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21299.271620 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1371 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 24 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.958333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 65.285714 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3764 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3764 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3764 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3764 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3764 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3764 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30989 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 30989 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 30989 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 30989 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 30989 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 30989 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 594730000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 594730000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 594730000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 594730000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 594730000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 594730000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002654 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002654 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002654 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002654 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19191.648650 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19191.648650 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19191.648650 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19191.648650 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19191.648650 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19191.648650 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3776 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3776 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3776 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3776 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3776 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3776 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30960 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 30960 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 30960 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 30960 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 30960 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 30960 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 598675999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 598675999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 598675999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 598675999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 598675999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 598675999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002655 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002655 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002655 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19337.080071 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19337.080071 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19337.080071 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19337.080071 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19337.080071 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19337.080071 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95648 # number of replacements -system.cpu.l2cache.tagsinuse 30089.528668 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88145 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53223.581535 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53203.017876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52655.192101 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53223.581535 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53203.017876 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 128767 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250601778 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209164905 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1459766683 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3249822 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3249822 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5391078264 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5391078264 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250601778 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6600243169 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6850844947 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250601778 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6600243169 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6850844947 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394982 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309055 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955313 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955313 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764292 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.667771 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764292 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.667771 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53904.447838 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55296.332602 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55052.296085 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.314815 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.314815 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52723.966162 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52723.966162 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53904.447838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53177.163417 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53203.421273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53904.447838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53177.163417 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53203.421273 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158317 # number of replacements -system.cpu.dcache.tagsinuse 4072.315940 # Cycle average of tags in use -system.cpu.dcache.total_refs 44364640 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162413 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.159415 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 284606000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.315940 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994218 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26064832 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26064832 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18267213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18267213 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15986 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15986 # number of LoadLockedReq hits +system.cpu.dcache.replacements 158299 # number of replacements +system.cpu.dcache.tagsinuse 4072.272113 # Cycle average of tags in use +system.cpu.dcache.total_refs 44344927 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162395 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.068303 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 284501000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.272113 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994207 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994207 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26045311 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26045311 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18267055 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18267055 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15985 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15985 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44332045 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44332045 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44332045 # number of overall hits -system.cpu.dcache.overall_hits::total 44332045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124417 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1582688 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1582688 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707105 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707105 # number of overall misses -system.cpu.dcache.overall_misses::total 1707105 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4247904000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4247904000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98406408482 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98406408482 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1297000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102654312482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102654312482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102654312482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102654312482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26189249 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26189249 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44312366 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44312366 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44312366 # number of overall hits +system.cpu.dcache.overall_hits::total 44312366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 124674 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 124674 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1582846 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1582846 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1707520 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707520 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707520 # number of overall misses +system.cpu.dcache.overall_misses::total 1707520 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4256897000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4256897000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98390757481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98390757481 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 860000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 860000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102647654481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102647654481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102647654481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102647654481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26169985 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26169985 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16031 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16031 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46039150 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46039150 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46039150 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46039150 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004751 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004751 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079733 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079733 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002807 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002807 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037079 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037079 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037079 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037079 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34142.472492 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34142.472492 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62176.757821 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62176.757821 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28822.222222 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28822.222222 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60133.566759 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60133.566759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60133.566759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60133.566759 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5187 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46019886 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46019886 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46019886 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46019886 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079741 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079741 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002621 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002621 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037104 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037104 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037104 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037104 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34144.224137 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34144.224137 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.663439 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.663439 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20476.190476 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20476.190476 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.052521 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60115.052521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.052521 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60115.052521 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3743 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 131 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.516393 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.572519 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129090 # number of writebacks -system.cpu.dcache.writebacks::total 129090 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69000 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69000 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475354 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475354 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544354 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544354 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544354 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544354 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55417 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55417 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107334 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107334 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162751 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162751 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162751 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162751 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878666500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6813869491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6813869491 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8692535991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8692535991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8692535991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8692535991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33900.544959 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33900.544959 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63482.861824 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63482.861824 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53410.031219 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53410.031219 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 129075 # number of writebacks +system.cpu.dcache.writebacks::total 129075 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69278 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69278 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475504 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475504 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1544782 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544782 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544782 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544782 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55396 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55396 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107342 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107342 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162738 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162738 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162738 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162738 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878391000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878391000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809216990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809216990 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687607990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8687607990 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687607990 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8687607990 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33908.422991 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33908.422991 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.787781 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.787781 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.015964 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.015964 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.015964 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.015964 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |