diff options
Diffstat (limited to 'tests/long/se/50.vortex')
3 files changed, 1965 insertions, 1491 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 7d4bfa05d..14d4b21df 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,217 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.046793 # Number of seconds simulated -sim_ticks 46793182500 # Number of ticks simulated -final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.046394 # Number of seconds simulated +sim_ticks 46393648500 # Number of ticks simulated +final_tick 46393648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131801 # Simulator instruction rate (inst/s) -host_op_rate 131801 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69813482 # Simulator tick rate (ticks/s) -host_mem_usage 220956 # Number of bytes of host memory used -host_seconds 670.26 # Real time elapsed on the host +host_inst_rate 96549 # Simulator instruction rate (inst/s) +host_op_rate 96549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50704548 # Simulator tick rate (ticks/s) +host_mem_usage 252684 # Number of bytes of host memory used +host_seconds 914.98 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10272832 # Number of bytes read from this memory -system.physmem.bytes_read::total 10787712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 514880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 514880 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 514944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10272704 # Number of bytes read from this memory +system.physmem.bytes_read::total 10787648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 514944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 514944 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7422400 # Number of bytes written to this memory system.physmem.bytes_written::total 7422400 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8045 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160513 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 8046 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160511 # Number of read requests responded to by this memory +system.physmem.num_reads::total 168557 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 115975 # Number of write requests responded to by this memory system.physmem.num_writes::total 115975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11003312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 219536938 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 230540250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11003312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11003312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 158621397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 158621397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 158621397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11003312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 219536938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 389161648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 11099450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 221424793 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 232524243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11099450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11099450 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 159987417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 159987417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 159987417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11099450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 221424793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 392511660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168557 # Total number of read requests seen +system.physmem.writeReqs 115975 # Total number of write requests seen +system.physmem.cpureqs 284532 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10787648 # Total number of bytes read from memory +system.physmem.bytesWritten 7422400 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10787648 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7422400 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 12 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 10983 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10544 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10882 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10471 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10499 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10074 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10523 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10483 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10531 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10030 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10827 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10322 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7511 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7019 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7391 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7077 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7441 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7201 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7286 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7177 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7254 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7052 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7484 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7300 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 46393600000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 168557 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 115975 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 162958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 4989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 1271098054 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4666794054 # Sum of mem lat for all requests +system.physmem.totBusLat 674180000 # Total cycles spent in databus access +system.physmem.totBankLat 2721516000 # Total cycles spent in bank access +system.physmem.avgQLat 7541.59 # Average queueing delay per request +system.physmem.avgBankLat 16147.12 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 27688.71 # Average memory access latency +system.physmem.avgRdBW 232.52 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 159.99 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 232.52 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 159.99 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.45 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.10 # Average read queue length over time +system.physmem.avgWrQLen 10.39 # Average write queue length over time +system.physmem.readRowHits 152922 # Number of row buffer hits during reads +system.physmem.writeRowHits 84722 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.05 # Row buffer hit rate for writes +system.physmem.avgGap 163052.31 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277225 # DTB read hits +system.cpu.dtb.read_hits 20277224 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367373 # DTB read accesses -system.cpu.dtb.write_hits 14736820 # DTB write hits +system.cpu.dtb.read_accesses 20367372 # DTB read accesses +system.cpu.dtb.write_hits 14736801 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14744072 # DTB write accesses -system.cpu.dtb.data_hits 35014045 # DTB hits +system.cpu.dtb.write_accesses 14744053 # DTB write accesses +system.cpu.dtb.data_hits 35014025 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35111445 # DTB accesses -system.cpu.itb.fetch_hits 12477645 # ITB hits -system.cpu.itb.fetch_misses 12958 # ITB misses +system.cpu.dtb.data_accesses 35111425 # DTB accesses +system.cpu.itb.fetch_hits 12475425 # ITB hits +system.cpu.itb.fetch_misses 12954 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12490603 # ITB accesses +system.cpu.itb.fetch_accesses 12488379 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 93586366 # number of cpu cycles simulated +system.cpu.numCycles 92787298 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 18829185 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 12442057 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 5026145 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16204746 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 5047870 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 1660949 # Number of times the RAS was used to get a target. +system.cpu.branch_predictor.lookups 18828887 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 12440846 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 5023695 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 16217673 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 5047073 # Number of BTB hits +system.cpu.branch_predictor.usedRAS 1660946 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 1031 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 31.150565 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 8475762 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10353423 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74332851 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 31.120821 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 8474385 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10354502 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74331965 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126652101 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 65265 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126651215 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 65206 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 292895 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14120054 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35064610 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4681911 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 233734 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4915645 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 8856618 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 35.692355 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44775927 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 292836 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14119774 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35064022 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4679410 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 233785 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4913195 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 8859107 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 35.674465 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44776036 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 78075293 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 78069956 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 311800 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23300937 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 70285429 # Number of cycles cpu stages are processed. -system.cpu.activity 75.102210 # Percentage of cycles cpu is active +system.cpu.timesIdled 311324 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 22508104 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 70279194 # Number of cycles cpu stages are processed. +system.cpu.activity 75.742257 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -114,144 +272,144 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 1.059380 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.050335 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.059380 # CPI: Total CPI of All Threads -system.cpu.ipc 0.943948 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.050335 # CPI: Total CPI of All Threads +system.cpu.ipc 0.952077 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.943948 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 40161098 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 53425268 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 57.086593 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 50931554 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42654812 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 45.578019 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 50461046 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43125320 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 46.080772 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 71466223 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22120143 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 23.636074 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 47482076 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46104290 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 49.263896 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 85221 # number of replacements -system.cpu.icache.tagsinuse 1887.407088 # Cycle average of tags in use -system.cpu.icache.total_refs 12359392 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 87267 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.627328 # Average number of references to valid blocks. +system.cpu.ipc_total 0.952077 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 39364116 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 53423182 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 57.575965 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 50132225 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42655073 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.970811 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 49662532 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43124766 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 46.477015 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 70666607 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22120691 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 23.840215 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46683402 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 46103896 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 49.687723 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 85246 # number of replacements +system.cpu.icache.tagsinuse 1892.367381 # Cycle average of tags in use +system.cpu.icache.total_refs 12357191 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 87292 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 141.561552 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1887.407088 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.921585 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.921585 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12359392 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12359392 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12359392 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12359392 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12359392 # number of overall hits -system.cpu.icache.overall_hits::total 12359392 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 118206 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 118206 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 118206 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 118206 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 118206 # number of overall misses -system.cpu.icache.overall_misses::total 118206 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1871587000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1871587000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1871587000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1871587000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1871587000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1871587000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12477598 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12477598 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12477598 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12477598 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12477598 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12477598 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.009473 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.009473 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.009473 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.009473 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15833.265655 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15833.265655 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15833.265655 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1892.367381 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.924008 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.924008 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12357191 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12357191 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12357191 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12357191 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12357191 # number of overall hits +system.cpu.icache.overall_hits::total 12357191 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 118187 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 118187 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 118187 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 118187 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 118187 # number of overall misses +system.cpu.icache.overall_misses::total 118187 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1883931500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1883931500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1883931500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1883931500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1883931500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1883931500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12475378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12475378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12475378 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12475378 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12475378 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12475378 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009474 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009474 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009474 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009474 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009474 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009474 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15940.259927 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15940.259927 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15940.259927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15940.259927 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15940.259927 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 2050 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1882 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 108 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 21.808511 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 17.425926 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30939 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30939 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30939 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30939 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30939 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87267 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 87267 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 87267 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 87267 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 87267 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 87267 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1309592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1309592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1309592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1309592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1309592500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1309592500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006994 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006994 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006994 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006994 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15006.732213 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15006.732213 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15006.732213 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15006.732213 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30895 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 30895 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 30895 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 30895 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 30895 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 30895 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 87292 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 87292 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 87292 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 87292 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 87292 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 87292 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1323717000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1323717000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1323717000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1323717000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1323717000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1323717000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006997 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006997 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006997 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006997 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15164.241855 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15164.241855 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15164.241855 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15164.241855 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15164.241855 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15164.241855 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 200251 # number of replacements -system.cpu.dcache.tagsinuse 4072.865489 # Cycle average of tags in use -system.cpu.dcache.total_refs 34126021 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4074.773035 # Cycle average of tags in use +system.cpu.dcache.total_refs 34126001 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.000352 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 486992000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.865489 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994352 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994352 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20180532 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20180532 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13945489 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13945489 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34126021 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34126021 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34126021 # number of overall hits -system.cpu.dcache.overall_hits::total 34126021 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96106 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96106 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 667888 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 667888 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 763994 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 763994 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 763994 # number of overall misses -system.cpu.dcache.overall_misses::total 763994 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3881207000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3881207000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 34562623000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 34562623000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38443830000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38443830000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38443830000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38443830000 # number of overall miss cycles +system.cpu.dcache.avg_refs 167.000254 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 420616000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4074.773035 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994818 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994818 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20180529 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20180529 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13945472 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13945472 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34126001 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34126001 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34126001 # number of overall hits +system.cpu.dcache.overall_hits::total 34126001 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96109 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96109 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 667905 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 667905 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 764014 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 764014 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 764014 # number of overall misses +system.cpu.dcache.overall_misses::total 764014 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3658302500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3658302500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32880134000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32880134000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36538436500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36538436500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36538436500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36538436500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -262,38 +420,38 @@ system.cpu.dcache.overall_accesses::cpu.data 34890015 system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004740 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004740 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045704 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045704 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.021897 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.021897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.021897 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.021897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40384.648201 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40384.648201 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51749.130094 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51749.130094 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50319.544394 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 12521367 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 100.881952 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045705 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045705 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.021898 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.021898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.021898 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.021898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38064.099096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38064.099096 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49228.758581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 49228.758581 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47824.302303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47824.302303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47824.302303 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11803841 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 124100 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 271 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95.115560 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks -system.cpu.dcache.writebacks::total 165811 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35339 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35339 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524308 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 524308 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 559647 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 559647 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 559647 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 559647 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 165814 # number of writebacks +system.cpu.dcache.writebacks::total 165814 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35342 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35342 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 524325 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 524325 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 559667 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 559667 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 559667 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 559667 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses @@ -302,14 +460,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204347 system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1916080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1916080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7177771000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7177771000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9093851000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9093851000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9093851000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9093851000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1847026500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1847026500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6899064500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6899064500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8746091000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8746091000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8746091000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8746091000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -318,152 +476,152 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31531.587868 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31531.587868 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49991.440312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49991.440312 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44502.003944 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44502.003944 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30395.222736 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30395.222736 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48050.316897 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48050.316897 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 87267 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 87292 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 291614 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 87267 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 291639 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 87292 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 291614 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092188 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486414 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.253718 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 291639 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.092173 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.486381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.253669 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911511 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.911511 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092188 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.785492 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.578018 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092188 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.785492 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.578018 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53139.403356 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52285.973665 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52469.009091 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52692.610285 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52692.610285 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53139.403356 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52617.962408 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52642.849939 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53139.403356 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52617.962408 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52642.849939 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.092173 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.785483 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.577965 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.092173 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.785483 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.577965 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54854.523987 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 49937.805458 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50992.455345 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50569.448366 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50569.448366 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54854.523987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50453.501629 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50663.582646 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54854.523987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50453.501629 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50663.582646 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1238 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 309.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 115975 # number of writebacks system.cpu.l2cache.writebacks::total 115975 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8045 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29466 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37511 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8046 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29464 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37510 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131047 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 131047 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8045 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 160513 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168558 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8045 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160513 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168558 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329317000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1181708500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1511025500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5272374500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5272374500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6454083000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6783400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329317000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6454083000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6783400000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486414 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253718 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160511 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168557 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160511 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168557 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339209803 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1094048732 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1433258535 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4985919806 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4985919806 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339209803 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6079968538 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6419178341 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339209803 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6079968538 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6419178341 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.486381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253669 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911511 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911511 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.578018 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092188 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785492 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.578018 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40934.369173 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40104.136971 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40282.197222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40232.698955 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40232.698955 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40934.369173 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40209.098328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40243.714330 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.577965 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.092173 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.785483 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.577965 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42158.812205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37131.710969 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38210.038256 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38046.806154 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38046.806154 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42158.812205 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37878.827856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38083.131172 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 9eadbf92f..ce6ab2ad0 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,59 +1,217 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.021083 # Number of seconds simulated -sim_ticks 21083079000 # Number of ticks simulated -final_tick 21083079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021820 # Number of seconds simulated +sim_ticks 21820020000 # Number of ticks simulated +final_tick 21820020000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198104 # Simulator instruction rate (inst/s) -host_op_rate 198104 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52475767 # Simulator tick rate (ticks/s) -host_mem_usage 221996 # Number of bytes of host memory used -host_seconds 401.77 # Real time elapsed on the host +host_inst_rate 158943 # Simulator instruction rate (inst/s) +host_op_rate 158943 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43574235 # Simulator tick rate (ticks/s) +host_mem_usage 253708 # Number of bytes of host memory used +host_seconds 500.76 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 559552 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10295232 # Number of bytes read from this memory -system.physmem.bytes_read::total 10854784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 559552 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 559552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7426304 # Number of bytes written to this memory -system.physmem.bytes_written::total 7426304 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 160863 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169606 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116036 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116036 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 26540336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 488317290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 514857626 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 26540336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 26540336 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 352240012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 352240012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 352240012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 26540336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 488317290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867097638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 559680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10296000 # Number of bytes read from this memory +system.physmem.bytes_read::total 10855680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 559680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 559680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7426944 # Number of bytes written to this memory +system.physmem.bytes_written::total 7426944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 160875 # Number of read requests responded to by this memory +system.physmem.num_reads::total 169620 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116046 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116046 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 25649839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 471860246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 497510085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 25649839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 25649839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 340372924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 340372924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 340372924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 25649839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 471860246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 837883008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 169621 # Total number of read requests seen +system.physmem.writeReqs 116046 # Total number of write requests seen +system.physmem.cpureqs 285667 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10855680 # Total number of bytes read from memory +system.physmem.bytesWritten 7426944 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10855680 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7426944 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 11095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10656 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10958 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10512 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10822 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10578 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 10358 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10136 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10631 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10838 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10582 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10059 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10909 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10352 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7516 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7034 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7440 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7204 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7555 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 7178 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7051 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7488 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7299 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 21820003000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 169621 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 116046 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 0 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 66903 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 55166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7012 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 2256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 5060410122 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7401532122 # Sum of mem lat for all requests +system.physmem.totBusLat 678440000 # Total cycles spent in databus access +system.physmem.totBankLat 1662682000 # Total cycles spent in bank access +system.physmem.avgQLat 29835.56 # Average queueing delay per request +system.physmem.avgBankLat 9802.97 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 43638.54 # Average memory access latency +system.physmem.avgRdBW 497.51 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 340.37 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 497.51 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 340.37 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 5.24 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.34 # Average read queue length over time +system.physmem.avgWrQLen 10.53 # Average write queue length over time +system.physmem.readRowHits 153635 # Number of row buffer hits during reads +system.physmem.writeRowHits 84286 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.58 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.63 # Row buffer hit rate for writes +system.physmem.avgGap 76382.65 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22489278 # DTB read hits -system.cpu.dtb.read_misses 215924 # DTB read misses -system.cpu.dtb.read_acv 41 # DTB read access violations -system.cpu.dtb.read_accesses 22705202 # DTB read accesses -system.cpu.dtb.write_hits 15793400 # DTB write hits -system.cpu.dtb.write_misses 42287 # DTB write misses +system.cpu.dtb.read_hits 22500738 # DTB read hits +system.cpu.dtb.read_misses 216644 # DTB read misses +system.cpu.dtb.read_acv 44 # DTB read access violations +system.cpu.dtb.read_accesses 22717382 # DTB read accesses +system.cpu.dtb.write_hits 15795905 # DTB write hits +system.cpu.dtb.write_misses 41245 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 15835687 # DTB write accesses -system.cpu.dtb.data_hits 38282678 # DTB hits -system.cpu.dtb.data_misses 258211 # DTB misses -system.cpu.dtb.data_acv 41 # DTB access violations -system.cpu.dtb.data_accesses 38540889 # DTB accesses -system.cpu.itb.fetch_hits 14126698 # ITB hits -system.cpu.itb.fetch_misses 39196 # ITB misses +system.cpu.dtb.write_accesses 15837150 # DTB write accesses +system.cpu.dtb.data_hits 38296643 # DTB hits +system.cpu.dtb.data_misses 257889 # DTB misses +system.cpu.dtb.data_acv 44 # DTB access violations +system.cpu.dtb.data_accesses 38554532 # DTB accesses +system.cpu.itb.fetch_hits 14148494 # ITB hits +system.cpu.itb.fetch_misses 39336 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14165894 # ITB accesses +system.cpu.itb.fetch_accesses 14187830 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,146 +225,146 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 42166161 # number of cpu cycles simulated +system.cpu.numCycles 43640043 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16730416 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 10797894 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 473008 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 12422807 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7474415 # Number of BTB hits +system.cpu.BPredUnit.lookups 16741832 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 10806668 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477582 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 12162476 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7482577 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1997304 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 44664 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 15021331 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106728114 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16730416 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9471719 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19806820 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2130939 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5131628 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 8233 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 318680 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14126698 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 218104 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 41829396 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.551510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.168900 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1995510 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 45710 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 15036393 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106856108 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16741832 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9478087 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19828359 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2147542 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 4492220 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 8232 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 323266 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 14148494 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 220972 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 41243035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.590889 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.177319 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22022576 52.65% 52.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1548600 3.70% 56.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1408416 3.37% 59.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1521519 3.64% 63.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4198220 10.04% 73.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1858565 4.44% 77.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 685862 1.64% 79.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1087856 2.60% 82.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7497782 17.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21414676 51.92% 51.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1548321 3.75% 55.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1410779 3.42% 59.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1521748 3.69% 62.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4201075 10.19% 72.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1864766 4.52% 77.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 686260 1.66% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1087985 2.64% 81.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7507425 18.20% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 41829396 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.396774 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.531132 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16130863 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4679035 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18837705 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 745587 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1436206 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3804156 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108982 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104831583 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305633 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1436206 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16616599 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2463979 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 82005 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19040737 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2189870 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103389139 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 244 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 14351 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2051944 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 62312738 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124671441 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124212160 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 459281 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 41243035 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.383635 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.448579 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16096491 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4096982 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18769266 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 833511 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1446785 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3807119 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 110554 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104936406 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 308694 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1446785 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16548633 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1976361 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 82879 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19114757 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2073620 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 103469028 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 341 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14640 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 1956889 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 62372396 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124769861 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 124309039 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 460822 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9765857 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5555 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5551 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4525057 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23373120 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16387776 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1111175 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 372431 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91431067 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5402 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89032304 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 124930 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11266116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4904200 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 819 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 41829396 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.128463 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.117137 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9825515 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5546 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5543 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4207574 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23385563 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16393614 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1121004 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 386917 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91482649 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5403 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89074963 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 123031 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11309425 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4934372 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 820 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 41243035 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.159758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.116316 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13456265 32.17% 32.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6919123 16.54% 48.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5589725 13.36% 62.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4803253 11.48% 73.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4671765 11.17% 84.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2679732 6.41% 91.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1951840 4.67% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1334332 3.19% 98.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 423361 1.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12823282 31.09% 31.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6988742 16.95% 48.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5560534 13.48% 61.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4799338 11.64% 73.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4679683 11.35% 84.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2682377 6.50% 91.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1950315 4.73% 95.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1335480 3.24% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 423284 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 41829396 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 41243035 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 128041 6.73% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 804964 42.29% 49.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 970251 50.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 129257 6.79% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 803786 42.23% 49.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 970116 50.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49721701 55.85% 55.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43788 0.05% 55.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49746538 55.85% 55.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43785 0.05% 55.90% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.90% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121439 0.14% 56.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 86 0.00% 56.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 122461 0.14% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.17% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38932 0.04% 56.21% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121262 0.14% 56.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 122235 0.14% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 55 0.00% 56.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38920 0.04% 56.21% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.21% # Type of FU issued @@ -228,84 +386,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.21% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.21% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22979273 25.81% 82.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16004570 17.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22991531 25.81% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16010548 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89032304 # Type of FU issued -system.cpu.iq.rate 2.111463 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1903256 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021377 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 221310686 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102298169 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86978851 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611504 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420531 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 298097 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90629664 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305896 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1444097 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89074963 # Type of FU issued +system.cpu.iq.rate 2.041129 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1903159 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021366 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 220805862 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102391842 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87007224 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 613289 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 421743 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 298831 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90671357 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 306765 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1448727 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3096482 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5652 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17147 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1774399 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3108925 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5719 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 17139 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1780237 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2494 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 46 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2546 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 373 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1436206 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1444549 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 56493 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100968085 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 243573 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23373120 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16387776 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5402 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 48618 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 436 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17147 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 252218 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 171298 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 423516 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88057641 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22708636 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 974663 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1446785 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1296877 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 55540 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101030605 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 244499 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23385563 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16393614 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5403 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 48652 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 428 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 17139 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 253350 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 173638 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426988 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88093519 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22720865 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 981444 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9531616 # number of nop insts executed -system.cpu.iew.exec_refs 38544729 # number of memory reference insts executed -system.cpu.iew.exec_branches 15136263 # Number of branches executed -system.cpu.iew.exec_stores 15836093 # Number of stores executed -system.cpu.iew.exec_rate 2.088349 # Inst execution rate -system.cpu.iew.wb_sent 87691296 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87276948 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33460873 # num instructions producing a value -system.cpu.iew.wb_consumers 43882648 # num instructions consuming a value +system.cpu.iew.exec_nop 9542553 # number of nop insts executed +system.cpu.iew.exec_refs 38558406 # number of memory reference insts executed +system.cpu.iew.exec_branches 15140678 # Number of branches executed +system.cpu.iew.exec_stores 15837541 # Number of stores executed +system.cpu.iew.exec_rate 2.018640 # Inst execution rate +system.cpu.iew.wb_sent 87722588 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87306055 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33473930 # num instructions producing a value +system.cpu.iew.wb_consumers 43902488 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.069834 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762508 # average fanout of values written-back +system.cpu.iew.wb_rate 2.000595 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762461 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9477917 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9547814 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 366510 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 40393190 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.187019 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.818394 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 369802 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39796250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.219824 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.827061 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 17375613 43.02% 43.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7063647 17.49% 60.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3493568 8.65% 69.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2102678 5.21% 74.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2090838 5.18% 79.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1172557 2.90% 82.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1137405 2.82% 85.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 723784 1.79% 87.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5233100 12.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16770955 42.14% 42.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7067067 17.76% 59.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3514313 8.83% 68.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2098075 5.27% 74.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2085843 5.24% 79.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1169184 2.94% 82.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1108409 2.79% 84.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 748224 1.88% 86.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5234180 13.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 40393190 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39796250 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -316,70 +474,70 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5233100 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5234180 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 131661337 # The number of ROB reads -system.cpu.rob.rob_writes 197076783 # The number of ROB writes -system.cpu.timesIdled 11011 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 336765 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 131133214 # The number of ROB reads +system.cpu.rob.rob_writes 197227324 # The number of ROB writes +system.cpu.timesIdled 14215 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2397008 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.529781 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.529781 # CPI: Total CPI of All Threads -system.cpu.ipc 1.887574 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.887574 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116593496 # number of integer regfile reads -system.cpu.int_regfile_writes 57858579 # number of integer regfile writes -system.cpu.fp_regfile_reads 252858 # number of floating regfile reads -system.cpu.fp_regfile_writes 241901 # number of floating regfile writes -system.cpu.misc_regfile_reads 38310 # number of misc regfile reads +system.cpu.cpi 0.548299 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.548299 # CPI: Total CPI of All Threads +system.cpu.ipc 1.823824 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.823824 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116640350 # number of integer regfile reads +system.cpu.int_regfile_writes 57883705 # number of integer regfile writes +system.cpu.fp_regfile_reads 253852 # number of floating regfile reads +system.cpu.fp_regfile_writes 241497 # number of floating regfile writes +system.cpu.misc_regfile_reads 38324 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 94995 # number of replacements -system.cpu.icache.tagsinuse 1931.010955 # Cycle average of tags in use -system.cpu.icache.total_refs 14025954 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 97043 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 144.533392 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 17649756000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1931.010955 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.942876 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.942876 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14025954 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14025954 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14025954 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14025954 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14025954 # number of overall hits -system.cpu.icache.overall_hits::total 14025954 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 100744 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 100744 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 100744 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 100744 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 100744 # number of overall misses -system.cpu.icache.overall_misses::total 100744 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 779635000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 779635000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 779635000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 779635000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 779635000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 779635000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14126698 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14126698 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14126698 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14126698 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14126698 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14126698 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007131 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007131 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007131 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007131 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007131 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007131 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7738.773525 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 7738.773525 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 7738.773525 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 7738.773525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 7738.773525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 7738.773525 # average overall miss latency +system.cpu.icache.replacements 93950 # number of replacements +system.cpu.icache.tagsinuse 1932.033344 # Cycle average of tags in use +system.cpu.icache.total_refs 14048966 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 95998 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 146.346445 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18344988000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 1932.033344 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.943376 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.943376 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14048966 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14048966 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14048966 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14048966 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14048966 # number of overall hits +system.cpu.icache.overall_hits::total 14048966 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 99528 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 99528 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 99528 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 99528 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 99528 # number of overall misses +system.cpu.icache.overall_misses::total 99528 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 808544500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 808544500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 808544500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 808544500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 808544500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 808544500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14148494 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14148494 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14148494 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14148494 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14148494 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14148494 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007035 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007035 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007035 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007035 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007035 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007035 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8123.789285 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8123.789285 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8123.789285 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8123.789285 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8123.789285 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8123.789285 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,286 +546,286 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3700 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3700 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3700 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3700 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3700 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3700 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 97044 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 97044 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 97044 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 97044 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 97044 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 97044 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 497811000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 497811000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 497811000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 497811000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 497811000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 497811000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006870 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006870 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006870 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006870 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5129.745270 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5129.745270 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5129.745270 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 5129.745270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5129.745270 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 5129.745270 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3529 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3529 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3529 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3529 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3529 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3529 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95999 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 95999 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 95999 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 95999 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 95999 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 95999 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 523730500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 523730500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 523730500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 523730500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 523730500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 523730500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006785 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006785 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006785 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006785 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5455.582871 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5455.582871 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5455.582871 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 5455.582871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5455.582871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 5455.582871 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 201505 # number of replacements -system.cpu.dcache.tagsinuse 4076.313431 # Cycle average of tags in use -system.cpu.dcache.total_refs 34371357 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205601 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 167.175048 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 155296000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.313431 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995194 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995194 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20790228 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20790228 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13581056 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13581056 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 73 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 73 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34371284 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34371284 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34371284 # number of overall hits -system.cpu.dcache.overall_hits::total 34371284 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 252353 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 252353 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1032321 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1032321 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1284674 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1284674 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1284674 # number of overall misses -system.cpu.dcache.overall_misses::total 1284674 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7773688500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7773688500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39504948500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39504948500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 47278637000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 47278637000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 47278637000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 47278637000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21042581 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21042581 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 201587 # number of replacements +system.cpu.dcache.tagsinuse 4077.730467 # Cycle average of tags in use +system.cpu.dcache.total_refs 34377845 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205683 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 167.139944 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 145380000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4077.730467 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.995540 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.995540 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20796650 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20796650 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13581134 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13581134 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34377784 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34377784 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34377784 # number of overall hits +system.cpu.dcache.overall_hits::total 34377784 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 252404 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 252404 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1032243 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1032243 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1284647 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1284647 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1284647 # number of overall misses +system.cpu.dcache.overall_misses::total 1284647 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7081461500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7081461500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 60841906500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 60841906500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 67923368000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 67923368000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 67923368000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 67923368000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21049054 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21049054 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 73 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 73 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35655958 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35655958 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35655958 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35655958 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011992 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011992 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070642 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.070642 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036030 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036030 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036030 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036030 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30804.819043 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30804.819043 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38268.085702 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38268.085702 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36802.050170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36802.050170 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 181 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 51 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35662431 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35662431 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35662431 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35662431 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011991 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011991 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070637 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.070637 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036022 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036022 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036022 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036022 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28056.058937 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28056.058937 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58941.457099 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 58941.457099 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52873.176834 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52873.176834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52873.176834 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52873.176834 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1971 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 36 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.066667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 51 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.750000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 40 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 166256 # number of writebacks -system.cpu.dcache.writebacks::total 166256 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 190181 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 190181 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 888892 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 888892 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1079073 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1079073 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1079073 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1079073 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62172 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62172 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143429 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143429 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205601 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205601 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205601 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205601 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1152797500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1152797500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5564302000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5564302000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6717099500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6717099500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6717099500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6717099500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002955 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002955 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005766 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005766 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005766 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005766 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18542.068777 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18542.068777 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38794.818342 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38794.818342 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32670.558509 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32670.558509 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32670.558509 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32670.558509 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 166289 # number of writebacks +system.cpu.dcache.writebacks::total 166289 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 190140 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 190140 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 888824 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 888824 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1078964 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1078964 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1078964 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1078964 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62264 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62264 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143419 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143419 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205683 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205683 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205683 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205683 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1130234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1130234500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8280369500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8280369500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9410604000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9410604000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9410604000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9410604000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005767 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005767 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005767 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005767 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18152.295066 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18152.295066 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57735.512728 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57735.512728 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45752.949928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45752.949928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45752.949928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45752.949928 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 137202 # number of replacements -system.cpu.l2cache.tagsinuse 29157.346540 # Cycle average of tags in use -system.cpu.l2cache.total_refs 157131 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 168078 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.934870 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 137215 # number of replacements +system.cpu.l2cache.tagsinuse 29193.790344 # Cycle average of tags in use +system.cpu.l2cache.total_refs 156193 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 168097 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.929184 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25380.921968 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1917.691461 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1858.733111 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.774564 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.058523 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.056724 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.889812 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 88301 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32273 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 120574 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 166256 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 166256 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12465 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12465 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 88301 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 44738 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 133039 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 88301 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 44738 # number of overall hits -system.cpu.l2cache.overall_hits::total 133039 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8743 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 29897 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 38640 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130966 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130966 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143431 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 97044 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205601 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 302645 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 97044 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205601 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 302645 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.090093 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.480891 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.242692 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913094 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.913094 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.090093 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.782404 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.560412 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.090093 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.782404 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.560412 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35626.787144 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35332.123624 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35398.796584 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41225.604355 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41225.604355 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35626.787144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40130.278560 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 39898.128604 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.787144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40130.278560 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 39898.128604 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 75 # number of cycles access was blocked +system.cpu.l2cache.occ_blocks::writebacks 25457.491350 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1903.606524 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1832.692470 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.562251 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.091105 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.782150 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.562251 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38800.022868 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34552.014040 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 35513.010527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 62001.592089 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 62001.592089 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38800.022868 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56897.292929 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 55964.161277 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38800.022868 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56897.292929 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 55964.161277 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 1668 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6.818182 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 49.058824 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8743 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 160863 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 169606 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 283805000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 965325500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1249130500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4998997500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4998997500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283805000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5964323000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6248128000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283805000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5964323000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6248128000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.090093 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480891 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.242692 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913094 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913094 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.090093 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782404 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.560412 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.090093 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782404 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.560412 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32460.825803 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32288.373415 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32327.393892 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38170.193027 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38170.193027 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32460.825803 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37077.034495 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36839.074089 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32460.825803 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37077.034495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36839.074089 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 116046 # number of writebacks +system.cpu.l2cache.writebacks::total 116046 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8746 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29915 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 38661 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130960 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130960 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8746 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 160875 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 169621 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8746 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 160875 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 169621 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 306935647 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 916786687 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1223722334 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7694631450 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7694631450 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 306935647 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8611418137 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8918353784 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 306935647 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8611418137 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8918353784 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480462 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.244285 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913122 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.562251 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091105 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782150 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.562251 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35094.402813 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30646.387665 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31652.630144 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58755.585293 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58755.585293 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35094.402813 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53528.628668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52578.122898 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35094.402813 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53528.628668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52578.122898 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index fe9fd6111..c4dd2ec41 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,197 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023747 # Number of seconds simulated -sim_ticks 23747395500 # Number of ticks simulated -final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024118 # Number of seconds simulated +sim_ticks 24118236000 # Number of ticks simulated +final_tick 24118236000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142184 # Simulator instruction rate (inst/s) -host_op_rate 201762 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47606944 # Simulator tick rate (ticks/s) -host_mem_usage 237384 # Number of bytes of host memory used -host_seconds 498.82 # Real time elapsed on the host -sim_insts 70924309 # Number of instructions simulated -sim_ops 100643556 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8028992 # Number of bytes read from this memory -system.physmem.bytes_read::total 8354880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 325888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 325888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417728 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417728 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5092 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125453 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130545 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84652 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84652 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13723105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 338099898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 351823003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13723105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13723105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 228139882 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 228139882 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 228139882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13723105 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 338099898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 579962885 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 96109 # Simulator instruction rate (inst/s) +host_op_rate 136382 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32682486 # Simulator tick rate (ticks/s) +host_mem_usage 260548 # Number of bytes of host memory used +host_seconds 737.96 # Real time elapsed on the host +sim_insts 70924474 # Number of instructions simulated +sim_ops 100643721 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 326720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory +system.physmem.bytes_read::total 8354752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 326720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 326720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417408 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417408 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5105 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130543 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84647 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84647 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13546596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 332861491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 346408087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13546596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13546596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 224618749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 224618749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 224618749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13546596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 332861491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 571026836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 130544 # Total number of read requests seen +system.physmem.writeReqs 84647 # Total number of write requests seen +system.physmem.cpureqs 215212 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8354752 # Total number of bytes read from memory +system.physmem.bytesWritten 5417408 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8354752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5417408 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 6 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 21 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8259 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8120 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8253 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 7969 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8186 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8129 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8104 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8256 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 8061 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 8114 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8038 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5079 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5269 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5220 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5401 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5326 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5458 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5400 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5357 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5255 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 24118216500 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 0 # Categorize read packet sizes +system.physmem.readPktSize::3 0 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 130544 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 0 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 84647 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 21 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 69205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 57726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 3556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 2308860118 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4224446118 # Sum of mem lat for all requests +system.physmem.totBusLat 522152000 # Total cycles spent in databus access +system.physmem.totBankLat 1393434000 # Total cycles spent in bank access +system.physmem.avgQLat 17687.26 # Average queueing delay per request +system.physmem.avgBankLat 10674.55 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 32361.81 # Average memory access latency +system.physmem.avgRdBW 346.41 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 224.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 346.41 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 224.62 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 3.57 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.18 # Average read queue length over time +system.physmem.avgWrQLen 10.22 # Average write queue length over time +system.physmem.readRowHits 119025 # Number of row buffer hits during reads +system.physmem.writeRowHits 63519 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes +system.physmem.avgGap 112078.18 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +235,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 47494792 # number of cpu cycles simulated +system.cpu.numCycles 48236473 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16945853 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12976600 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 671047 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11791616 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7980415 # Number of BTB hits +system.cpu.BPredUnit.lookups 16941730 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12971297 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 673506 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11955063 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7993850 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1850372 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114214 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12555295 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 86800259 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16945853 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9830787 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21603869 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2612787 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10088905 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 370 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 11920379 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 192164 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46165707 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.632126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.343505 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1846956 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114386 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12578866 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 86846522 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16941730 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9840806 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21621241 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2621679 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 9822158 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 11935876 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 192083 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 45946369 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.646136 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.346825 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24583523 53.25% 53.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2172032 4.70% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2013449 4.36% 62.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2091121 4.53% 66.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1494392 3.24% 70.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1411801 3.06% 73.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 982905 2.13% 75.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1224192 2.65% 77.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10192292 22.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24346810 52.99% 52.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2176798 4.74% 57.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2018114 4.39% 62.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2096656 4.56% 66.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1493050 3.25% 69.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1410144 3.07% 73.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 982338 2.14% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1219252 2.65% 77.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10203207 22.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46165707 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.356794 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.827574 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14647959 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8470510 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19858799 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1377235 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1811204 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3409264 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 108749 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118806925 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 370081 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1811204 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16375618 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2381141 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 742521 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19461585 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5393638 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 116666793 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 9401 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4563999 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 255 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117035573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 537232740 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537225721 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7019 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99159360 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17876213 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25291 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25289 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12820996 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29922759 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22636012 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3511140 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4209388 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112770529 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 41465 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108119060 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 319934 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12017924 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 28288746 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4343 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46165707 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.341978 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.993843 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 45946369 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.351222 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.800433 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14667970 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8208523 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19889635 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1362773 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1817468 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3410064 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108805 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118869438 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 371525 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1817468 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16391147 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2180805 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 744758 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19482609 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5329582 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116713190 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 108 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 9859 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4505903 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 207 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117071318 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 537479367 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537472531 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6836 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159624 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17911694 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25668 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25645 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12679365 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29945230 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22644975 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3554453 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4308488 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112817859 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41708 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108131794 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 320520 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12061302 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28451439 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4553 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 45946369 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.353435 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.992555 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10763393 23.31% 23.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8065577 17.47% 40.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7395154 16.02% 56.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7189034 15.57% 72.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5495666 11.90% 84.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3896907 8.44% 92.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1882413 4.08% 96.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 886108 1.92% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 591455 1.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10567306 23.00% 23.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8020118 17.46% 40.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7429171 16.17% 56.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7172224 15.61% 72.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5474021 11.91% 84.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3920572 8.53% 92.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1887629 4.11% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 890680 1.94% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 584648 1.27% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46165707 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 45946369 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 111137 4.37% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1401194 55.04% 59.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1033519 40.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112571 4.42% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1415190 55.57% 59.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1018757 40.01% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57171551 52.88% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91476 0.08% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57176824 52.88% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91588 0.08% 52.96% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 254 0.00% 52.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 236 0.00% 52.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.96% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.96% # Type of FU issued @@ -239,158 +397,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.96% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.96% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29115621 26.93% 79.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21740151 20.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29115499 26.93% 79.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21747640 20.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108119060 # Type of FU issued -system.cpu.iq.rate 2.276440 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2545850 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023547 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 265268953 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124855497 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106214423 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 658 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1042 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 198 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110664579 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 331 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2183386 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108131794 # Type of FU issued +system.cpu.iq.rate 2.241702 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2546520 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023550 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 265076321 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124946354 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106228285 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 676 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1064 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 184 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110677977 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 337 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2176777 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2612315 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8134 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27815 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2076938 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2634753 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7333 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 27466 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2085868 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1811204 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 969930 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37593 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 112821828 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 344750 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29922759 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22636012 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24938 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1077 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4742 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27815 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 448633 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 200270 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 648903 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106941825 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28766464 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1177235 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1817468 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 825568 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 31883 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112869381 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 345659 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29945230 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22644975 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 25238 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1097 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3023 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 27466 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 452017 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 199338 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 651355 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106955311 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28765738 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1176483 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9834 # number of nop insts executed -system.cpu.iew.exec_refs 50197967 # number of memory reference insts executed -system.cpu.iew.exec_branches 14707935 # Number of branches executed -system.cpu.iew.exec_stores 21431503 # Number of stores executed -system.cpu.iew.exec_rate 2.251654 # Inst execution rate -system.cpu.iew.wb_sent 106459563 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106214621 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53551409 # num instructions producing a value -system.cpu.iew.wb_consumers 103987749 # num instructions consuming a value +system.cpu.iew.exec_nop 9814 # number of nop insts executed +system.cpu.iew.exec_refs 50205955 # number of memory reference insts executed +system.cpu.iew.exec_branches 14704580 # Number of branches executed +system.cpu.iew.exec_stores 21440217 # Number of stores executed +system.cpu.iew.exec_rate 2.217312 # Inst execution rate +system.cpu.iew.wb_sent 106472209 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106228469 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53599142 # num instructions producing a value +system.cpu.iew.wb_consumers 104275439 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.236342 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514978 # average fanout of values written-back +system.cpu.iew.wb_rate 2.202244 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12173182 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37122 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 565028 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44354504 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.269197 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.754788 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12220612 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37155 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 567157 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44128902 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.280802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.756042 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15099779 34.04% 34.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11755524 26.50% 60.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3528202 7.95% 68.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2907503 6.56% 75.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1884478 4.25% 79.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1967896 4.44% 83.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685684 1.55% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 580329 1.31% 86.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5945109 13.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14889585 33.74% 33.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11723135 26.57% 60.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3525477 7.99% 68.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2911105 6.60% 74.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1898953 4.30% 79.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1983472 4.49% 83.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685141 1.55% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 578421 1.31% 86.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5933613 13.45% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44354504 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929861 # Number of instructions committed -system.cpu.commit.committedOps 100649108 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 44128902 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70930026 # Number of instructions committed +system.cpu.commit.committedOps 100649273 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869518 # Number of memory references committed -system.cpu.commit.loads 27310444 # Number of loads committed +system.cpu.commit.refs 47869584 # Number of memory references committed +system.cpu.commit.loads 27310477 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13744841 # Number of branches committed +system.cpu.commit.branches 13744874 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91486123 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486255 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5945109 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5933613 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 151206386 # The number of ROB reads -system.cpu.rob.rob_writes 227466743 # The number of ROB writes -system.cpu.timesIdled 61795 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1329085 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924309 # Number of Instructions Simulated -system.cpu.committedOps 100643556 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924309 # Number of Instructions Simulated -system.cpu.cpi 0.669655 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.669655 # CPI: Total CPI of All Threads -system.cpu.ipc 1.493307 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.493307 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 514746035 # number of integer regfile reads -system.cpu.int_regfile_writes 104090442 # number of integer regfile writes -system.cpu.fp_regfile_reads 1004 # number of floating regfile reads -system.cpu.fp_regfile_writes 868 # number of floating regfile writes -system.cpu.misc_regfile_reads 145207051 # number of misc regfile reads -system.cpu.misc_regfile_writes 38512 # number of misc regfile writes -system.cpu.icache.replacements 28686 # number of replacements -system.cpu.icache.tagsinuse 1815.800680 # Cycle average of tags in use -system.cpu.icache.total_refs 11888473 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30726 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 386.918994 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 151039875 # The number of ROB reads +system.cpu.rob.rob_writes 227567987 # The number of ROB writes +system.cpu.timesIdled 41986 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2290104 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924474 # Number of Instructions Simulated +system.cpu.committedOps 100643721 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924474 # Number of Instructions Simulated +system.cpu.cpi 0.680110 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.680110 # CPI: Total CPI of All Threads +system.cpu.ipc 1.470350 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.470350 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 514798749 # number of integer regfile reads +system.cpu.int_regfile_writes 104102920 # number of integer regfile writes +system.cpu.fp_regfile_reads 856 # number of floating regfile reads +system.cpu.fp_regfile_writes 720 # number of floating regfile writes +system.cpu.misc_regfile_reads 145263086 # number of misc regfile reads +system.cpu.misc_regfile_writes 38578 # number of misc regfile writes +system.cpu.icache.replacements 29552 # number of replacements +system.cpu.icache.tagsinuse 1826.273597 # Cycle average of tags in use +system.cpu.icache.total_refs 11903209 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 31595 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 376.743440 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1815.800680 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886621 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886621 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11888474 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11888474 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11888474 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11888474 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11888474 # number of overall hits -system.cpu.icache.overall_hits::total 11888474 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 31905 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 31905 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 31905 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 31905 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 31905 # number of overall misses -system.cpu.icache.overall_misses::total 31905 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328897000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328897000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328897000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328897000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328897000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328897000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11920379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11920379 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11920379 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11920379 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11920379 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11920379 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002677 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002677 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002677 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002677 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002677 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002677 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10308.635010 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10308.635010 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10308.635010 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10308.635010 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10308.635010 # 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number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11935876 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11935876 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11935876 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002737 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002737 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002737 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002737 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002737 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002737 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11071.419825 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11071.419825 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11071.419825 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11071.419825 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11071.419825 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +557,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1159 # 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number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62795873000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62795873000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62795873000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26351541 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26351541 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20497 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20497 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19255 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19255 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46196088 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46196088 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46196088 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46196088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078836 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078836 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002049 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002049 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036154 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036154 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036154 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036154 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20342.991178 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20342.991178 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34612.904607 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34612.904607 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8535.714286 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8535.714286 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33713.205595 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20624 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20624 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19288 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19288 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46201442 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46201442 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46201442 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46201442 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003986 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003986 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078833 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078833 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001794 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001794 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036144 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036144 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036144 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036144 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24747.305993 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24747.305993 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38468.092802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38468.092802 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12121.621622 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12121.621622 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37604.953760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37604.953760 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37604.953760 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 394 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 149 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 39.400000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 16.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128103 # number of writebacks -system.cpu.dcache.writebacks::total 128103 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49707 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49707 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457877 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1457877 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1507584 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1507584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1507584 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1507584 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55596 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55596 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107006 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107006 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162602 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162602 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162602 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162602 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 945497500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 945497500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3824998000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3824998000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4770495500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4770495500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4770495500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4770495500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002110 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002110 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 128088 # number of writebacks +system.cpu.dcache.writebacks::total 128088 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49495 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49495 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457827 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1457827 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1507322 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1507322 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1507322 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1507322 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55553 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55553 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107008 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107008 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162561 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162561 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162561 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162561 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1141045500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1141045500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4220015000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4220015000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5361060500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5361060500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5361060500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5361060500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002108 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002108 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005391 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003520 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003520 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003520 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.574214 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.574214 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35745.640431 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35745.640431 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29338.479846 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29338.479846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29338.479846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29338.479846 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003519 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003519 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003519 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003519 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20539.763829 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20539.763829 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39436.444004 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39436.444004 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32978.761819 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32978.761819 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32978.761819 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32978.761819 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 97972 # number of replacements -system.cpu.l2cache.tagsinuse 28672.320506 # Cycle average of tags in use -system.cpu.l2cache.total_refs 85492 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128764 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.663943 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 97971 # number of replacements +system.cpu.l2cache.tagsinuse 28800.701977 # Cycle average of tags in use +system.cpu.l2cache.total_refs 86327 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 128762 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.670438 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25877.470214 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1151.216152 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1643.634140 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.789718 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035132 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.050160 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.875010 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 25596 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32355 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 57951 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128103 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128103 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 25974.611226 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1154.606563 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 1671.484188 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.792682 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.035236 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.051010 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.878928 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 26463 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 32338 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 58801 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128088 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128088 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4711 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4711 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 25596 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 37066 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 62662 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 25596 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 37066 # number of overall hits -system.cpu.l2cache.overall_hits::total 62662 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5128 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 23202 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 28330 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 18 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102315 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102315 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5128 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 125517 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130645 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5128 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40826.285922 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 1001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 1001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36679.130781 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36679.130781 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.022718 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37609.705655 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37575.885096 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.022718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37609.705655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37575.885096 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |