diff options
Diffstat (limited to 'tests/long/se/50.vortex')
10 files changed, 0 insertions, 4086 deletions
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini deleted file mode 100644 index 46094eb94..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ /dev/null @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout deleted file mode 100755 index a86af0918..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28063 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 61709224000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt deleted file mode 100644 index 0d9a67eb8..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ /dev/null @@ -1,829 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.061709 # Number of seconds simulated -sim_ticks 61709224000 # Number of ticks simulated -final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 484192 # Simulator instruction rate (inst/s) -host_op_rate 484192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337853764 # Simulator tick rate (ticks/s) -host_mem_usage 263376 # Number of bytes of host memory used -host_seconds 182.65 # Real time elapsed on the host -sim_insts 88438073 # Number of instructions simulated -sim_ops 88438073 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory -system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory -system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165740 # Number of read requests accepted -system.physmem.writeReqs 115251 # Number of write requests accepted -system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue -system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10345 # Per bank write bursts -system.physmem.perBankRdBursts::1 10387 # Per bank write bursts -system.physmem.perBankRdBursts::2 10224 # Per bank write bursts -system.physmem.perBankRdBursts::3 10068 # Per bank write bursts -system.physmem.perBankRdBursts::4 10353 # Per bank write bursts -system.physmem.perBankRdBursts::5 10360 # Per bank write bursts -system.physmem.perBankRdBursts::6 9794 # Per bank write bursts -system.physmem.perBankRdBursts::7 10230 # Per bank write bursts -system.physmem.perBankRdBursts::8 10568 # Per bank write bursts -system.physmem.perBankRdBursts::9 10626 # Per bank write bursts -system.physmem.perBankRdBursts::10 10568 # Per bank write bursts -system.physmem.perBankRdBursts::11 10241 # Per bank write bursts -system.physmem.perBankRdBursts::12 10306 # Per bank write bursts -system.physmem.perBankRdBursts::13 10592 # Per bank write bursts -system.physmem.perBankRdBursts::14 10494 # Per bank write bursts -system.physmem.perBankRdBursts::15 10573 # Per bank write bursts -system.physmem.perBankWrBursts::0 7166 # Per bank write bursts -system.physmem.perBankWrBursts::1 7281 # Per bank write bursts -system.physmem.perBankWrBursts::2 7303 # Per bank write bursts -system.physmem.perBankWrBursts::3 7012 # Per bank write bursts -system.physmem.perBankWrBursts::4 7145 # Per bank write bursts -system.physmem.perBankWrBursts::5 7305 # Per bank write bursts -system.physmem.perBankWrBursts::6 6890 # Per bank write bursts -system.physmem.perBankWrBursts::7 7164 # Per bank write bursts -system.physmem.perBankWrBursts::8 7246 # Per bank write bursts -system.physmem.perBankWrBursts::9 7071 # Per bank write bursts -system.physmem.perBankWrBursts::10 7213 # Per bank write bursts -system.physmem.perBankWrBursts::11 7126 # Per bank write bursts -system.physmem.perBankWrBursts::12 7072 # Per bank write bursts -system.physmem.perBankWrBursts::13 7397 # Per bank write bursts -system.physmem.perBankWrBursts::14 7351 # Per bank write bursts -system.physmem.perBankWrBursts::15 7483 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61709200500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165740 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115251 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 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-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads -system.physmem.totQLat 3617300750 # Total ticks spent queuing -system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.28 # Data bus utilization in percentage -system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing -system.physmem.readRowHits 144262 # Number of row buffer hits during reads -system.physmem.writeRowHits 89468 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes -system.physmem.avgGap 219612.73 # Average gap between requests -system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ) -system.physmem_0.averagePower 393.299410 # Core power per rank (mW) -system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states -system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ) -system.physmem_1.averagePower 400.858918 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14696527 # Number of BP lookups -system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20579387 # DTB read hits -system.cpu.dtb.read_misses 95377 # DTB read misses -system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674764 # DTB read accesses -system.cpu.dtb.write_hits 14666029 # DTB write hits -system.cpu.dtb.write_misses 8840 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674869 # DTB write accesses -system.cpu.dtb.data_hits 35245416 # DTB hits -system.cpu.dtb.data_misses 104217 # DTB misses -system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35349633 # DTB accesses -system.cpu.itb.fetch_hits 25650137 # ITB hits -system.cpu.itb.fetch_misses 5179 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25655316 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 123418448 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88438073 # Number of instructions committed -system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.395535 # CPI: cycles per instruction -system.cpu.ipc 0.716571 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction -system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction -system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::MemRead 20366476 23.03% 83.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 14619024 16.53% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 310 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked -system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200809 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits -system.cpu.dcache.overall_hits::total 34647996 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses -system.cpu.dcache.overall_misses::total 341611 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168117 # number of writebacks -system.cpu.dcache.writebacks::total 168117 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136509 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136706 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136706 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136706 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136706 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61338 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61338 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3088657500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50354.714859 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50354.714859 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84853.890518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84853.890518 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 153962 # number of replacements -system.cpu.icache.tags.tagsinuse 1929.475732 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25494126 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 156010 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.413409 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 43906590500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1929.475732 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.942127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.942127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51456284 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51456284 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25494126 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25494126 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25494126 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25494126 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25494126 # number of overall hits -system.cpu.icache.overall_hits::total 25494126 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 156011 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 156011 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 156011 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 156011 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 156011 # number of overall misses -system.cpu.icache.overall_misses::total 156011 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2690499000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2690499000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2690499000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2690499000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2690499000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2690499000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25650137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25650137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25650137 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25650137 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25650137 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25650137 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17245.572428 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17245.572428 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17245.572428 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17245.572428 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153962 # number of writebacks -system.cpu.icache.writebacks::total 153962 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 156011 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 156011 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 156011 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 156011 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 156011 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 156011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2534489000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2534489000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2534489000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2534489000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2534489000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2534489000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16245.578837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16245.578837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 135280 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31691.220276 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 547521 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168048 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.258123 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 14447297000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 710.430921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1986.776331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28994.013023 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021681 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060632 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.884827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.967139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 8856 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22759 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5893544 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5893544 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168117 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168117 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153962 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153962 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 149161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33355 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33355 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 149161 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46014 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 195175 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 149161 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46014 # number of overall hits -system.cpu.l2cache.overall_hits::total 195175 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6850 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6850 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27983 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27983 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6850 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158891 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165741 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6850 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158891 # number of overall misses -system.cpu.l2cache.overall_misses::total 165741 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11833894500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11833894500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 734127500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 734127500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2646160500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2646160500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 734127500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14480055000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15214182500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 734127500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14480055000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15214182500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168117 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168117 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 153962 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 153962 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 156011 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 156011 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61338 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61338 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 156011 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360916 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 156011 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360916 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043907 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043907 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456210 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456210 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043907 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775437 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.459223 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043907 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775437 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.459223 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90398.558530 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90398.558530 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107171.897810 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107171.897810 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94563.145481 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94563.145481 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 91794.924008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 91794.924008 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115252 # number of writebacks -system.cpu.l2cache.writebacks::total 115252 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6850 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6850 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27983 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27983 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6850 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158891 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165741 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6850 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158891 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165741 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10524814500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10524814500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 665637500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 665637500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2366330500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2366330500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 665637500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12891145000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13556782500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 665637500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12891145000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13556782500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135280 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34832 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution -system.membus.trans_dist::CleanEvict 15886 # Transaction distribution -system.membus.trans_dist::ReadExReq 130908 # Transaction distribution -system.membus.trans_dist::ReadExResp 130908 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165740 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165740 # Request fanout histogram -system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini deleted file mode 100644 index 42d282c4a..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ /dev/null @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr deleted file mode 100755 index e0bca4e4e..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr +++ /dev/null @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout deleted file mode 100755 index 03964c60a..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ /dev/null @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28054 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 22819771500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg deleted file mode 100644 index 472b08431..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg +++ /dev/null @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out deleted file mode 100644 index 726b45c60..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out +++ /dev/null @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every <mod 0>Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD <Query0> for <Part2> class:: - - if (link[1].length >= 5) :: - - Build Query2 for <Address> class:: - - if (State == CA || State == T*) - - Build Query1 for <Person> class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD <Query3> for <DrawObj> class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD <Query4> for <NamedDrawObj> class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET <DrawObjs> entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET <NamedDrawObjs> entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET <LibRectangles> entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST <DbRectangles> entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET <PersonNames > entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=<True>; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - <Part2 > Asserts = 2; NULL Asserts = 3. - <DrawObj > Asserts = 0; NULL Asserts = 5. - <NamedObj > Asserts = 0; NULL Asserts = 0. - <Person > Asserts = 0; NULL Asserts = 5. - <TestObj > Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=<True>; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in <Primal> DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in <Primal> DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt deleted file mode 100644 index 53a1c5599..000000000 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ /dev/null @@ -1,1097 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.022820 # Number of seconds simulated -sim_ticks 22819771500 # Number of ticks simulated -final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 390933 # Simulator instruction rate (inst/s) -host_op_rate 390933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112084385 # Simulator tick rate (ticks/s) -host_mem_usage 265424 # Number of bytes of host memory used -host_seconds 203.59 # Real time elapsed on the host -sim_insts 79591756 # Number of instructions simulated -sim_ops 79591756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 414016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10170944 # Number of bytes read from this memory -system.physmem.bytes_read::total 10584960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 414016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 414016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 7372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158921 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165390 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18142864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 445707530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 463850394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18142864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18142864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 323079835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 323079835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 323079835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18142864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 445707530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 786930228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165390 # Number of read requests accepted -system.physmem.writeReqs 115197 # Number of write requests accepted -system.physmem.readBursts 165390 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115197 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10584512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7370752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10584960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7372608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10310 # Per bank write bursts -system.physmem.perBankRdBursts::1 10353 # Per bank write bursts -system.physmem.perBankRdBursts::2 10221 # Per bank write bursts -system.physmem.perBankRdBursts::3 10036 # Per bank write bursts -system.physmem.perBankRdBursts::4 10349 # Per bank write bursts -system.physmem.perBankRdBursts::5 10326 # Per bank write bursts -system.physmem.perBankRdBursts::6 9802 # Per bank write bursts -system.physmem.perBankRdBursts::7 10209 # Per bank write bursts -system.physmem.perBankRdBursts::8 10557 # Per bank write bursts -system.physmem.perBankRdBursts::9 10617 # Per bank write bursts -system.physmem.perBankRdBursts::10 10516 # Per bank write bursts -system.physmem.perBankRdBursts::11 10223 # Per bank write bursts -system.physmem.perBankRdBursts::12 10279 # Per bank write bursts -system.physmem.perBankRdBursts::13 10557 # Per bank write bursts -system.physmem.perBankRdBursts::14 10475 # Per bank write bursts -system.physmem.perBankRdBursts::15 10553 # Per bank write bursts -system.physmem.perBankWrBursts::0 7167 # Per bank write bursts -system.physmem.perBankWrBursts::1 7277 # Per bank write bursts -system.physmem.perBankWrBursts::2 7300 # Per bank write bursts -system.physmem.perBankWrBursts::3 7008 # Per bank write bursts -system.physmem.perBankWrBursts::4 7142 # Per bank write bursts -system.physmem.perBankWrBursts::5 7300 # Per bank write bursts -system.physmem.perBankWrBursts::6 6892 # Per bank write bursts -system.physmem.perBankWrBursts::7 7158 # Per bank write bursts -system.physmem.perBankWrBursts::8 7240 # Per bank write bursts -system.physmem.perBankWrBursts::9 7069 # Per bank write bursts -system.physmem.perBankWrBursts::10 7202 # Per bank write bursts -system.physmem.perBankWrBursts::11 7121 # Per bank write bursts -system.physmem.perBankWrBursts::12 7069 # Per bank write bursts -system.physmem.perBankWrBursts::13 7390 # Per bank write bursts -system.physmem.perBankWrBursts::14 7350 # Per bank write bursts -system.physmem.perBankWrBursts::15 7483 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22819740500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165390 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115197 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 42313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 44648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 402.130084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 240.586732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.720381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13091 29.32% 29.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8315 18.62% 47.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5360 12.01% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2692 6.03% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2549 5.71% 71.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1575 3.53% 75.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1705 3.82% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1125 2.52% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8236 18.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 44648 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.304961 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.955367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 317.126574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7095 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7096 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.229989 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.211978 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.816035 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6480 91.32% 91.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 18 0.25% 91.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 334 4.71% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 161 2.27% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 74 1.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 24 0.34% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7096 # Writes before turning the bus around for reads -system.physmem.totQLat 7131716500 # Total ticks spent queuing -system.physmem.totMemAccLat 10232647750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43122.43 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 61872.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 463.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 323.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 463.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 323.08 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.15 # Data bus utilization in percentage -system.physmem.busUtilRead 3.62 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 145971 # Number of row buffer hits during reads -system.physmem.writeRowHits 89923 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes -system.physmem.avgGap 81328.57 # Average gap between requests -system.physmem.pageHitRate 84.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153103020 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 81361005 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 582666840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 298813680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1398920640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1820142240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 87895200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 2523555300 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1884269760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 2191410645 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11023267740 # Total energy per rank (pJ) -system.physmem_0.averagePower 483.057740 # Core power per rank (mW) -system.physmem_0.totalIdleTime 18596850000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 135529000 # Time in different power states -system.physmem_0.memoryStateTime::REF 594334000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 8155766000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 4906976500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3493009750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 5534156250 # Time in different power states -system.physmem_1.actEnergy 165747960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 88078155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 598167780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 302363280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1429652640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1911531480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 82258560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 2724848520 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1880202720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 2026371015 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11210189940 # Total energy per rank (pJ) -system.physmem_1.averagePower 491.248979 # Core power per rank (mW) -system.physmem_1.totalIdleTime 18411251500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 119903000 # Time in different power states -system.physmem_1.memoryStateTime::REF 607208000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 7539541250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 4896374750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3681289750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 5975454750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16458678 # Number of BP lookups -system.cpu.branchPred.condPredicted 10655092 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 320474 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8794743 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7227596 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.180866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1974394 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3324 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39317 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31522 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7795 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2656 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22495361 # DTB read hits -system.cpu.dtb.read_misses 227004 # DTB read misses -system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22722365 # DTB read accesses -system.cpu.dtb.write_hits 15803250 # DTB write hits -system.cpu.dtb.write_misses 44602 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15847852 # DTB write accesses -system.cpu.dtb.data_hits 38298611 # DTB hits -system.cpu.dtb.data_misses 271606 # DTB misses -system.cpu.dtb.data_acv 22 # DTB access violations -system.cpu.dtb.data_accesses 38570217 # DTB accesses -system.cpu.itb.fetch_hits 13713928 # ITB hits -system.cpu.itb.fetch_misses 29641 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13743569 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45639548 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15527632 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104958165 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16458678 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9233512 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 28526394 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 879432 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1335 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 342280 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 91 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13713928 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 186437 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 44842161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.340613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.113400 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25352844 56.54% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1513864 3.38% 59.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1375551 3.07% 62.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1499198 3.34% 66.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4186922 9.34% 75.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1824752 4.07% 79.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669001 1.49% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050081 2.34% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7369948 16.44% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44842161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.360623 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.299720 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14899514 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10738608 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18272960 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 588305 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 342774 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3699945 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98528 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 102994976 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312859 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 342774 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15240271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5029380 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97820 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18506228 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5625688 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102003977 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6871 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 88609 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 422499 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5043111 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61324692 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123005722 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122686459 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319262 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8777811 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5683 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5735 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2339310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23131891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16353716 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1249387 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502474 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90699211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5558 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88573949 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67838 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11113012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4439512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 975 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44842161 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.975238 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.240795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18402096 41.04% 41.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5711089 12.74% 53.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5105714 11.39% 65.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4382501 9.77% 74.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4313150 9.62% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2637224 5.88% 90.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1940283 4.33% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1377321 3.07% 97.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 972783 2.17% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44842161 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 241463 9.57% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168317 46.29% 55.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1113838 44.13% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 25 0.00% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 417 0.02% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49366935 55.74% 55.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43991 0.05% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22887385 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15970151 18.03% 99.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 459 0.00% 99.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 23933 0.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued -system.cpu.iq.rate 1.940728 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2524060 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028497 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223970516 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611441 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90792080 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305929 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5856 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740339 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3017 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 190756 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 342774 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1435868 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3107979 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100192818 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 116708 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23131891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16353716 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5558 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3773 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3106841 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 111267 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 152585 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 263852 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87883972 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22722991 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 689977 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9488049 # number of nop insts executed -system.cpu.iew.exec_refs 38571182 # number of memory reference insts executed -system.cpu.iew.exec_branches 15118040 # Number of branches executed -system.cpu.iew.exec_stores 15848191 # Number of stores executed -system.cpu.iew.exec_rate 1.925610 # Inst execution rate -system.cpu.iew.wb_sent 87519959 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87118018 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33843453 # num instructions producing a value -system.cpu.iew.wb_consumers 44250497 # num instructions consuming a value -system.cpu.iew.wb_rate 1.908827 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764815 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8632074 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 223532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43575084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.027321 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.870724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22117259 50.76% 50.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6277727 14.41% 65.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2900957 6.66% 71.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1737731 3.99% 75.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1677521 3.85% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1124025 2.58% 82.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1202727 2.76% 85.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795829 1.83% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5741308 13.18% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43575084 # Number of insts commited each cycle -system.cpu.commit.committedInsts 88340672 # Number of instructions committed -system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 34890015 # Number of memory references committed -system.cpu.commit.loads 20276638 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 13754477 # Number of branches committed -system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. -system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. -system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 20276331 22.95% 83.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 14611772 16.54% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 307 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5741308 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 133489180 # The number of ROB reads -system.cpu.rob.rob_writes 195215826 # The number of ROB writes -system.cpu.timesIdled 45373 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 797387 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 79591756 # Number of Instructions Simulated -system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.573421 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.573421 # CPI: Total CPI of All Threads -system.cpu.ipc 1.743921 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.743921 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116327818 # number of integer regfile reads -system.cpu.int_regfile_writes 57658172 # number of integer regfile writes -system.cpu.fp_regfile_reads 255578 # number of floating regfile reads -system.cpu.fp_regfile_writes 240399 # number of floating regfile writes -system.cpu.misc_regfile_reads 38260 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201413 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.948439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33978122 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205509 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.336418 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244590500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.948439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2488 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1533 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70808789 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70808789 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20418812 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20418812 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13559258 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13559258 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33978070 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33978070 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33978070 # number of overall hits -system.cpu.dcache.overall_hits::total 33978070 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269399 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269399 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1054119 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1054119 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1323518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1323518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1323518 # number of overall misses -system.cpu.dcache.overall_misses::total 1323518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19371317500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19371317500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 94432641988 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 94432641988 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113803959488 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113803959488 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113803959488 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113803959488 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20688211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20688211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35301588 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35301588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35301588 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35301588 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072134 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072134 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037492 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037492 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037492 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037492 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71905.677081 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71905.677081 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89584.422620 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89584.422620 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85985.955225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85985.955225 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7415690 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 299 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 82797 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.564719 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 149.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168510 # number of writebacks -system.cpu.dcache.writebacks::total 168510 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207284 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207284 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910725 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910725 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118009 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118009 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118009 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118009 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62115 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62115 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205509 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205509 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205509 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205509 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3617431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3617431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15283982713 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 15283982713 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18901414213 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18901414213 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18901414213 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18901414213 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003002 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005822 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005822 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005822 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58237.647911 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58237.647911 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 106587.323828 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 106587.323828 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90457 # number of replacements -system.cpu.icache.tags.tagsinuse 1914.919853 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13608920 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92505 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.115507 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19216549500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1914.919853 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935019 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935019 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1462 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27520357 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27520357 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 13608920 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13608920 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13608920 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13608920 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13608920 # number of overall hits -system.cpu.icache.overall_hits::total 13608920 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105006 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105006 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105006 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105006 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105006 # number of overall misses -system.cpu.icache.overall_misses::total 105006 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2088801499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2088801499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2088801499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2088801499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2088801499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2088801499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13713926 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13713926 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13713926 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13713926 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13713926 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13713926 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007657 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007657 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007657 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007657 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007657 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007657 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19892.210912 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 19892.210912 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19892.210912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19892.210912 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 683 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.687500 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 90457 # number of writebacks -system.cpu.icache.writebacks::total 90457 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12500 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12500 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12500 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12500 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12500 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12500 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92506 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 92506 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 92506 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 92506 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 92506 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 92506 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1693618500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1693618500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1693618500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1693618500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1693618500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1693618500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006745 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006745 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006745 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18308.201630 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18308.201630 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 134872 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31840.102351 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 422133 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 167640 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.518092 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5003072000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 716.868966 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1773.767441 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29349.465945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021877 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.054131 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.895675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.971683 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2733 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28770 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1005 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4886720 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4886720 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168510 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168510 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 90457 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 90457 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12581 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12581 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86036 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 86036 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34007 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 34007 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 86036 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46588 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132624 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 86036 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46588 # number of overall hits -system.cpu.l2cache.overall_hits::total 132624 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130815 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130815 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6470 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6470 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28106 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 28106 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6470 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158921 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165391 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6470 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158921 # number of overall misses -system.cpu.l2cache.overall_misses::total 165391 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14933033000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14933033000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 647096000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 647096000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3162742000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3162742000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 647096000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18095775000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18742871000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 647096000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18095775000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18742871000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168510 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168510 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 90457 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 90457 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143396 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143396 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92506 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 92506 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62113 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 62113 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 92506 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205509 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 298015 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 92506 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205509 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 298015 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912264 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.912264 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.069941 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.069941 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452498 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452498 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069941 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773304 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.554975 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069941 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773304 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.554975 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 114153.827925 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 114153.827925 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100014.837713 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100014.837713 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112529.068526 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112529.068526 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 113324.612585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 113324.612585 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115198 # number of writebacks -system.cpu.l2cache.writebacks::total 115198 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130815 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130815 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6470 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6470 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28106 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28106 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6470 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158921 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6470 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158921 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165391 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13624883000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13624883000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 582406000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 582406000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2881682000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2881682000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 582406000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16506565000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17088971000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 582406000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16506565000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17088971000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912264 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912264 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452498 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452498 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.554975 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.554975 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 104153.827925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 104153.827925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90016.383308 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90016.383308 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102529.068526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102529.068526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589885 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291870 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4237 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4237 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62113 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275468 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612431 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11709568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23937216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35646784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134872 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7372672 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 432887 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009788 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 428650 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4237 0.98% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432887 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553909500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138764985 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308272981 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130745 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34575 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115197 # Transaction distribution -system.membus.trans_dist::CleanEvict 15548 # Transaction distribution -system.membus.trans_dist::ReadExReq 130815 # Transaction distribution -system.membus.trans_dist::ReadExResp 130815 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461525 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 461525 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17957568 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165390 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165390 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165390 # Request fanout histogram -system.membus.reqLayer0.occupancy 779827500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 851966000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.7 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |