diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 508 |
1 files changed, 254 insertions, 254 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index d5a78ee76..b53980a02 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.009857 # Number of seconds simulated -sim_ticks 1009857089500 # Number of ticks simulated -final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.009999 # Number of seconds simulated +sim_ticks 1009998808500 # Number of ticks simulated +final_tick 1009998808500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137029 # Simulator instruction rate (inst/s) -host_op_rate 137029 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 76042102 # Simulator tick rate (ticks/s) -host_mem_usage 209964 # Number of bytes of host memory used -host_seconds 13280.24 # Real time elapsed on the host +host_inst_rate 135204 # Simulator instruction rate (inst/s) +host_op_rate 135204 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 75039783 # Simulator tick rate (ticks/s) +host_mem_usage 209960 # Number of bytes of host memory used +host_seconds 13459.51 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 172617984 # Number of bytes read from this memory -system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory +system.physmem.bytes_read 172618048 # Number of bytes read from this memory +system.physmem.bytes_inst_read 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written 74938304 # Number of bytes written to this memory -system.physmem.num_reads 2697156 # Number of read requests responded to by this memory +system.physmem.num_reads 2697157 # Number of read requests responded to by this memory system.physmem.num_writes 1170911 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 170933081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 54376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 74206841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 245139922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 170909160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 54432 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 74196428 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 245105588 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614420 # DTB read hits +system.cpu.dtb.read_hits 444614444 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511498 # DTB read accesses -system.cpu.dtb.write_hits 160920903 # DTB write hits +system.cpu.dtb.read_accesses 449511522 # DTB read accesses +system.cpu.dtb.write_hits 160920906 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162622207 # DTB write accesses -system.cpu.dtb.data_hits 605535323 # DTB hits +system.cpu.dtb.write_accesses 162622210 # DTB write accesses +system.cpu.dtb.data_hits 605535350 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612133705 # DTB accesses -system.cpu.itb.fetch_hits 233080732 # ITB hits +system.cpu.dtb.data_accesses 612133732 # DTB accesses +system.cpu.itb.fetch_hits 231980230 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 233080754 # ITB accesses +system.cpu.itb.fetch_accesses 231980252 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -54,16 +54,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2019714180 # number of cpu cycles simulated +system.cpu.numCycles 2019997618 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746235830 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1746428176 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7533712 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 442869413 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576844767 # Number of cycles cpu stages are processed. -system.cpu.activity 78.072669 # Percentage of cycles cpu is active +system.cpu.timesIdled 7533729 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 443112454 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576885164 # Number of cycles cpu stages are processed. +system.cpu.activity 78.063714 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -75,158 +75,158 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.110023 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901009 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.110023 # CPI: Total CPI of All Threads +system.cpu.ipc 0.900882 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.901009 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 330376347 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 257464252 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140461747 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 220099806 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 142435401 # Number of BTB hits +system.cpu.ipc_total 0.900882 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 328891112 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253883187 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 140042357 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232477361 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138151285 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 64.714006 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 178933469 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 151442878 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1665721133 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.425694 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175108073 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153783039 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669728742 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3041923750 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045931359 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 235 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 654640669 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617252269 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 126684712 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 7178577 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133863289 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81336473 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.204199 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1137868323 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 580 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651109695 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617989652 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121368305 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12075594 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133443899 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81756170 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 62.009227 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139611303 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 827214176 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1192500004 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.043008 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1086300254 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933413926 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.215149 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1046559994 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973154186 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.182767 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1609984436 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409729744 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.286521 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 997434545 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022279635 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 50.615065 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 829317091 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190680527 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.944650 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1087591326 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932406292 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.158782 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1046003601 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973994017 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.217582 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1610294122 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409703496 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.282375 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 997062989 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022934629 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.640388 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 664.479191 # Cycle average of tags in use -system.cpu.icache.total_refs 233079667 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 666.311000 # Cycle average of tags in use +system.cpu.icache.total_refs 231979155 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 270057.223516 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 664.479191 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.324453 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.324453 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 233079667 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 233079667 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 233079667 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 233079667 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 233079667 # number of overall hits -system.cpu.icache.overall_hits::total 233079667 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1062 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1062 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1062 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1062 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1062 # number of overall misses -system.cpu.icache.overall_misses::total 1062 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58337000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58337000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58337000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58337000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58337000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58337000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 233080729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 233080729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 233080729 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 233080729 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 233080729 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 233080729 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.311000 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325347 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325347 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231979155 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231979155 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231979155 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231979155 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231979155 # number of overall hits +system.cpu.icache.overall_hits::total 231979155 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1072 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1072 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1072 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1072 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1072 # number of overall misses +system.cpu.icache.overall_misses::total 1072 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58539000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58539000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58539000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58539000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58539000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58539000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231980227 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231980227 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231980227 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231980227 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231980227 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231980227 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54931.261770 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54607.276119 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54607.276119 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 125500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31375 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 204 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 204 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 204 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 204 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 858 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 858 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 858 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45872500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45872500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45872500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45872500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45872500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45872500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 213 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 213 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 213 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 213 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45929000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45929000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45929000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45929000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53464.452214 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53467.986030 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53467.986030 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements -system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use -system.cpu.dcache.total_refs 595070081 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4082.536815 # Cycle average of tags in use +system.cpu.dcache.total_refs 595069970 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.611665 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996731 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996731 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271428 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157798653 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157798653 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595070081 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595070081 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595070081 # number of overall hits -system.cpu.dcache.overall_hits::total 595070081 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324235 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324235 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2929849 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2929849 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10254084 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10254084 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10254084 # number of overall misses -system.cpu.dcache.overall_misses::total 10254084 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 180892053500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 180892053500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 110288339500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 110288339500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 291180393000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 291180393000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 291180393000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 291180393000 # number of overall miss cycles +system.cpu.dcache.avg_refs 65.310143 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12672189000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.536815 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996713 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996713 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271423 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271423 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157798547 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157798547 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595069970 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595069970 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595069970 # number of overall hits +system.cpu.dcache.overall_hits::total 595069970 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324240 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324240 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2929955 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2929955 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10254195 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10254195 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10254195 # number of overall misses +system.cpu.dcache.overall_misses::total 10254195 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 180897499500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 180897499500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110294932000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110294932000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 291192431500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 291192431500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 291192431500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 291192431500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -239,28 +239,28 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24697.740242 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.011466 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208994 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24698.466940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.899650 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28397.395554 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 11000000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8092150500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2762 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 209020 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3982.621289 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 38714.718687 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks system.cpu.dcache.writebacks::total 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101953 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101953 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040683 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1040683 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1142636 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1142636 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1142636 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1142636 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101958 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101958 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040789 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1040789 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1142747 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1142747 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1142747 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1142747 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses @@ -269,36 +269,36 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156087671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 156087671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215279506500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 215279506500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215279506500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215279506500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156091594000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 156091594000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191446500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191446500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215283040500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215283040500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215283040500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215283040500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21611.960181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.257462 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21612.503361 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.051551 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.752746 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2686299 # number of replacements -system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7564573 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10843.964569 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 26.537327 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15484.737472 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.330932 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.472557 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.804298 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 2686301 # number of replacements +system.cpu.l2cache.tagsinuse 26348.804807 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7564571 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2710944 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.790383 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 224336260000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 10843.214494 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.756246 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15478.834067 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.330909 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000817 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.472377 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.804102 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits @@ -309,41 +309,41 @@ system.cpu.l2cache.demand_hits::cpu.data 6415150 # nu system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 858 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1807023 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1807881 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1807882 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 889275 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 889275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 858 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 2696298 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2697156 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 858 # number of overall misses +system.cpu.l2cache.demand_misses::total 2697157 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2696298 # number of overall misses -system.cpu.l2cache.overall_misses::total 2697156 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44903500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94408605500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94453509000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46507390000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 46507390000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44903500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 140915995500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 140960899000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44903500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 140915995500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 140960899000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 858 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 2697157 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44955000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94411778000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94456733000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46506892000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46506892000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44955000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 140918670000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 140963625000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44955000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 140918670000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 140963625000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221840 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222699 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 3058572 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 3058572 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889608 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1889608 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 858 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112306 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 858 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112307 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112307 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses @@ -351,13 +351,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52335.081585 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52245.381215 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52298.096764 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52334.109430 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52247.136865 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52297.536757 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52334.109430 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.759421 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -368,28 +368,28 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks system.cpu.l2cache.writebacks::total 1170911 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1807881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1807882 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889275 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 889275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2696298 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2697156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2697157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2696298 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2697156 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34440500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319858000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354298500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671113500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671113500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34440500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990971500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 108025412000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34440500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990971500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 108025412000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 2697157 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34480500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319844500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354325000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671150000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671150000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34480500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990994500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108025475000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34480500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990994500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108025475000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses @@ -397,13 +397,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.442890 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.548149 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.578786 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.279395 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.540678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.619831 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.279395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.579796 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |