diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 423 |
1 files changed, 204 insertions, 219 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index bbfef95ab..4d872659d 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.993559 # Nu sim_ticks 993559170500 # Number of ticks simulated final_tick 993559170500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 148425 # Simulator instruction rate (inst/s) -host_op_rate 148425 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 81036604 # Simulator tick rate (ticks/s) -host_mem_usage 464668 # Number of bytes of host memory used -host_seconds 12260.62 # Real time elapsed on the host +host_inst_rate 139940 # Simulator instruction rate (inst/s) +host_op_rate 139940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76403951 # Simulator tick rate (ticks/s) +host_mem_usage 449176 # Number of bytes of host memory used +host_seconds 13004.03 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory @@ -85,30 +85,17 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 1959688 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 1018171 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1630106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 87736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35917 # What read queue length does an incoming req see +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 1018058 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1630116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 205318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 87737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 35934 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -137,9 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 41624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 43773 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44240 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44256 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44259 # What write queue length does an incoming req see @@ -162,7 +148,7 @@ system.physmem.wrQLenPdf::20 44263 # Wh system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 2640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 491 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see @@ -170,15 +156,14 @@ system.physmem.wrQLenPdf::28 5 # Wh system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 35848625999 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 104288840999 # Sum of mem lat for all requests +system.physmem.totQLat 35843451500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 104284202750 # Sum of mem lat for all requests system.physmem.totBusLat 9795530000 # Total cycles spent in databus access -system.physmem.totBankLat 58644685000 # Total cycles spent in bank access -system.physmem.avgQLat 18298.46 # Average queueing delay per request -system.physmem.avgBankLat 29934.41 # Average bank access latency per request +system.physmem.totBankLat 58645221250 # Total cycles spent in bank access +system.physmem.avgQLat 18295.82 # Average queueing delay per request +system.physmem.avgBankLat 29934.69 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53232.87 # Average memory access latency +system.physmem.avgMemAccLat 53230.51 # Average memory access latency system.physmem.avgRdBW 126.23 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 65.58 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 126.23 # Average consumed read bandwidth in MB/s @@ -187,13 +172,13 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time system.physmem.avgWrQLen 10.46 # Average write queue length over time -system.physmem.readRowHits 770935 # Number of row buffer hits during reads -system.physmem.writeRowHits 285714 # Number of row buffer hits during writes +system.physmem.readRowHits 770937 # Number of row buffer hits during reads +system.physmem.writeRowHits 285715 # Number of row buffer hits during writes system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes system.physmem.avgGap 333661.47 # Average gap between requests system.cpu.branchPred.lookups 326540496 # Number of BP lookups -system.cpu.branchPred.condPredicted 252608544 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 252608543 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 138248451 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 220022753 # Number of BTB lookups system.cpu.branchPred.BTBHits 135563778 # Number of BTB hits @@ -205,22 +190,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444796007 # DTB read hits +system.cpu.dtb.read_hits 444796009 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449693085 # DTB read accesses -system.cpu.dtb.write_hits 160833351 # DTB write hits +system.cpu.dtb.read_accesses 449693087 # DTB read accesses +system.cpu.dtb.write_hits 160833358 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534655 # DTB write accesses -system.cpu.dtb.data_hits 605629358 # DTB hits +system.cpu.dtb.write_accesses 162534662 # DTB write accesses +system.cpu.dtb.data_hits 605629367 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612227740 # DTB accesses -system.cpu.itb.fetch_hits 232025962 # ITB hits +system.cpu.dtb.data_accesses 612227749 # DTB accesses +system.cpu.itb.fetch_hits 232025963 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232025984 # ITB accesses +system.cpu.itb.fetch_accesses 232025985 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -237,16 +222,16 @@ system.cpu.workload.num_syscalls 29 # Nu system.cpu.numCycles 1987118342 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172378846 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154161650 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667662469 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172378847 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154161649 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667662468 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043865086 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 3043865085 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 230 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 575 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651727789 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884568 # Number of Address Generations +system.cpu.regfile_manager.regForwards 651727790 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884569 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 120519408 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 11130585 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 131649993 # Number of Branches Incorrectly Predicted @@ -256,12 +241,12 @@ system.cpu.execution_unit.executions 1139371391 # Nu system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1741838166 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741838474 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7484554 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415293759 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571824583 # Number of cycles cpu stages are processed. -system.cpu.activity 79.100703 # Percentage of cycles cpu is active +system.cpu.timesIdled 7484621 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415293731 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571824611 # Number of cycles cpu stages are processed. +system.cpu.activity 79.100705 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -279,66 +264,66 @@ system.cpu.cpi_total 1.091955 # CP system.cpu.ipc 0.915789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.915789 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 800261653 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186856689 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.727529 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1053419210 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933699132 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.idleCycles 800261647 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186856695 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.727530 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1053419200 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933699142 # Number of cycles 1+ instructions are processed. system.cpu.stage1.utilization 46.987596 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1014725197 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972393145 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.934838 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1577495451 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409622891 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.idleCycles 1014725184 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972393158 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.934839 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1577495448 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409622894 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 20.613915 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 965781597 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021336745 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.idleCycles 965781598 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021336744 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 51.397882 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements system.cpu.icache.tagsinuse 667.839755 # Cycle average of tags in use -system.cpu.icache.total_refs 232024853 # Total number of references to valid blocks. +system.cpu.icache.total_refs 232024854 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270110.422584 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270110.423749 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 667.839755 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.326094 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.326094 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232024853 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232024853 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232024853 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232024853 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232024853 # number of overall hits -system.cpu.icache.overall_hits::total 232024853 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 232024854 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232024854 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232024854 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232024854 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232024854 # number of overall hits +system.cpu.icache.overall_hits::total 232024854 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 1109 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1109 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 1109 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1109 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 1109 # number of overall misses system.cpu.icache.overall_misses::total 1109 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64824000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64824000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64824000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232025962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232025962 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232025962 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232025962 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232025962 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232025962 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 64819000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 64819000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 64819000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 64819000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 64819000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 64819000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232025963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232025963 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232025963 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232025963 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232025963 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232025963 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58452.660054 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58452.660054 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58452.660054 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58452.660054 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58452.660054 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58448.151488 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 58448.151488 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 58448.151488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 58448.151488 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 58448.151488 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -359,34 +344,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 859 system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51094000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 51094000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51094000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 51094000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51094000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 51094000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51089000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51089000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51089000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51089000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59480.791618 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59480.791618 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59480.791618 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59480.791618 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59474.970896 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59474.970896 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59474.970896 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59474.970896 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 1926957 # number of replacements -system.cpu.l2cache.tagsinuse 30901.189493 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 30901.189526 # Cycle average of tags in use system.cpu.l2cache.total_refs 8958712 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 1956750 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 4.578363 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 67146389752 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15036.220551 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.907128 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15830.061814 # Average occupied blocks per requestor +system.cpu.l2cache.warmup_cycle 67146389751 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15036.225587 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 34.907127 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15830.056812 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::writebacks 0.458869 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001065 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.483095 # Average percentage of cache occupancy @@ -412,17 +397,17 @@ system.cpu.l2cache.demand_misses::total 1959688 # nu system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958829 # number of overall misses system.cpu.l2cache.overall_misses::total 1959688 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50231000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163632000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 83213863000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66179053000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 66179053000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 50231000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 149342685000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 149392916000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 50231000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 149342685000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 149392916000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 50226000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 83163468000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 83213694000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66176738000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 66176738000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 50226000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 149340206000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 149390432000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 50226000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 149340206000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 149390432000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7221841 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7222700 # number of ReadReq accesses(hits+misses) @@ -447,17 +432,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58476.135041 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.488947 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.632538 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84703.875213 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84703.875213 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76233.010561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58476.135041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76240.797436 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76233.010561 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 58470.314319 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70625.349673 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70616.489122 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84700.912199 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84700.912199 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76231.743012 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 58470.314319 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76239.531884 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76231.743012 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,17 +464,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959688 system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958829 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959688 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39571189 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68487354640 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68526925829 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56485658700 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56485658700 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39571189 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124973013340 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 125012584529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39571189 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124973013340 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 125012584529 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39565474 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 68486082132 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 68525647606 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56482752358 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56482752358 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39565474 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124968834490 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 125008399964 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39565474 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124968834490 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 125008399964 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses @@ -501,51 +486,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46066.576251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58161.876674 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58153.059668 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72297.108661 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72297.108661 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46066.576251 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63799.858660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63792.085541 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46059.923166 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58160.796015 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58151.974947 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72293.388777 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72293.388777 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46059.923166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63797.725320 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63789.950219 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107372 # number of replacements system.cpu.dcache.tagsinuse 4082.262475 # Cycle average of tags in use -system.cpu.dcache.total_refs 593512880 # Total number of references to valid blocks. +system.cpu.dcache.total_refs 593512840 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 9111468 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.139106 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 65.139102 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 4082.262475 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268758 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156244122 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156244122 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593512880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593512880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593512880 # number of overall hits -system.cpu.dcache.overall_hits::total 593512880 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 156244082 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156244082 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593512840 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593512840 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593512840 # number of overall hits +system.cpu.dcache.overall_hits::total 593512840 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7326905 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7326905 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4484380 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4484380 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 11811285 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11811285 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11811285 # number of overall misses -system.cpu.dcache.overall_misses::total 11811285 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288165500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 167288165500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 202507086500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 202507086500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 369795252000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 369795252000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 369795252000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 369795252000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 4484420 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4484420 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 11811325 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11811325 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11811325 # number of overall misses +system.cpu.dcache.overall_misses::total 11811325 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 167288000500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 167288000500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 202511222000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 202511222000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 369799222500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 369799222500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 369799222500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 369799222500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -556,38 +541,38 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027900 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027900 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027901 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027901 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.019512 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.019512 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.019512 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.019512 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.036924 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.036924 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.324339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.324339 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31308.638476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.638476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31308.638476 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13465460 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4770860 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 372579 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22832.014404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22832.014404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45158.843730 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45158.843730 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31308.868607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31308.868607 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31308.868607 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13465422 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4771270 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 372557 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65753 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.141221 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.557298 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.143253 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.563533 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 3693293 # number of writebacks system.cpu.dcache.writebacks::total 3693293 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104622 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 104622 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595195 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2595195 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2699817 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2699817 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2699817 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2699817 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595235 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2595235 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2699857 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2699857 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2699857 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2699857 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222283 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222283 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889185 # number of WriteReq MSHR misses @@ -596,14 +581,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9111468 system.cpu.dcache.demand_mshr_misses::total 9111468 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9111468 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9111468 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964459500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79317190500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 79317190500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230281650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230281650000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230281650000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230281650000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150964297500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 150964297500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79314869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 79314869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230279166500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 230279166500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230279166500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 230279166500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -612,14 +597,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.595412 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.595412 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41984.872048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41984.872048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.825250 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.825250 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20902.572981 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20902.572981 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41983.643211 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41983.643211 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25273.552681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25273.552681 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |