diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 724 |
1 files changed, 362 insertions, 362 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 9335161f5..7470c11aa 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.987579 # Number of seconds simulated -sim_ticks 987579062500 # Number of ticks simulated -final_tick 987579062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.985090 # Number of seconds simulated +sim_ticks 985089830500 # Number of ticks simulated +final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79028 # Simulator instruction rate (inst/s) -host_op_rate 79028 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42888030 # Simulator tick rate (ticks/s) -host_mem_usage 458304 # Number of bytes of host memory used -host_seconds 23026.92 # Real time elapsed on the host +host_inst_rate 109003 # Simulator instruction rate (inst/s) +host_op_rate 109003 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59005665 # Simulator tick rate (ticks/s) +host_mem_usage 485696 # Number of bytes of host memory used +host_seconds 16694.83 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125364928 # Number of bytes read from this memory -system.physmem.bytes_read::total 125419904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125364992 # Number of bytes read from this memory +system.physmem.bytes_read::total 125419968 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 65155520 # Number of bytes written to this memory system.physmem.bytes_written::total 65155520 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958827 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959686 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1958828 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959687 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1018055 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018055 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 126941662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 126997330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55667 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55667 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 65974991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 65974991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 65974991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 126941662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 192972321 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959686 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 55808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 127262497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 127318306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 66141704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 66141704 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 66141704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 127262497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193460010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959687 # Total number of read requests seen system.physmem.writeReqs 1018055 # Total number of write requests seen -system.physmem.cpureqs 2977741 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125419904 # Total number of bytes read from memory +system.physmem.cpureqs 2977742 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125419968 # Total number of bytes read from memory system.physmem.bytesWritten 65155520 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125419904 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 125419968 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 65155520 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 577 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 582 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 123238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 122431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 123239 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 122861 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 121276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 122601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 122602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 122222 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 124477 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 123481 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 121547 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 122168 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 122611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 120103 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 122610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 120102 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 120483 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 121941 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 124488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123178 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123177 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 63120 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 63437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 63438 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 63830 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 63407 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 63139 # Track writes on a per bank basis @@ -69,7 +69,7 @@ system.physmem.perBankWrReqs::6 63395 # Tr system.physmem.perBankWrReqs::7 63432 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 62525 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 63278 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63961 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 63960 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 63327 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 63976 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 64713 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 65307 # Tr system.physmem.perBankWrReqs::15 64492 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 987579010500 # Total gap between requests +system.physmem.totGap 985089778500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959686 # Categorize read packet sizes +system.physmem.readPktSize::6 1959687 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -105,10 +105,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1651837 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192315 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 82006 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1651728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 192414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82029 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32933 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -138,9 +138,9 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see @@ -161,9 +161,9 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see @@ -171,47 +171,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 19599583947 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 85189869947 # Sum of mem lat for all requests -system.physmem.totBusLat 7836436000 # Total cycles spent in databus access -system.physmem.totBankLat 57753850000 # Total cycles spent in bank access -system.physmem.avgQLat 10004.34 # Average queueing delay per request -system.physmem.avgBankLat 29479.65 # Average bank access latency per request +system.physmem.totQLat 19640844571 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 85229742571 # Sum of mem lat for all requests +system.physmem.totBusLat 7836420000 # Total cycles spent in databus access +system.physmem.totBankLat 57752478000 # Total cycles spent in bank access +system.physmem.avgQLat 10025.42 # Average queueing delay per request +system.physmem.avgBankLat 29479.01 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 43483.99 # Average memory access latency -system.physmem.avgRdBW 127.00 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 65.97 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 127.00 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 65.97 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 43504.43 # Average memory access latency +system.physmem.avgRdBW 127.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 66.14 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 127.32 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 66.14 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 1.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.09 # Average read queue length over time system.physmem.avgWrQLen 10.28 # Average write queue length over time -system.physmem.readRowHits 834542 # Number of row buffer hits during reads -system.physmem.writeRowHits 194109 # Number of row buffer hits during writes +system.physmem.readRowHits 834572 # Number of row buffer hits during reads +system.physmem.writeRowHits 194113 # Number of row buffer hits during writes system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes -system.physmem.avgGap 331653.76 # Average gap between requests +system.physmem.avgGap 330817.71 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444784364 # DTB read hits +system.cpu.dtb.read_hits 444784566 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449681442 # DTB read accesses -system.cpu.dtb.write_hits 160833165 # DTB write hits +system.cpu.dtb.read_accesses 449681644 # DTB read accesses +system.cpu.dtb.write_hits 160833172 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534469 # DTB write accesses -system.cpu.dtb.data_hits 605617529 # DTB hits +system.cpu.dtb.write_accesses 162534476 # DTB write accesses +system.cpu.dtb.data_hits 605617738 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612215911 # DTB accesses -system.cpu.itb.fetch_hits 232120860 # ITB hits +system.cpu.dtb.data_accesses 612216120 # DTB accesses +system.cpu.itb.fetch_hits 231916745 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232120882 # ITB accesses +system.cpu.itb.fetch_accesses 231916767 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -225,42 +225,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1975158126 # number of cpu cycles simulated +system.cpu.numCycles 1970179662 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328916009 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253846257 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140045817 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 232481413 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138136467 # Number of BTB hits +system.cpu.branch_predictor.lookups 326556831 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 252596788 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 138232865 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 218937552 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 135479530 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.418284 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175138589 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153777420 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669811898 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 61.880444 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3046014515 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043822969 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 650984890 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617988746 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121313944 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12133415 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133447359 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81752917 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.010775 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139622793 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651716748 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617888959 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120522099 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11112308 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131634407 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83565858 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.168329 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139351244 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746581569 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1741570972 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7474420 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 398305853 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1576852273 # Number of cycles cpu stages are processed. -system.cpu.activity 79.834230 # Percentage of cycles cpu is active +system.cpu.timesIdled 7474606 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 398498363 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571681299 # Number of cycles cpu stages are processed. +system.cpu.activity 79.773501 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -272,72 +272,72 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.085383 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.082647 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.085383 # CPI: Total CPI of All Threads -system.cpu.ipc 0.921334 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.082647 # CPI: Total CPI of All Threads +system.cpu.ipc 0.923662 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.921334 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 784384186 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190773940 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.287525 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1042820423 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932337703 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.203193 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1001198544 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 973959582 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.310461 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1565492748 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409665378 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.740890 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 952315389 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022842737 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.785360 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.923662 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 783567133 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186612529 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.228646 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1036391021 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933788641 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 47.396116 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 997796043 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972383619 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.355073 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1560555740 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409623922 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.791196 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 948846788 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021332874 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.839581 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.497042 # Cycle average of tags in use -system.cpu.icache.total_refs 232119756 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 667.601881 # Cycle average of tags in use +system.cpu.icache.total_refs 231915637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270220.903376 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269983.279395 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.497042 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325926 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325926 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232119756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232119756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232119756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232119756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232119756 # number of overall hits -system.cpu.icache.overall_hits::total 232119756 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1104 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1104 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1104 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1104 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1104 # number of overall misses -system.cpu.icache.overall_misses::total 1104 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58767000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58767000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58767000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58767000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58767000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58767000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232120860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232120860 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232120860 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232120860 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232120860 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232120860 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 667.601881 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325977 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325977 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231915637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231915637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231915637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231915637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231915637 # number of overall hits +system.cpu.icache.overall_hits::total 231915637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses +system.cpu.icache.overall_misses::total 1108 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 59929000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 59929000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 59929000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 59929000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 59929000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 59929000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231916745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231916745 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231916745 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231916745 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231916745 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231916745 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53230.978261 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53230.978261 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53230.978261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53230.978261 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53230.978261 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54087.545126 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54087.545126 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54087.545126 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54087.545126 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54087.545126 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -346,203 +346,95 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 63 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 249 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 249 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 249 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 249 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46993000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46993000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46993000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46993000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46993000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46993000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47313000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47313000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47313000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47313000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47313000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47313000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54706.635623 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54706.635623 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54706.635623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54706.635623 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55079.161816 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55079.161816 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55079.161816 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55079.161816 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107377 # number of replacements -system.cpu.dcache.tagsinuse 4082.124534 # Cycle average of tags in use -system.cpu.dcache.total_refs 593539067 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111473 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.141944 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12681076000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.124534 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996612 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996612 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437268755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437268755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156270312 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156270312 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593539067 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593539067 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593539067 # number of overall hits -system.cpu.dcache.overall_hits::total 593539067 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7326908 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7326908 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4458190 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4458190 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 11785098 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11785098 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11785098 # number of overall misses -system.cpu.dcache.overall_misses::total 11785098 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 160313092500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 160313092500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195290221000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195290221000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 355603313500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 355603313500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 355603313500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 355603313500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027737 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027737 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21880.047149 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21880.047149 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43804.822361 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43804.822361 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30173.980182 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.980182 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30173.980182 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9234267 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4818811 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 358092 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65601 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.787415 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 73.456365 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693297 # number of writebacks -system.cpu.dcache.writebacks::total 3693297 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568993 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2568993 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2673625 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2673625 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2673625 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2673625 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222276 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222276 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889197 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889197 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111473 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111473 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111473 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111473 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144007395000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 144007395000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67943434500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 67943434500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211950829500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211950829500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211950829500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211950829500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19939.336990 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19939.336990 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35964.187165 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35964.187165 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23261.971967 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23261.971967 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1926955 # number of replacements -system.cpu.l2cache.tagsinuse 30885.794112 # Cycle average of tags in use +system.cpu.l2cache.replacements 1926956 # number of replacements +system.cpu.l2cache.tagsinuse 30892.708902 # Cycle average of tags in use system.cpu.l2cache.total_refs 8958711 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1956748 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.578367 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 67633900002 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 15038.473814 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 35.309498 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 15812.010801 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.458938 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001078 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.482544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.942560 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 6044303 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6044303 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3693297 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3693297 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1108343 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1108343 # number of ReadExReq hits +system.cpu.l2cache.sampled_refs 1956749 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 4.578365 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 67095700002 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 15036.085957 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 35.170225 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15821.452721 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.458865 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001073 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.482832 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.942771 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 6044304 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6044304 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3693296 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3693296 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1108342 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1108342 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.data 7152646 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 7152646 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.data 7152646 # number of overall hits system.cpu.l2cache.overall_hits::total 7152646 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1177531 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1178390 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1177532 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1178391 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1958827 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1959686 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1958828 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1959687 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1958827 # number of overall misses -system.cpu.l2cache.overall_misses::total 1959686 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46130000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76211329000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 76257459000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 54802656500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 54802656500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46130000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 131013985500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 131060115500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46130000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 131013985500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 131060115500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 1958828 # number of overall misses +system.cpu.l2cache.overall_misses::total 1959687 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76219681500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 76266131500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 54834553000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 54834553000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46450000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 131054234500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 131100684500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46450000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 131054234500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 131100684500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221834 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222693 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3693297 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3693297 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889639 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889639 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221836 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222695 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3693296 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3693296 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889638 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889638 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111473 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111474 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112333 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111473 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112332 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111474 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112333 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses @@ -554,17 +446,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215059 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53701.979045 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64721.293112 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 64713.260466 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70143.270284 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70143.270284 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66878.120015 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53701.979045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66883.898119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66878.120015 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54074.505239 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64728.331374 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 64720.565160 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70184.095400 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70184.095400 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66898.787664 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54074.505239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66904.411464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66898.787664 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -576,27 +468,27 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 1018055 # number of writebacks system.cpu.l2cache.writebacks::total 1018055 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177531 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1178390 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177532 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1178391 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1958827 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1959686 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1958828 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1959687 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1958827 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1959686 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35264420 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61190782598 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61226047018 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44920930070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44920930070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35264420 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106111712668 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 106146977088 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35264420 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106111712668 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 106146977088 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958828 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959687 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35585421 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 61199276421 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 61234861842 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44953209175 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44953209175 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35585421 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106152485596 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 106188071017 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35585421 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106152485596 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 106188071017 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses @@ -608,17 +500,125 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41052.875437 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51965.326261 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51957.371514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57495.405160 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57495.405160 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41052.875437 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54171.048627 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54165.298465 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41426.566938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 51972.495373 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51964.807812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57536.719982 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57536.719982 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41426.566938 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 54191.835933 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54186.240464 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 9107378 # number of replacements +system.cpu.dcache.tagsinuse 4082.173275 # Cycle average of tags in use +system.cpu.dcache.total_refs 593539212 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111474 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.141953 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12614691000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.173275 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996624 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996624 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437268752 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437268752 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 156270460 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156270460 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593539212 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593539212 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593539212 # number of overall hits +system.cpu.dcache.overall_hits::total 593539212 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7326911 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7326911 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4458042 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4458042 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 11784953 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 11784953 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 11784953 # number of overall misses +system.cpu.dcache.overall_misses::total 11784953 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 160323624500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 160323624500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 195351556000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 195351556000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 355675180500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 355675180500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 355675180500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 355675180500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027736 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027736 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019469 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019469 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019469 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019469 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21881.475631 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21881.475631 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43820.034894 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43820.034894 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30180.449638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30180.449638 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30180.449638 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9247830 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 4818517 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 358256 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65602 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 25.813469 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 73.450764 # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3693296 # number of writebacks +system.cpu.dcache.writebacks::total 3693296 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104633 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104633 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2568846 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2568846 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2673479 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2673479 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2673479 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2673479 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222278 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222278 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889196 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111474 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111474 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111474 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111474 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 144015924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 144015924000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67975303000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67975303000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211991227000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 211991227000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211991227000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 211991227000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19940.512398 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19940.512398 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35981.075018 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35981.075018 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23266.403109 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23266.403109 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |