diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 402 |
1 files changed, 248 insertions, 154 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index bf815a6e1..d5a78ee76 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.009857 # Nu sim_ticks 1009857089500 # Number of ticks simulated final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102085 # Simulator instruction rate (inst/s) -host_tick_rate 56650413 # Simulator tick rate (ticks/s) -host_mem_usage 208040 # Number of bytes of host memory used -host_seconds 17826.12 # Real time elapsed on the host +host_inst_rate 137029 # Simulator instruction rate (inst/s) +host_op_rate 137029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76042102 # Simulator tick rate (ticks/s) +host_mem_usage 209964 # Number of bytes of host memory used +host_seconds 13280.24 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated +sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read 172617984 # Number of bytes read from this memory system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory system.physmem.bytes_written 74938304 # Number of bytes written to this memory @@ -69,9 +71,10 @@ system.cpu.comNops 83736345 # Nu system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed system.cpu.comInts 916086844 # Number of Integer instructions committed system.cpu.comFloats 190 # Number of Floating Point instructions committed -system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads @@ -125,26 +128,39 @@ system.cpu.icache.total_refs 233079667 # To system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 664.479191 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.324453 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 233079667 # number of ReadReq hits -system.cpu.icache.demand_hits 233079667 # number of demand (read+write) hits -system.cpu.icache.overall_hits 233079667 # number of overall hits -system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses -system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses -system.cpu.icache.overall_misses 1062 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 58337000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 58337000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 58337000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 233080729 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 233080729 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 233080729 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 54931.261770 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 54931.261770 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 54931.261770 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 664.479191 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.324453 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.324453 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 233079667 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 233079667 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 233079667 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 233079667 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 233079667 # number of overall hits +system.cpu.icache.overall_hits::total 233079667 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1062 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1062 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1062 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1062 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1062 # number of overall misses +system.cpu.icache.overall_misses::total 1062 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 58337000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 58337000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 58337000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 58337000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 58337000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 58337000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 233080729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 233080729 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 233080729 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 233080729 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 233080729 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 233080729 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54931.261770 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 204 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 204 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 204 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 858 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 45872500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 45872500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 45872500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 204 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 204 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 204 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 204 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 204 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 858 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 858 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 858 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45872500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 45872500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45872500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 45872500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45872500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 45872500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53464.452214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 9107352 # number of replacements system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use @@ -181,32 +200,49 @@ system.cpu.dcache.total_refs 595070081 # To system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 4082.611665 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.996731 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 437271428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 157798653 # number of WriteReq hits -system.cpu.dcache.demand_hits 595070081 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 595070081 # number of overall hits -system.cpu.dcache.ReadReq_misses 7324235 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 2929849 # number of WriteReq misses -system.cpu.dcache.demand_misses 10254084 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 10254084 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 180892053500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110288339500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 291180393000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 291180393000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.018229 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 28396.528934 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 28396.528934 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 4082.611665 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996731 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996731 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271428 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271428 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157798653 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157798653 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595070081 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595070081 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595070081 # number of overall hits +system.cpu.dcache.overall_hits::total 595070081 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324235 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324235 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2929849 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2929849 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10254084 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10254084 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10254084 # number of overall misses +system.cpu.dcache.overall_misses::total 10254084 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 180892053500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 180892053500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 110288339500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 110288339500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 291180393000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 291180393000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 291180393000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 291180393000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018229 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016940 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016940 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24697.740242 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.011466 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked @@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 3983.701557 system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 3058572 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 101953 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1040683 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1142636 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1142636 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 59191835500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 215279506500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 215279506500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.015052 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 3058572 # number of writebacks +system.cpu.dcache.writebacks::total 3058572 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101953 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101953 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1040683 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1040683 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1142636 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1142636 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1142636 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1142636 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222282 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889166 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889166 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156087671000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 156087671000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59191835500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 59191835500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215279506500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215279506500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215279506500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215279506500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21611.960181 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.257462 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2686299 # number of replacements system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use @@ -248,36 +292,72 @@ system.cpu.l2cache.total_refs 7564573 # To system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 15511.274798 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10843.964569 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.473367 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::1 0.330932 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 5414817 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits 3058572 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits 1000333 # number of ReadExReq hits -system.cpu.l2cache.demand_hits 6415150 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 6415150 # number of overall hits -system.cpu.l2cache.ReadReq_misses 1807881 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 889275 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 2697156 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 2697156 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 94453509000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 46507390000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 140960899000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 140960899000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 7222698 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses 3058572 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 1889608 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 9112306 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 9112306 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.250305 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 0.470613 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.295990 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.295990 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52262.790510 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52262.790510 # average overall miss latency +system.cpu.l2cache.occ_blocks::writebacks 10843.964569 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 26.537327 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 15484.737472 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.330932 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.000810 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.472557 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.804298 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5414817 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5414817 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3058572 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3058572 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1000333 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1000333 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6415150 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 6415150 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 6415150 # number of overall hits +system.cpu.l2cache.overall_hits::total 6415150 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 858 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1807023 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1807881 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 889275 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 889275 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 858 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2696298 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2697156 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 858 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2696298 # number of overall misses +system.cpu.l2cache.overall_misses::total 2697156 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44903500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94408605500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 94453509000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 46507390000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 46507390000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 44903500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 140915995500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 140960899000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 44903500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 140915995500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 140960899000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 858 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221840 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3058572 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3058572 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889608 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889608 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 858 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111448 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112306 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 858 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111448 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112306 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250216 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.470613 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.295924 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.295924 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52335.081585 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52245.381215 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52298.096764 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52335.081585 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52262.767506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked @@ -286,30 +366,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 1170911 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 1807881 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 889275 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 72354298500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671113500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 108025412000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 108025412000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250305 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470613 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.295990 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.writebacks::writebacks 1170911 # number of writebacks +system.cpu.l2cache.writebacks::total 1170911 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 858 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1807023 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1807881 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 889275 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 889275 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 858 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2696298 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2697156 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 858 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2696298 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2697156 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34440500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 72319858000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 72354298500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35671113500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35671113500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34440500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 108025412000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34440500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990971500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 108025412000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250216 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295924 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.442890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.548149 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.578786 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |