diff options
Diffstat (limited to 'tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt')
| -rw-r--r-- | tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 668 |
1 files changed, 334 insertions, 334 deletions
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 35d38838f..def42a9fe 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,59 +1,59 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.991340 # Number of seconds simulated -sim_ticks 991340143500 # Number of ticks simulated -final_tick 991340143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.996061 # Number of seconds simulated +sim_ticks 996061088500 # Number of ticks simulated +final_tick 996061088500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147354 # Simulator instruction rate (inst/s) -host_op_rate 147354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 80272080 # Simulator tick rate (ticks/s) -host_mem_usage 218972 # Number of bytes of host memory used -host_seconds 12349.75 # Real time elapsed on the host +host_inst_rate 139633 # Simulator instruction rate (inst/s) +host_op_rate 139633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 76428343 # Simulator tick rate (ticks/s) +host_mem_usage 218940 # Number of bytes of host memory used +host_seconds 13032.61 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137579712 # Number of bytes read from this memory -system.physmem.bytes_read::total 137634688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 137579648 # Number of bytes read from this memory +system.physmem.bytes_read::total 137634624 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67105088 # Number of bytes written to this memory -system.physmem.bytes_written::total 67105088 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67105024 # Number of bytes written to this memory +system.physmem.bytes_written::total 67105024 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2149683 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2150542 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048517 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048517 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138781540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138836996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55456 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 67691285 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 67691285 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 67691285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138781540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 206528281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 2149682 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2150541 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1048516 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1048516 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 55193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138123705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138178898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 55193 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 55193 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 67370390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 67370390 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 67370390 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 55193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138123705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 205549288 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444614343 # DTB read hits +system.cpu.dtb.read_hits 444620723 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449511421 # DTB read accesses -system.cpu.dtb.write_hits 160920087 # DTB write hits +system.cpu.dtb.read_accesses 449517801 # DTB read accesses +system.cpu.dtb.write_hits 160920434 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162621391 # DTB write accesses -system.cpu.dtb.data_hits 605534430 # DTB hits +system.cpu.dtb.write_accesses 162621738 # DTB write accesses +system.cpu.dtb.data_hits 605541157 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612132812 # DTB accesses -system.cpu.itb.fetch_hits 232194533 # ITB hits +system.cpu.dtb.data_accesses 612139539 # DTB accesses +system.cpu.itb.fetch_hits 232151959 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 232194555 # ITB accesses +system.cpu.itb.fetch_accesses 232151981 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -67,42 +67,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1982680288 # number of cpu cycles simulated +system.cpu.numCycles 1992122178 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 328915928 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 253819011 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 140072488 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 231593889 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 138169193 # Number of BTB hits +system.cpu.branch_predictor.lookups 328832264 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 253784019 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 139998376 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 232594122 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 138120343 # Number of BTB hits system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 59.660120 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 175201939 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 153713989 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1669764044 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 59.382560 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 175107833 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 153724431 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1669698374 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3045966661 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 236 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3045900991 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 237 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 581 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651015392 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617989806 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 121318277 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 12155753 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 133474030 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 81726039 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.023228 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139614733 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 582 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651085046 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617993265 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 121277812 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 12122106 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 133399918 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 81800180 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.988781 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139625101 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1746574278 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1749883167 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7486032 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 405569141 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1577111147 # Number of cycles cpu stages are processed. -system.cpu.activity 79.544400 # Percentage of cycles cpu is active +system.cpu.timesIdled 7972682 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 415150633 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1576971545 # Number of cycles cpu stages are processed. +system.cpu.activity 79.160383 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -114,144 +114,144 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.089516 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.094705 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.089516 # CPI: Total CPI of All Threads -system.cpu.ipc 0.917838 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.094705 # CPI: Total CPI of All Threads +system.cpu.ipc 0.913488 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.917838 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 791779407 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1190900881 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 60.065200 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1050371352 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 932308936 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 47.022656 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1008674680 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 974005608 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 49.125702 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1572973951 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409706337 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.664266 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 959730175 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1022950113 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.594305 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.913488 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 801357098 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1190765080 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 59.773697 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1059714238 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 932407940 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 46.804757 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1018188148 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 973934030 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 48.889272 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1582467246 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409654932 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.563745 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 969329070 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1022793108 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 51.341887 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 666.725255 # Cycle average of tags in use -system.cpu.icache.total_refs 232193463 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 666.783228 # Cycle average of tags in use +system.cpu.icache.total_refs 232150871 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270306.708964 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 270257.125728 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 666.725255 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.325549 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.325549 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 232193463 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 232193463 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 232193463 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 232193463 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 232193463 # number of overall hits -system.cpu.icache.overall_hits::total 232193463 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1067 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1067 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1067 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1067 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1067 # number of overall misses -system.cpu.icache.overall_misses::total 1067 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58495000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58495000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58495000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58495000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58495000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58495000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 232194530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 232194530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 232194530 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 232194530 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 232194530 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 232194530 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 666.783228 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.325578 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.325578 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 232150871 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 232150871 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 232150871 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 232150871 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 232150871 # number of overall hits +system.cpu.icache.overall_hits::total 232150871 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1085 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1085 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1085 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1085 # number of overall misses +system.cpu.icache.overall_misses::total 1085 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60468000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60468000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60468000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60468000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60468000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60468000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 232151956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 232151956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 232151956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 232151956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 232151956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 232151956 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54821.930647 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54821.930647 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54821.930647 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54821.930647 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54821.930647 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54821.930647 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55730.875576 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55730.875576 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55730.875576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55730.875576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55730.875576 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 85000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 114500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 28333.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 22900 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 208 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 208 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 208 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 226 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 226 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 226 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 226 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 859 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47379000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47379000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47379000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53474.970896 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53474.970896 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53474.970896 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53474.970896 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53474.970896 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53474.970896 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55155.995343 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55155.995343 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55155.995343 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55155.995343 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107366 # number of replacements -system.cpu.dcache.tagsinuse 4082.290547 # Cycle average of tags in use -system.cpu.dcache.total_refs 595076211 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111462 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.310727 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12667784000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.290547 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996653 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996653 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 437271439 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437271439 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 157804772 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 157804772 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 595076211 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 595076211 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 595076211 # number of overall hits -system.cpu.dcache.overall_hits::total 595076211 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7324224 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7324224 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2923730 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2923730 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 10247954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10247954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10247954 # number of overall misses -system.cpu.dcache.overall_misses::total 10247954 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 162150578000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 162150578000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 105068682500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 105068682500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 267219260500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 267219260500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 267219260500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 267219260500 # number of overall miss cycles +system.cpu.dcache.replacements 9107309 # number of replacements +system.cpu.dcache.tagsinuse 4082.354199 # Cycle average of tags in use +system.cpu.dcache.total_refs 595073835 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111405 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.310875 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12655884000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.354199 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 437271435 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437271435 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 157802400 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 157802400 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 595073835 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 595073835 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 595073835 # number of overall hits +system.cpu.dcache.overall_hits::total 595073835 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7324228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7324228 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2926102 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2926102 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 10250330 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 10250330 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10250330 # number of overall misses +system.cpu.dcache.overall_misses::total 10250330 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 166496556500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 166496556500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130053734500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130053734500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 296550291000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 296550291000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 296550291000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 296550291000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -262,54 +262,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016474 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016474 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018190 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.018190 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016930 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016930 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016930 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016930 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22138.943047 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22138.943047 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35936.520301 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35936.520301 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26075.376656 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26075.376656 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26075.376656 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26075.376656 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 10790500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7928721000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2625 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 208163 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4110.666667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 38089.002368 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.018205 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.018205 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016934 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016934 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016934 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016934 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22732.301138 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22732.301138 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44446.070062 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44446.070062 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28930.804277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28930.804277 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28930.804277 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 76478500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8150814500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 14619 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 208452 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5231.445379 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39101.637307 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3389687 # number of writebacks -system.cpu.dcache.writebacks::total 3389687 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101944 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 101944 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1034548 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1034548 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1136492 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1136492 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1136492 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1136492 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 3389633 # number of writebacks +system.cpu.dcache.writebacks::total 3389633 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101948 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101948 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1036977 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1036977 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1138925 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1138925 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1138925 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1138925 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 137265020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 137265020500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54890953000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 54890953000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192155973500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 192155973500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 192155973500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 192155973500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889125 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889125 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111405 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111405 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111405 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111405 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 140938235500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 140938235500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71711487500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 71711487500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212649723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 212649723000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212649723000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 212649723000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -318,149 +318,149 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.773869 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.773869 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29055.407579 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29055.407579 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21089.477572 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21089.477572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21089.477572 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21089.477572 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19514.368800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19514.368800 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37960.160127 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37960.160127 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23338.850924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23338.850924 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2133759 # number of replacements -system.cpu.l2cache.tagsinuse 30545.371941 # Cycle average of tags in use -system.cpu.l2cache.total_refs 8448402 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2163450 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 3.905060 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 183782202000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14422.538140 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 34.487886 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 16088.345915 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440141 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001052 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.490977 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.932171 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.data 5860988 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5860988 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3389687 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3389687 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1100791 # 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Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 16092.965953 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.440181 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001047 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.491118 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.932346 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.data 5860987 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5860987 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3389633 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3389633 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1100736 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1100736 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 6961723 # 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number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44957500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112350154500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 112395112000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44957500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112350154500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 112395112000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 2149682 # number of overall misses +system.cpu.l2cache.overall_misses::total 2150541 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46160000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71425674500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 71471834500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41981087000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41981087000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46160000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 113406761500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 113452921500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46160000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 113406761500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 113452921500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7221838 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7222697 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3389687 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3389687 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889624 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889624 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7221839 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7222698 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3389633 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3389633 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889566 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1889566 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111462 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112321 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9111405 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9112264 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111462 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112321 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9111405 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9112264 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188435 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.188436 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.188532 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417455 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.417455 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.417466 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.417466 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.235932 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.236004 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.235933 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.236005 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.235932 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.236004 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52337.019790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52256.438623 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52256.489456 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52275.931661 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52275.931661 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52337.019790 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52263.591655 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52263.620985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52337.019790 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52263.591655 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52263.620985 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::cpu.data 0.235933 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.236005 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53736.903376 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52485.997375 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52486.786477 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53219.435113 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53219.435113 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52755.525935 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53736.903376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52755.133783 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52755.525935 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 3381000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 111 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8292.857143 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30459.459459 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1048517 # number of writebacks -system.cpu.l2cache.writebacks::total 1048517 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1048516 # number of writebacks +system.cpu.l2cache.writebacks::total 1048516 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360850 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1361709 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 788833 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 788833 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1360852 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34481000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54466888500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54501369500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31621283000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31621283000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34481000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86088171500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 86122652500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34481000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86088171500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 86122652500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 2149682 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2150541 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35698000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54780311000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54816009000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32410594000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32410594000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35698000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87190905000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 87226603000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35698000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87190905000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 87226603000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188435 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.188436 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.188532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417455 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417455 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.417466 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.417466 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.236004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.236005 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.236004 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.861467 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40024.167616 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40024.241229 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40086.156385 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40086.156385 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.861467 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40046.914592 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40046.952117 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235933 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.236005 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41557.625146 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40254.422230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40255.244321 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41086.918601 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41086.918601 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41557.625146 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40559.908396 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40560.306918 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |